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From: Marc Zyngier <maz@kernel.org>
To: muhammad.nazim.amirul.nazle.asmade@altera.com
Cc: tglx@kernel.org, catalin.marinas@arm.com, will@kernel.org,
	heiko@sntech.de, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
	adrian.ho.yin.ng@altera.com
Subject: Re: [PATCH] irqchip/gic-v3-its: Add Altera Agilex5 DMA workaround
Date: Mon, 22 Jun 2026 08:08:08 +0100	[thread overview]
Message-ID: <861pdzrr1j.wl-maz@kernel.org> (raw)
In-Reply-To: <20260622024945.21354-1-muhammad.nazim.amirul.nazle.asmade@altera.com>

On Mon, 22 Jun 2026 03:49:45 +0100,
muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> 
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Altera Agilex5 GIC600 integration has DDR addressing limitation where
> only the first 40 bits of physical address can be accessible. Extend
> existing dma32 quirk in driver to support Agilex5.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

I like the fact that you waited another *year*[1] to post a fixed
version of this change, and couldn't even be bothered to tag this as a
new version, not to mention the lack of Suggested-by: tag for code
that was provided for your perusal.

So you're late to the party, and someone else is doing actual work [2].

Please synchronise with them.

	M.

[1] https://lore.kernel.org/linux-arm-kernel/6a44509ca0edaabc17e59d2e27fef1c782183456.1751618484.git.adrianhoyin.ng@altera.com/
[2] https://lore.kernel.org/r/20260618220427.14325-3-marek.vasut+renesas@mailbox.org

-- 
Without deviation from the norm, progress is not possible.

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: muhammad.nazim.amirul.nazle.asmade@altera.com
Cc: tglx@kernel.org, catalin.marinas@arm.com, will@kernel.org,
	heiko@sntech.de, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
	adrian.ho.yin.ng@altera.com
Subject: Re: [PATCH] irqchip/gic-v3-its: Add Altera Agilex5 DMA workaround
Date: Mon, 22 Jun 2026 08:08:08 +0100	[thread overview]
Message-ID: <861pdzrr1j.wl-maz@kernel.org> (raw)
In-Reply-To: <20260622024945.21354-1-muhammad.nazim.amirul.nazle.asmade@altera.com>

On Mon, 22 Jun 2026 03:49:45 +0100,
muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> 
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Altera Agilex5 GIC600 integration has DDR addressing limitation where
> only the first 40 bits of physical address can be accessible. Extend
> existing dma32 quirk in driver to support Agilex5.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

I like the fact that you waited another *year*[1] to post a fixed
version of this change, and couldn't even be bothered to tag this as a
new version, not to mention the lack of Suggested-by: tag for code
that was provided for your perusal.

So you're late to the party, and someone else is doing actual work [2].

Please synchronise with them.

	M.

[1] https://lore.kernel.org/linux-arm-kernel/6a44509ca0edaabc17e59d2e27fef1c782183456.1751618484.git.adrianhoyin.ng@altera.com/
[2] https://lore.kernel.org/r/20260618220427.14325-3-marek.vasut+renesas@mailbox.org

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

  reply	other threads:[~2026-06-22  7:08 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-22  2:49 [PATCH] irqchip/gic-v3-its: Add Altera Agilex5 DMA workaround muhammad.nazim.amirul.nazle.asmade
2026-06-22  2:49 ` muhammad.nazim.amirul.nazle.asmade
2026-06-22  7:08 ` Marc Zyngier [this message]
2026-06-22  7:08   ` Marc Zyngier
2026-06-22  7:46   ` Nazle Asmade, Muhammad Nazim Amirul
2026-06-22  7:46     ` Nazle Asmade, Muhammad Nazim Amirul

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