[PATCH] irqchip/gic-v3-its: Add Altera Agilex5 DMA workaround

* [PATCH] irqchip/gic-v3-its: Add Altera Agilex5 DMA workaround
@ 2026-06-22  2:49 ` muhammad.nazim.amirul.nazle.asmade
  0 siblings, 0 replies; 6+ messages in thread
From: muhammad.nazim.amirul.nazle.asmade @ 2026-06-22  2:49 UTC (permalink / raw)
  To: maz, tglx
  Cc: catalin.marinas, will, heiko, linux-arm-kernel, linux-kernel,
	linux-rockchip, adrian.ho.yin.ng

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Altera Agilex5 GIC600 integration has DDR addressing limitation where
only the first 40 bits of physical address can be accessible. Extend
existing dma32 quirk in driver to support Agilex5.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
 arch/arm64/Kconfig               | 11 +++++++++++
 drivers/irqchip/irq-gic-v3-its.c | 22 +++++++++++++++-------
 2 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index b3afe0688919..5d3216b718fe 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1391,6 +1391,17 @@ config ROCKCHIP_ERRATUM_3568002
 
 	  If unsure, say Y.
 
+config ALTERA_SOCFPGA_AGILEX5_ERRATUM
+	bool "Altera SoCFPGA Agilex5: GIC600 can not access physical addresses higher than 4GB"
+	default y
+	help
+	  On SoCFPGA Agilex5 platforms, the integrated GIC600 is limited to
+	  32-bit AXI addressing and cannot access memory above 4GB. As a
+	  result, any GIC-visible resources placed outside this range may
+	  not be accessible and can lead to incorrect operation.
+
+	  If unsure, say Y.
+
 config ROCKCHIP_ERRATUM_3588001
 	bool "Rockchip 3588001: GIC600 can not support shareability attributes"
 	default y
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index b57d81ad33a0..db69e6ec98d8 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -4890,10 +4890,20 @@ static bool __maybe_unused its_enable_quirk_hip09_162100801(void *data)
 	return true;
 }
 
-static bool __maybe_unused its_enable_rk3568002(void *data)
+static bool __maybe_unused its_enable_dma32_quirk(void *data)
 {
-	if (!of_machine_is_compatible("rockchip,rk3566") &&
-	    !of_machine_is_compatible("rockchip,rk3568"))
+	static const char * const compatible[] = {
+#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002
+		"rockchip,rk3566",
+		"rockchip,rk3568",
+#endif
+#ifdef CONFIG_ALTERA_SOCFPGA_AGILEX5_ERRATUM
+		"intel,socfpga-agilex5",
+#endif
+		NULL
+	};
+
+	if (!of_machine_compatible_match(compatible))
 		return false;
 
 	gfp_flags_quirk |= GFP_DMA32;
@@ -4968,14 +4978,12 @@ static const struct gic_quirk its_quirks[] = {
 		.property = "dma-noncoherent",
 		.init   = its_set_non_coherent,
 	},
-#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002
 	{
-		.desc   = "ITS: Rockchip erratum RK3568002",
+		.desc   = "ITS: GIC600 integration limited to 32bit",
 		.iidr   = 0x0201743b,
 		.mask   = 0xffffffff,
-		.init   = its_enable_rk3568002,
+		.init   = its_enable_dma32_quirk,
 	},
-#endif
 	{
 	}
 };
-- 
2.43.7


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