From: Keith Packard <keithp@keithp.com>
To: "Lespiau, Damien" <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Daniel Vetter <daniel.vetter@ffwll.ch>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 6/7] drm/i915: Disable FDI RX before FDI TX
Date: Fri, 17 Aug 2012 16:10:57 -0700 [thread overview]
Message-ID: <86393lunb2.fsf@miki.keithp.com> (raw)
In-Reply-To: <CAPX-8+_bZNyXL0b8nBkN97sj-KnT_eZXZ-5Hp5R6P-L-D-QAKg@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1044 bytes --]
"Lespiau, Damien" <damien.lespiau@intel.com> writes:
> I can't see anything in the docs about an order requirement for those.
Right, the docs don't say anything, which is a bit disconcerting.
> Not sure why the other way does not make sense. Somehow disabling TX
> before RX makes some sense to me (TX enabled without a ready RX looks
> weird?, no data should flow as the pipe is shutdown at that point
> anyway). Maybe it just does not matter?
And here I figured disabling RX before TX made more sense -- otherwise
the receiver wouldn't be seeing anything. In other areas of the driver,
we're careful to disable receivers before senders (disable CRTC before
PLL, etc).
> Another detail is that disabling the PLLs seem to have an order in the
> disabling sequence, TX, then RX.
>
> I. Disable CPU FDI Transmitter PLL
> II. Disable PCH FDI Receiver PLL
That ordering doesn't matter as the FDI receiver and transmitter are
both disabled by that point, so they aren't talking at all.
--
keith.packard@intel.com
[-- Attachment #2: Type: application/pgp-signature, Size: 827 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Keith Packard <keithp@keithp.com>
To: "Lespiau\, Damien" <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Daniel Vetter <daniel.vetter@ffwll.ch>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 6/7] drm/i915: Disable FDI RX before FDI TX
Date: Fri, 17 Aug 2012 16:10:57 -0700 [thread overview]
Message-ID: <86393lunb2.fsf@miki.keithp.com> (raw)
In-Reply-To: <CAPX-8+_bZNyXL0b8nBkN97sj-KnT_eZXZ-5Hp5R6P-L-D-QAKg@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1044 bytes --]
"Lespiau, Damien" <damien.lespiau@intel.com> writes:
> I can't see anything in the docs about an order requirement for those.
Right, the docs don't say anything, which is a bit disconcerting.
> Not sure why the other way does not make sense. Somehow disabling TX
> before RX makes some sense to me (TX enabled without a ready RX looks
> weird?, no data should flow as the pipe is shutdown at that point
> anyway). Maybe it just does not matter?
And here I figured disabling RX before TX made more sense -- otherwise
the receiver wouldn't be seeing anything. In other areas of the driver,
we're careful to disable receivers before senders (disable CRTC before
PLL, etc).
> Another detail is that disabling the PLLs seem to have an order in the
> disabling sequence, TX, then RX.
>
> I. Disable CPU FDI Transmitter PLL
> II. Disable PCH FDI Receiver PLL
That ordering doesn't matter as the FDI receiver and transmitter are
both disabled by that point, so they aren't talking at all.
--
keith.packard@intel.com
[-- Attachment #2: Type: application/pgp-signature, Size: 827 bytes --]
next prev parent reply other threads:[~2012-08-17 23:10 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-14 4:34 [PATCH 0/7] drm/i915: IVB FDI B/C fixes and misc cleanups Keith Packard
2012-08-14 4:34 ` [PATCH 1/7] drm/i915: Allow VGA on CRTC 2 Keith Packard
2012-08-15 22:42 ` Daniel Vetter
2012-08-14 4:34 ` [PATCH 2/7] drm/i915: FDI B/C share 4 lanes on Ivybridge Keith Packard
2012-08-17 14:45 ` [Intel-gfx] " Lespiau, Damien
2012-08-17 15:00 ` Keith Packard
2012-08-17 15:00 ` [Intel-gfx] " Keith Packard
2012-08-17 15:12 ` Lespiau, Damien
2012-08-14 4:34 ` [PATCH 3/7] drm/i915: Delay between FDI link training tries. Clear FDI_RX_IIR before training Keith Packard
2012-08-17 15:34 ` [Intel-gfx] " Lespiau, Damien
2012-08-14 4:34 ` [PATCH 4/7] drm/i915: Check display_bpc against max_fdi_bpp after display_bpc is set Keith Packard
2012-08-17 14:58 ` Lespiau, Damien
2012-08-17 14:58 ` [Intel-gfx] " Lespiau, Damien
2012-08-14 4:34 ` [PATCH 5/7] drm/i915: Pipe-C only configurations would not get SR Keith Packard
2012-08-17 15:50 ` [Intel-gfx] " Lespiau, Damien
2012-08-14 4:34 ` [PATCH 6/7] drm/i915: Disable FDI RX before FDI TX Keith Packard
2012-08-17 16:43 ` Lespiau, Damien
2012-08-17 16:43 ` [Intel-gfx] " Lespiau, Damien
2012-08-17 23:10 ` Keith Packard [this message]
2012-08-17 23:10 ` Keith Packard
2012-08-14 4:34 ` [PATCH 7/7] drm/i915: Merge FDI RX reg writes during training Keith Packard
2012-08-17 17:14 ` [Intel-gfx] " Lespiau, Damien
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=86393lunb2.fsf@miki.keithp.com \
--to=keithp@keithp.com \
--cc=damien.lespiau@intel.com \
--cc=daniel.vetter@ffwll.ch \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=linux-kernel@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.