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From: Keith Packard <keithp@keithp.com>
To: "Lespiau, Damien" <damien.lespiau@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
	intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 2/7] drm/i915: FDI B/C share 4 lanes on Ivybridge
Date: Fri, 17 Aug 2012 08:00:58 -0700	[thread overview]
Message-ID: <86lihdbm1h.fsf@miki.keithp.com> (raw)
In-Reply-To: <CAPX-8+8euppecLhZu3XR95uM5e9m_kYmbJ6vmgBU=d03cs=RWA@mail.gmail.com>


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"Lespiau, Damien" <damien.lespiau@intel.com> writes:

> On Tue, Aug 14, 2012 at 5:34 AM, Keith Packard <keithp@keithp.com> wrote:
>
> @@ -3728,7 +3728,8 @@ static inline bool intel_panel_use_ssc(struct
> drm_i915_private *dev_priv)
>   */
>  static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
>                                          unsigned int *pipe_bpp,
> -                                        struct drm_display_mode *mode)
> +                                        struct drm_display_mode *mode,
> +                                        int max_fdi_bpp)
>
> There's some kernel-doc for this function, maybe add a @max_fdi_bpp
> there?

Will do

> This chunk is being moved around in a later patch in the series,
> merging the two patches in one looks like a good idea?

Or at least move this into its final position in this patch.

> I guess this does not cover the case of pipe B using 3 lanes meaning
> pipe C can use 1?

It didn't look like that was a supported mode from the docs.

> This duplicates the code just that is just a few lines away, instead
> how about moving the logic to set target_clock up in front of this
> whole if()?

It's not the same, it's the inverse -- computing bpp from lanes+clock
clock instead of computing lanes from bpp+clock. But, yeah, it would be
nice to have these merged somehow. I couldn't figure out a good way though.

> This chunk is also reworked in a later commit in this series.

I'll see if I can't avoid that as it's confusing. Thanks for your review!

-- 
keith.packard@intel.com

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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WARNING: multiple messages have this Message-ID (diff)
From: Keith Packard <keithp@keithp.com>
To: "Lespiau\, Damien" <damien.lespiau@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/7] drm/i915: FDI B/C share 4 lanes on Ivybridge
Date: Fri, 17 Aug 2012 08:00:58 -0700	[thread overview]
Message-ID: <86lihdbm1h.fsf@miki.keithp.com> (raw)
In-Reply-To: <CAPX-8+8euppecLhZu3XR95uM5e9m_kYmbJ6vmgBU=d03cs=RWA@mail.gmail.com>

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"Lespiau, Damien" <damien.lespiau@intel.com> writes:

> On Tue, Aug 14, 2012 at 5:34 AM, Keith Packard <keithp@keithp.com> wrote:
>
> @@ -3728,7 +3728,8 @@ static inline bool intel_panel_use_ssc(struct
> drm_i915_private *dev_priv)
>   */
>  static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
>                                          unsigned int *pipe_bpp,
> -                                        struct drm_display_mode *mode)
> +                                        struct drm_display_mode *mode,
> +                                        int max_fdi_bpp)
>
> There's some kernel-doc for this function, maybe add a @max_fdi_bpp
> there?

Will do

> This chunk is being moved around in a later patch in the series,
> merging the two patches in one looks like a good idea?

Or at least move this into its final position in this patch.

> I guess this does not cover the case of pipe B using 3 lanes meaning
> pipe C can use 1?

It didn't look like that was a supported mode from the docs.

> This duplicates the code just that is just a few lines away, instead
> how about moving the logic to set target_clock up in front of this
> whole if()?

It's not the same, it's the inverse -- computing bpp from lanes+clock
clock instead of computing lanes from bpp+clock. But, yeah, it would be
nice to have these merged somehow. I couldn't figure out a good way though.

> This chunk is also reworked in a later commit in this series.

I'll see if I can't avoid that as it's confusing. Thanks for your review!

-- 
keith.packard@intel.com

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  reply	other threads:[~2012-08-17 15:00 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-08-14  4:34 [PATCH 0/7] drm/i915: IVB FDI B/C fixes and misc cleanups Keith Packard
2012-08-14  4:34 ` [PATCH 1/7] drm/i915: Allow VGA on CRTC 2 Keith Packard
2012-08-15 22:42   ` Daniel Vetter
2012-08-14  4:34 ` [PATCH 2/7] drm/i915: FDI B/C share 4 lanes on Ivybridge Keith Packard
2012-08-17 14:45   ` [Intel-gfx] " Lespiau, Damien
2012-08-17 15:00     ` Keith Packard [this message]
2012-08-17 15:00       ` Keith Packard
2012-08-17 15:12       ` Lespiau, Damien
2012-08-14  4:34 ` [PATCH 3/7] drm/i915: Delay between FDI link training tries. Clear FDI_RX_IIR before training Keith Packard
2012-08-17 15:34   ` [Intel-gfx] " Lespiau, Damien
2012-08-14  4:34 ` [PATCH 4/7] drm/i915: Check display_bpc against max_fdi_bpp after display_bpc is set Keith Packard
2012-08-17 14:58   ` Lespiau, Damien
2012-08-17 14:58     ` [Intel-gfx] " Lespiau, Damien
2012-08-14  4:34 ` [PATCH 5/7] drm/i915: Pipe-C only configurations would not get SR Keith Packard
2012-08-17 15:50   ` [Intel-gfx] " Lespiau, Damien
2012-08-14  4:34 ` [PATCH 6/7] drm/i915: Disable FDI RX before FDI TX Keith Packard
2012-08-17 16:43   ` Lespiau, Damien
2012-08-17 16:43     ` [Intel-gfx] " Lespiau, Damien
2012-08-17 23:10     ` Keith Packard
2012-08-17 23:10       ` Keith Packard
2012-08-14  4:34 ` [PATCH 7/7] drm/i915: Merge FDI RX reg writes during training Keith Packard
2012-08-17 17:14   ` [Intel-gfx] " Lespiau, Damien

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