[PATCH v2 0/4] arm64: add R8A78000 support

[PATCH v2 0/4] arm64: add R8A78000 support

[Kuninori Morimoto]

Hi Geert

This is v2 of R8A78000 support for Renesas.

This patch-set adds R8A78000 and Ironhide board support.
It is based on SDK v4.28.0 or later. It will be released at end of Oct.

Link: https://lore.kernel.org/r/87tt1c9z7h.wl-kuninori.morimoto.gx@renesas.com

v1 -> v2
	- Add Krzysztof's Acked-by on [1/4]
	- Tidyup "cache" properties on [3/4]
	- Add "clock-" prefix on fixed-clock [3/4]
	- remove un-needed clock-frequency [3/4]
	- use "-" instead of "_" on dummy-clk-sgasyncd4 [3/4]
	- use "0" instead of "0x0" for gic [3/4]
	- cleanup "bootargs" [4/4]

Duy Nguyen (1):
  soc: renesas: Identify R-Car X5H

Hai Pham (2):
  arm64: dts: renesas: Add R8A78000 X5H DTs
  arm64: renesas: Add R8A78000 Ironhide board code

Kuninori Morimoto (1):
  dt-bindings: soc: renesas: Document R-Car X5H Ironhide

 .../bindings/soc/renesas/renesas.yaml         |    6 +
 arch/arm64/boot/dts/renesas/Makefile          |    2 +
 .../boot/dts/renesas/r8a78000-ironhide.dts    |   87 ++
 arch/arm64/boot/dts/renesas/r8a78000.dtsi     | 1063 +++++++++++++++++
 drivers/soc/renesas/Kconfig                   |   12 +
 drivers/soc/renesas/renesas-soc.c             |   12 +
 6 files changed, 1182 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a78000.dtsi

-- 
2.43.0

[PATCH v2 1/4] dt-bindings: soc: renesas: Document R-Car X5H Ironhide

[Kuninori Morimoto]

Document the compatible values for the Renesas R-Car X5H (R8A78000) SoC,
as used on the Renesas Ironhide board.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index 5f9d541d177a..f4947ac65460 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -473,6 +473,12 @@ properties:
           - const: renesas,r8a779mb
           - const: renesas,r8a7795
 
+      - description: R-Car X5H (R8A78000)
+        items:
+          - enum:
+              - renesas,ironhide    # Ironhide (RTP8A78000ASKB0F10S)
+          - const: renesas,r8a78000
+
       - description: RZ/N1D (R9A06G032)
         items:
           - enum:
-- 
2.43.0

Re: [PATCH v2 1/4] dt-bindings: soc: renesas: Document R-Car X5H Ironhide

[Geert Uytterhoeven]

On Wed, 10 Sept 2025 at 04:01, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> Document the compatible values for the Renesas R-Car X5H (R8A78000) SoC,
> as used on the Renesas Ironhide board.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 2/4] soc: renesas: Identify R-Car X5H

[Kuninori Morimoto]

From: Duy Nguyen <duy.nguyen.rh@renesas.com>

Add support for identifying the R-Car X5H SoC.

[Kuninori: tidyup for upstreaming]

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/soc/renesas/Kconfig       | 12 ++++++++++++
 drivers/soc/renesas/renesas-soc.c | 12 ++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 719b7f4f376f..7229f4afb3fa 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -39,6 +39,10 @@ config ARCH_RCAR_GEN4
 	bool
 	select ARCH_RCAR_GEN3
 
+config ARCH_RCAR_GEN5
+	bool
+	select ARCH_RCAR_GEN4
+
 config ARCH_RMOBILE
 	bool
 	select PM
@@ -348,6 +352,14 @@ config ARCH_R8A779H0
 	help
 	  This enables support for the Renesas R-Car V4M SoC.
 
+config ARCH_R8A78000
+	bool "ARM64 Platform support for R8A78000 (R-Car X5H)"
+	default y if ARCH_RENESAS
+	default ARCH_RENESAS
+	select ARCH_RCAR_GEN5
+	help
+	  This enables support for the Renesas R-Car X5H SoC.
+
 config ARCH_R9A07G043
 	bool "ARM64 Platform support for R9A07G043U (RZ/G2UL)"
 	default y if ARCH_RENESAS
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index df2b38417b80..1eb52356b996 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -36,6 +36,10 @@ static const struct renesas_family fam_rcar_gen4 __initconst __maybe_unused = {
 	.name	= "R-Car Gen4",
 };
 
+static const struct renesas_family fam_rcar_gen5 __initconst __maybe_unused = {
+	.name   = "R-Car Gen5",
+};
+
 static const struct renesas_family fam_rmobile __initconst __maybe_unused = {
 	.name	= "R-Mobile",
 	.reg	= 0xe600101c,		/* CCCR (Common Chip Code Register) */
@@ -266,6 +270,11 @@ static const struct renesas_soc soc_rcar_v4m __initconst __maybe_unused = {
 	.id     = 0x5d,
 };
 
+static const struct renesas_soc soc_rcar_x5h __initconst __maybe_unused = {
+	.family = &fam_rcar_gen5,
+	.id     = 0x60,
+};
+
 static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
 	.family	= &fam_shmobile,
 	.id	= 0x37,
@@ -378,6 +387,9 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = {
 #ifdef CONFIG_ARCH_R8A779H0
 	{ .compatible = "renesas,r8a779h0",	.data = &soc_rcar_v4m },
 #endif
+#ifdef CONFIG_ARCH_R8A78000
+	{ .compatible = "renesas,r8a78000",	.data = &soc_rcar_x5h },
+#endif
 #ifdef CONFIG_ARCH_R9A07G043
 #ifdef CONFIG_RISCV
 	{ .compatible = "renesas,r9a07g043",	.data = &soc_rz_five },
-- 
2.43.0

Re: [PATCH v2 2/4] soc: renesas: Identify R-Car X5H

[Geert Uytterhoeven]

On Wed, 10 Sept 2025 at 04:01, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Duy Nguyen <duy.nguyen.rh@renesas.com>
>
> Add support for identifying the R-Car X5H SoC.
>
> [Kuninori: tidyup for upstreaming]
>
> Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
> Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, will queue in renesas-devel for v6.18.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Kuninori Morimoto]

From: Hai Pham <hai.pham.ud@renesas.com>

Add initial DT support for R8A78000 (R-Car X5H) SoC.

[Kuninori: tidyup for upstreaming]

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
Signed-off-by: Minh Le <minh.le.aj@renesas.com>
Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 1063 +++++++++++++++++++++
 1 file changed, 1063 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a78000.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
new file mode 100644
index 000000000000..165c4e9fcf3b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -0,0 +1,1063 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car X5H (R8A78000) SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r8a78000";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&a720_0>;
+				};
+				core1 {
+					cpu = <&a720_1>;
+				};
+				core2 {
+					cpu = <&a720_2>;
+				};
+				core3 {
+					cpu = <&a720_3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&a720_4>;
+				};
+				core1 {
+					cpu = <&a720_5>;
+				};
+				core2 {
+					cpu = <&a720_6>;
+				};
+				core3 {
+					cpu = <&a720_7>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&a720_8>;
+				};
+				core1 {
+					cpu = <&a720_9>;
+				};
+				core2 {
+					cpu = <&a720_10>;
+				};
+				core3 {
+					cpu = <&a720_11>;
+				};
+			};
+
+			cluster3 {
+				core0 {
+					cpu = <&a720_12>;
+				};
+				core1 {
+					cpu = <&a720_13>;
+				};
+				core2 {
+					cpu = <&a720_14>;
+				};
+				core3 {
+					cpu = <&a720_15>;
+				};
+			};
+
+			cluster4 {
+				core0 {
+					cpu = <&a720_16>;
+				};
+				core1 {
+					cpu = <&a720_17>;
+				};
+				core2 {
+					cpu = <&a720_18>;
+				};
+				core3 {
+					cpu = <&a720_19>;
+				};
+			};
+
+			cluster5 {
+				core0 {
+					cpu = <&a720_20>;
+				};
+				core1 {
+					cpu = <&a720_21>;
+				};
+				core2 {
+					cpu = <&a720_22>;
+				};
+				core3 {
+					cpu = <&a720_23>;
+				};
+			};
+
+			cluster6 {
+				core0 {
+					cpu = <&a720_24>;
+				};
+				core1 {
+					cpu = <&a720_25>;
+				};
+				core2 {
+					cpu = <&a720_26>;
+				};
+				core3 {
+					cpu = <&a720_27>;
+				};
+			};
+
+			cluster7 {
+				core0 {
+					cpu = <&a720_28>;
+				};
+				core1 {
+					cpu = <&a720_29>;
+				};
+				core2 {
+					cpu = <&a720_30>;
+				};
+				core3 {
+					cpu = <&a720_31>;
+				};
+			};
+		};
+
+		a720_0: cpu@0 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x0>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_0>;
+			enable-method = "psci";
+
+			L1_CA720_0: controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_0>;
+			};
+
+			L2_CA720_0: controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_0>;
+			};
+		};
+
+		a720_1: cpu@100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_1>;
+			enable-method = "psci";
+
+			L1_CA720_1: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_1>;
+			};
+
+			L2_CA720_1: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_0>;
+			};
+		};
+
+		a720_2: cpu@200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_2>;
+			enable-method = "psci";
+
+			L1_CA720_2: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_2>;
+			};
+
+			L2_CA720_2: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_0>;
+			};
+		};
+
+		a720_3: cpu@300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_3>;
+			enable-method = "psci";
+
+			L1_CA720_3: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_3>;
+			};
+
+			L2_CA720_3: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_0>;
+			};
+		};
+
+		a720_4: cpu@10000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x10000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_4>;
+			enable-method = "psci";
+
+			L1_CA720_4: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_4>;
+			};
+
+			L2_CA720_4: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_1>;
+			};
+		};
+
+		a720_5: cpu@10100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x10100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_5>;
+			enable-method = "psci";
+
+			L1_CA720_5: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_5>;
+			};
+
+			L2_CA720_5: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_1>;
+			};
+		};
+
+		a720_6: cpu@10200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x10200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_6>;
+			enable-method = "psci";
+
+			L1_CA720_6: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_6>;
+			};
+
+			L2_CA720_6: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_1>;
+			};
+		};
+
+		a720_7: cpu@10300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x10300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_7>;
+			enable-method = "psci";
+
+			L1_CA720_7: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_7>;
+			};
+
+			L2_CA720_7: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_1>;
+			};
+		};
+
+		a720_8: cpu@20000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x20000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_8>;
+			enable-method = "psci";
+
+			L1_CA720_8: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_8>;
+			};
+
+			L2_CA720_8: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_2>;
+			};
+		};
+
+		a720_9: cpu@20100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x20100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_9>;
+			enable-method = "psci";
+
+			L1_CA720_9: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_9>;
+			};
+
+			L2_CA720_9: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_2>;
+			};
+		};
+
+		a720_10: cpu@20200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x20200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_10>;
+			enable-method = "psci";
+
+			L1_CA720_10: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_10>;
+			};
+
+			L2_CA720_10: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_2>;
+			};
+		};
+
+		a720_11: cpu@20300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x20300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_11>;
+			enable-method = "psci";
+
+			L1_CA720_11: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_11>;
+			};
+
+			L2_CA720_11: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_2>;
+			};
+		};
+
+		a720_12: cpu@30000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x30000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_12>;
+			enable-method = "psci";
+
+			L1_CA720_12: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_12>;
+			};
+
+			L2_CA720_12: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_3>;
+			};
+		};
+
+		a720_13: cpu@30100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x30100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_13>;
+			enable-method = "psci";
+
+			L1_CA720_13: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_13>;
+			};
+
+			L2_CA720_13: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_3>;
+			};
+		};
+
+		a720_14: cpu@30200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x30200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_14>;
+			enable-method = "psci";
+
+			L1_CA720_14: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_14>;
+			};
+
+			L2_CA720_14: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_3>;
+			};
+		};
+
+		a720_15: cpu@30300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x30300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_15>;
+			enable-method = "psci";
+
+			L1_CA720_15: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_15>;
+			};
+
+			L2_CA720_15: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_3>;
+			};
+		};
+
+		a720_16: cpu@40000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x40000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_16>;
+			enable-method = "psci";
+
+			L1_CA720_16: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_16>;
+			};
+
+			L2_CA720_16: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_4>;
+			};
+		};
+
+		a720_17: cpu@40100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x40100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_17>;
+			enable-method = "psci";
+
+			L1_CA720_17: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_17>;
+			};
+
+			L2_CA720_17: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_4>;
+			};
+		};
+
+		a720_18: cpu@40200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x40200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_18>;
+			enable-method = "psci";
+
+			L1_CA720_18: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_18>;
+			};
+
+			L2_CA720_18: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_4>;
+			};
+		};
+
+		a720_19: cpu@40300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x40300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_19>;
+			enable-method = "psci";
+
+			L1_CA720_19: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_19>;
+			};
+
+			L2_CA720_19: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_4>;
+			};
+		};
+
+		a720_20: cpu@50000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x50000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_20>;
+			enable-method = "psci";
+
+			L1_CA720_20: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_20>;
+			};
+
+			L2_CA720_20: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_5>;
+			};
+		};
+
+		a720_21: cpu@50100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x50100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_21>;
+			enable-method = "psci";
+
+			L1_CA720_21: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_21>;
+			};
+
+			L2_CA720_21: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_5>;
+			};
+		};
+
+		a720_22: cpu@50200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x50200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_22>;
+			enable-method = "psci";
+
+			L1_CA720_22: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_22>;
+			};
+
+			L2_CA720_22: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_5>;
+			};
+		};
+
+		a720_23: cpu@50300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x50300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_23>;
+			enable-method = "psci";
+
+			L1_CA720_23: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_23>;
+			};
+
+			L2_CA720_23: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_5>;
+			};
+		};
+
+		a720_24: cpu@60000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x60000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_24>;
+			enable-method = "psci";
+
+			L1_CA720_24: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_24>;
+			};
+
+			L2_CA720_24: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_6>;
+			};
+		};
+
+		a720_25: cpu@60100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x60100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_25>;
+			enable-method = "psci";
+
+			L1_CA720_25: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_25>;
+			};
+
+			L2_CA720_25: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_6>;
+			};
+		};
+
+		a720_26: cpu@60200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x60200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_26>;
+			enable-method = "psci";
+
+			L1_CA720_26: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_26>;
+			};
+
+			L2_CA720_26: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_6>;
+			};
+		};
+
+		a720_27: cpu@60300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x60300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_27>;
+			enable-method = "psci";
+
+			L1_CA720_27: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_27>;
+			};
+
+			L2_CA720_27: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_6>;
+			};
+		};
+
+		a720_28: cpu@70000 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x70000>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_28>;
+			enable-method = "psci";
+
+			L1_CA720_28: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_28>;
+			};
+
+			L2_CA720_28: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_7>;
+			};
+		};
+
+		a720_29: cpu@70100 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x70100>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_29>;
+			enable-method = "psci";
+
+			L1_CA720_29: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_29>;
+			};
+
+			L2_CA720_29: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_7>;
+			};
+		};
+
+		a720_30: cpu@70200 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x70200>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_30>;
+			enable-method = "psci";
+
+			L1_CA720_30: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_30>;
+			};
+
+			L2_CA720_30: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_7>;
+			};
+		};
+
+		a720_31: cpu@70300 {
+			compatible = "arm,cortex-a720";
+			reg = <0x0 0x70300>;
+			device_type = "cpu";
+			next-level-cache = <&L1_CA720_31>;
+			enable-method = "psci";
+
+			L1_CA720_31: cache-controller-0 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <1>;
+				next-level-cache = <&L2_CA720_31>;
+			};
+
+			L2_CA720_31: cache-controller-1 {
+				compatible = "cache";
+				cache-unified;
+				cache-level = <2>;
+				next-level-cache = <&L3_CA720_7>;
+			};
+		};
+
+		L3_CA720_0: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_1: cache-controller-1 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_2: cache-controller-2 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_3: cache-controller-3 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_4: cache-controller-4 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_5: cache-controller-5 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_6: cache-controller-6 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+
+		L3_CA720_7: cache-controller-7 {
+			compatible = "cache";
+			cache-unified;
+			cache-level = <3>;
+		};
+	};
+
+	extal_clk: clock-extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* clock-frequency must be set on board */
+	};
+
+	extalr_clk: clock-extalr {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* clock-frequency must be set on board */
+	};
+
+	/*
+	 * In the early phase, there is no clock control support,
+	 * so assume that the clocks are enabled by default.
+	 * Therefore, dummy clocks are used.
+	 */
+	dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <266660000>;
+	};
+
+	/* External SCIF clock - to be overridden by boards that provide it */
+	scif_clk: clock-scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* clock-frequency must be set on board */
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		prr: chipid@189e0044 {
+			compatible = "renesas,prr";
+			reg = <0 0x189e0044 0 4>;
+		};
+
+		/* The Arm GIC-700AE - View 1 */
+		gic: interrupt-controller@39000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			redistributor-stride = <0x0 0x40000>;
+			#redistributor-regions = <32>;
+			reg = <0 0x39000000 0 0x20000>, // GICD
+			      <0 0x39080000 0 0x40000>, // GICR Core0
+			      <0 0x390C0000 0 0x40000>, // GICR Core1
+			      <0 0x39100000 0 0x40000>, // GICR Core2
+			      <0 0x39140000 0 0x40000>, // GICR Core3
+			      <0 0x39180000 0 0x40000>, // GICR Core4
+			      <0 0x391C0000 0 0x40000>, // GICR Core5
+			      <0 0x39200000 0 0x40000>, // GICR Core6
+			      <0 0x39240000 0 0x40000>, // GICR Core7
+			      <0 0x39280000 0 0x40000>, // GICR Core8
+			      <0 0x392C0000 0 0x40000>, // GICR Core9
+			      <0 0x39300000 0 0x40000>, // GICR Core10
+			      <0 0x39340000 0 0x40000>, // GICR Core11
+			      <0 0x39380000 0 0x40000>, // GICR Core12
+			      <0 0x393C0000 0 0x40000>, // GICR Core13
+			      <0 0x39400000 0 0x40000>, // GICR Core14
+			      <0 0x39440000 0 0x40000>, // GICR Core15
+			      <0 0x39480000 0 0x40000>, // GICR Core16
+			      <0 0x394C0000 0 0x40000>, // GICR Core17
+			      <0 0x39500000 0 0x40000>, // GICR Core18
+			      <0 0x39540000 0 0x40000>, // GICR Core19
+			      <0 0x39580000 0 0x40000>, // GICR Core20
+			      <0 0x395C0000 0 0x40000>, // GICR Core21
+			      <0 0x39600000 0 0x40000>, // GICR Core22
+			      <0 0x39640000 0 0x40000>, // GICR Core23
+			      <0 0x39680000 0 0x40000>, // GICR Core24
+			      <0 0x396C0000 0 0x40000>, // GICR Core25
+			      <0 0x39700000 0 0x40000>, // GICR Core26
+			      <0 0x39740000 0 0x40000>, // GICR Core27
+			      <0 0x39780000 0 0x40000>, // GICR Core28
+			      <0 0x397C0000 0 0x40000>, // GICR Core29
+			      <0 0x39800000 0 0x40000>, // GICR Core30
+			      <0 0x39840000 0 0x40000>; // GICR Core31
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		scif0: serial@c0700000 {
+			compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+			reg = <0 0xc0700000 0 0x40>;
+			interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		scif1: serial@c0704000 {
+			compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+			reg = <0 0xc0704000 0 0x40>;
+			interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		scif3: serial@c0708000 {
+			compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+			reg = <0 0xc0708000 0 0x40>;
+			interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		scif4: serial@c070c000 {
+			compatible = "renesas,rcar-gen5-scif", "renesas,scif";
+			reg = <0 0xc070c000 0 0x40>;
+			interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		hscif0: serial@c0710000 {
+			compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+			reg = <0 0xc0710000 0 0x60>;
+			interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		hscif1: serial@c0714000 {
+			compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+			reg = <0 0xc0714000 0 0x60>;
+			interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		hscif2: serial@c0718000 {
+			compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+			reg = <0 0xc0718000 0 0x60>;
+			interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+
+		hscif3: serial@c071c000 {
+			compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
+			reg = <0 0xc071c000 0 0x60>;
+			interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			status = "disabled";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+				  "hyp-virt";
+	};
+};
-- 
2.43.0

Re: [PATCH v2 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Geert Uytterhoeven]

Hi Morimoto-san,

On Wed, 10 Sept 2025 at 04:01, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Hai Pham <hai.pham.ud@renesas.com>
>
> Add initial DT support for R8A78000 (R-Car X5H) SoC.
>
> [Kuninori: tidyup for upstreaming]
>
> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
> Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
> Signed-off-by: Minh Le <minh.le.aj@renesas.com>
> Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
> Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi

> +/ {

> +       cpus {
> +               #address-cells = <2>;
> +               #size-cells = <0>;

> +               a720_0: cpu@0 {
> +                       compatible = "arm,cortex-a720";

"arm,cortex-a720ae"?

> +                       reg = <0x0 0x0>;
> +                       device_type = "cpu";
> +                       next-level-cache = <&L1_CA720_0>;
> +                       enable-method = "psci";

Please drop this line, as there is no psci node yet.

> +
> +                       L1_CA720_0: controller-0 {

cache-controller (lots of places).

> +                               compatible = "cache";
> +                               cache-unified;

The L1 cache is not unified, according to the documentation?

> +                               cache-level = <1>;

dtschema/schemas/cache-controller.yaml says valid values are 2..32,
so I think you just have to ignore the L1 cache.
I.e. drop it from DTS, and let the CPU's next-level-cache point to
the L2 cache.

> +                               next-level-cache = <&L2_CA720_0>;
> +                       };
> +
> +                       L2_CA720_0: controller-1 {
> +                               compatible = "cache";
> +                               cache-unified;
> +                               cache-level = <2>;
> +                               next-level-cache = <&L3_CA720_0>;
> +                       };

Shouldn't this node be located outside the cpu@0 node?

> +               };

> +
> +       extal_clk: clock-extal {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* clock-frequency must be set on board */
> +       };
> +
> +       extalr_clk: clock-extalr {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* clock-frequency must be set on board */
> +       };
> +
> +       /*
> +        * In the early phase, there is no clock control support,
> +        * so assume that the clocks are enabled by default.
> +        * Therefore, dummy clocks are used.
> +        */
> +       dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {

Perhaps use clock-*, for consistency with extal(r)?
However, please note that so far no Renesas DTS files use "clock-*"
as a node name, but "*-clk" is in active use. Krzysztof?

And don't forget to say "Thank you!" to our SCMI overlords ;-)

> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <266660000>;
> +       };
> +
> +       /* External SCIF clock - to be overridden by boards that provide it */
> +       scif_clk: clock-scif {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* clock-frequency must be set on board */

This clock is optional, and thus may be left unpopulated on a board,
so please (re-)add "clock-frequency = <0>;".

> +       };
> +
> +       soc: soc {

> +               /* The Arm GIC-700AE - View 1 */

s/700/720/

> +               gic: interrupt-controller@39000000 {
> +                       compatible = "arm,gic-v3";

The documentation states it is compliant with GICv4.1?

> +                       #interrupt-cells = <3>;
> +                       #address-cells = <0>;
> +                       interrupt-controller;
> +                       redistributor-stride = <0x0 0x40000>;
> +                       #redistributor-regions = <32>;
> +                       reg = <0 0x39000000 0 0x20000>, // GICD

The base address is 0x38000000, according to the docs?

> +                             <0 0x39080000 0 0x40000>, // GICR Core0
> +                             <0 0x390C0000 0 0x40000>, // GICR Core1
> +                             <0 0x39100000 0 0x40000>, // GICR Core2
> +                             <0 0x39140000 0 0x40000>, // GICR Core3
> +                             <0 0x39180000 0 0x40000>, // GICR Core4
> +                             <0 0x391C0000 0 0x40000>, // GICR Core5
> +                             <0 0x39200000 0 0x40000>, // GICR Core6
> +                             <0 0x39240000 0 0x40000>, // GICR Core7
> +                             <0 0x39280000 0 0x40000>, // GICR Core8
> +                             <0 0x392C0000 0 0x40000>, // GICR Core9
> +                             <0 0x39300000 0 0x40000>, // GICR Core10
> +                             <0 0x39340000 0 0x40000>, // GICR Core11
> +                             <0 0x39380000 0 0x40000>, // GICR Core12
> +                             <0 0x393C0000 0 0x40000>, // GICR Core13
> +                             <0 0x39400000 0 0x40000>, // GICR Core14
> +                             <0 0x39440000 0 0x40000>, // GICR Core15
> +                             <0 0x39480000 0 0x40000>, // GICR Core16
> +                             <0 0x394C0000 0 0x40000>, // GICR Core17
> +                             <0 0x39500000 0 0x40000>, // GICR Core18
> +                             <0 0x39540000 0 0x40000>, // GICR Core19
> +                             <0 0x39580000 0 0x40000>, // GICR Core20
> +                             <0 0x395C0000 0 0x40000>, // GICR Core21
> +                             <0 0x39600000 0 0x40000>, // GICR Core22
> +                             <0 0x39640000 0 0x40000>, // GICR Core23
> +                             <0 0x39680000 0 0x40000>, // GICR Core24
> +                             <0 0x396C0000 0 0x40000>, // GICR Core25
> +                             <0 0x39700000 0 0x40000>, // GICR Core26
> +                             <0 0x39740000 0 0x40000>, // GICR Core27
> +                             <0 0x39780000 0 0x40000>, // GICR Core28
> +                             <0 0x397C0000 0 0x40000>, // GICR Core29
> +                             <0 0x39800000 0 0x40000>, // GICR Core30
> +                             <0 0x39840000 0 0x40000>; // GICR Core31

No GICC, GICH, and GICV?

> +                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +               };
> +
> +               scif0: serial@c0700000 {
> +                       compatible = "renesas,rcar-gen5-scif", "renesas,scif";

Missing "renesas,scif-r8a78000" (everywhere)
("make dtbs_check" would have told you).

> +                       reg = <0 0xc0700000 0 0x40>;
> +                       interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
> +                       clock-names = "fck", "brg_int", "scif_clk";

"fck" on SCIF should be (derived from) SGASYNCD16 (66.666 MHz).

According to the DT bindings, "power-domains" and "resets" are missing.

> +                       status = "disabled";
> +               };

> +               hscif0: serial@c0710000 {
> +                       compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";

Missing "renesas,hscif-r8a78000".

> +                       reg = <0 0xc0710000 0 0x60>;
> +                       interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
> +                       clock-names = "fck", "brg_int", "scif_clk";

"fck" on HSCIF should be (derived from) SGASYNCD8 (133.33 MHz).

According to the DT bindings, "power-domains" and "resets" are missing.

> +                       status = "disabled";
> +               };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Kuninori Morimoto]

Hi Geert

Thank you for your review

> > +               a720_0: cpu@0 {
> > +                       compatible = "arm,cortex-a720";
> 
> "arm,cortex-a720ae"?

OK, will add a720ae support. But I'm not 100% familiar with ARM Cortex,
I assumes A720AE feature itself is same as A720.

> > +                       reg = <0x0 0x0>;
> > +                       device_type = "cpu";
> > +                       next-level-cache = <&L1_CA720_0>;
> > +                       enable-method = "psci";
> 
> Please drop this line, as there is no psci node yet.

OK, will remove

> > +
> > +                       L1_CA720_0: controller-0 {
> 
> cache-controller (lots of places).

Oops, cpu0 part lost "cache-". Will add

> > +                               compatible = "cache";
> > +                               cache-unified;
> 
> The L1 cache is not unified, according to the documentation?
> 
> > +                               cache-level = <1>;
> 
> dtschema/schemas/cache-controller.yaml says valid values are 2..32,
> so I think you just have to ignore the L1 cache.
> I.e. drop it from DTS, and let the CPU's next-level-cache point to
> the L2 cache.

Thanks. Will fix

> > +                       L2_CA720_0: controller-1 {
> > +                               compatible = "cache";
> > +                               cache-unified;
> > +                               cache-level = <2>;
> > +                               next-level-cache = <&L3_CA720_0>;
> > +                       };
> 
> Shouldn't this node be located outside the cpu@0 node?

Sorry, this is my bad. L2 is per core.
I will remove cache-unified, and keep it on each CPU.

> > +       /*
> > +        * In the early phase, there is no clock control support,
> > +        * so assume that the clocks are enabled by default.
> > +        * Therefore, dummy clocks are used.
> > +        */
> > +       dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {
> 
> Perhaps use clock-*, for consistency with extal(r)?
> However, please note that so far no Renesas DTS files use "clock-*"
> as a node name, but "*-clk" is in active use. Krzysztof?

Yeah, "*-clk" is more used to see.

> > +       /* External SCIF clock - to be overridden by boards that provide it */
> > +       scif_clk: clock-scif {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* clock-frequency must be set on board */
> 
> This clock is optional, and thus may be left unpopulated on a board,
> so please (re-)add "clock-frequency = <0>;".

OK, will do

> > +               /* The Arm GIC-700AE - View 1 */
> 
> s/700/720/

Oops, thanks. Will fix

> > +               gic: interrupt-controller@39000000 {
> > +                       compatible = "arm,gic-v3";
> 
> The documentation states it is compliant with GICv4.1?

I'm not familiar with GIC. And I think there is no v4 support on Linux yet ?
If my understanding was correct, GICv4 have GICv3 compatible.
We can use v3 driver so far, and can be replaced to v4 driver if it was
supported in Linux?

> > +                       #interrupt-cells = <3>;
> > +                       #address-cells = <0>;
> > +                       interrupt-controller;
> > +                       redistributor-stride = <0x0 0x40000>;
> > +                       #redistributor-regions = <32>;
> > +                       reg = <0 0x39000000 0 0x20000>, // GICD
> 
> The base address is 0x38000000, according to the docs?

It is indicated in very deep place in datasheet. I will indicate
detail in v2.

> > +                             <0 0x397C0000 0 0x40000>, // GICR Core29
> > +                             <0 0x39800000 0 0x40000>, // GICR Core30
> > +                             <0 0x39840000 0 0x40000>; // GICR Core31
> 
> No GICC, GICH, and GICV?

will be added later ?

> > +               scif0: serial@c0700000 {
> > +                       compatible = "renesas,rcar-gen5-scif", "renesas,scif";
> 
> Missing "renesas,scif-r8a78000" (everywhere)
> ("make dtbs_check" would have told you).

Grr, thank you for pointing it. will fix

> > +                       reg = <0 0xc0700000 0 0x40>;
> > +                       interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
> > +                       clock-names = "fck", "brg_int", "scif_clk";
> 
> "fck" on SCIF should be (derived from) SGASYNCD16 (66.666 MHz).
(snip)
> "fck" on HSCIF should be (derived from) SGASYNCD8 (133.33 MHz).

In the early phase, there is no clock control support, so assume that
the clocks are enabled by default. Therefore, dummy clocks are used.
But indeed the naming seems strange. Will use just "dummy-clk".

> According to the DT bindings, "power-domains" and "resets" are missing.

Unfortunately, can't use for now. It needs SCP support but is under
development. How should I do in this case ? Maybe use dummy device,
but can we use it ??

> > +               hscif0: serial@c0710000 {
> > +                       compatible = "renesas,rcar-gen5-hscif", "renesas,hscif";
> 
> Missing "renesas,hscif-r8a78000".

Grr, thank you for pointing it. will fix


Thank you for your help !!

Best regards
---
Kuninori Morimoto

Re: [PATCH v2 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Geert Uytterhoeven]

Hi Morimoto-san,

CC maz

On Fri, 12 Sept 2025 at 02:39, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> > > +               /* The Arm GIC-700AE - View 1 */
> >
> > s/700/720/
>
> Oops, thanks. Will fix
>
> > > +               gic: interrupt-controller@39000000 {
> > > +                       compatible = "arm,gic-v3";
> >
> > The documentation states it is compliant with GICv4.1?
>
> I'm not familiar with GIC. And I think there is no v4 support on Linux yet ?
> If my understanding was correct, GICv4 have GICv3 compatible.
> We can use v3 driver so far, and can be replaced to v4 driver if it was
> supported in Linux?

'git grep -i "\<gic.*v4.1"' does show support.

Marc?

> > > +                       #interrupt-cells = <3>;
> > > +                       #address-cells = <0>;
> > > +                       interrupt-controller;
> > > +                       redistributor-stride = <0x0 0x40000>;
> > > +                       #redistributor-regions = <32>;
> > > +                       reg = <0 0x39000000 0 0x20000>, // GICD
> >
> > The base address is 0x38000000, according to the docs?
>
> It is indicated in very deep place in datasheet. I will indicate
> detail in v2.
>
> > > +                             <0 0x397C0000 0 0x40000>, // GICR Core29
> > > +                             <0 0x39800000 0 0x40000>, // GICR Core30
> > > +                             <0 0x39840000 0 0x40000>; // GICR Core31
> >
> > No GICC, GICH, and GICV?
>
> will be added later ?

OK.

> > > +               scif0: serial@c0700000 {
> > > +                       compatible = "renesas,rcar-gen5-scif", "renesas,scif";
> >
> > Missing "renesas,scif-r8a78000" (everywhere)
> > ("make dtbs_check" would have told you).
>
> Grr, thank you for pointing it. will fix
>
> > > +                       reg = <0 0xc0700000 0 0x40>;
> > > +                       interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
> > > +                       clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
> > > +                       clock-names = "fck", "brg_int", "scif_clk";
> >
> > "fck" on SCIF should be (derived from) SGASYNCD16 (66.666 MHz).
> (snip)
> > "fck" on HSCIF should be (derived from) SGASYNCD8 (133.33 MHz).
>
> In the early phase, there is no clock control support, so assume that
> the clocks are enabled by default. Therefore, dummy clocks are used.
> But indeed the naming seems strange. Will use just "dummy-clk".

I know.  But currently the clock rate for the dummy "fck" clocks does
not match reality.  As the SCIF driver tries hard to find the best
clock and divider for the requested transfer rate, it might pick "fck",
breaking serial communication.
So please add dummy clocks for SGASYNCD16 and SGASYNCD8, and use them as
"fck" clocks for SCIF resp. HSCIF.

> > According to the DT bindings, "power-domains" and "resets" are missing.
>
> Unfortunately, can't use for now. It needs SCP support but is under
> development. How should I do in this case ? Maybe use dummy device,
> but can we use it ??

Just leave them out for now, but be prepared to receive complaints
from the dtbs_check bots ;-)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Marc Zyngier]

On Fri, 12 Sep 2025 08:37:29 +0100,
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> 
> Hi Morimoto-san,
> 
> CC maz
> 
> On Fri, 12 Sept 2025 at 02:39, Kuninori Morimoto
> <kuninori.morimoto.gx@renesas.com> wrote:
> > > > +               /* The Arm GIC-700AE - View 1 */
> > >
> > > s/700/720/
> >
> > Oops, thanks. Will fix
> >
> > > > +               gic: interrupt-controller@39000000 {
> > > > +                       compatible = "arm,gic-v3";
> > >
> > > The documentation states it is compliant with GICv4.1?
> >
> > I'm not familiar with GIC. And I think there is no v4 support on Linux yet ?
> > If my understanding was correct, GICv4 have GICv3 compatible.
> > We can use v3 driver so far, and can be replaced to v4 driver if it was
> > supported in Linux?
> 
> 'git grep -i "\<gic.*v4.1"' does show support.
> 
> Marc?

We don't need to differentiate the various GICv3.{0,1,2,3} and
GICv4.{0,1,2} in DT. GICv3 is enough, and everything is else can be
probed.

And yes, we support everything (but that's not relevant for DT).

> 
> > > > +                       #interrupt-cells = <3>;
> > > > +                       #address-cells = <0>;
> > > > +                       interrupt-controller;
> > > > +                       redistributor-stride = <0x0 0x40000>;

No. That's the architected value, and doesn't need to be described.
This property is solely designed to support broken HW, and I really
hope this is not the case here.

> > > > +                       #redistributor-regions = <32>;
> > > > +                       reg = <0 0x39000000 0 0x20000>, // GICD
> > >
> > > The base address is 0x38000000, according to the docs?
> >
> > It is indicated in very deep place in datasheet. I will indicate
> > detail in v2.
> >
> > > > +                             <0 0x397C0000 0 0x40000>, // GICR Core29
> > > > +                             <0 0x39800000 0 0x40000>, // GICR Core30
> > > > +                             <0 0x39840000 0 0x40000>; // GICR Core31

This really is silly. You have *one* RD region, not 32. This single
region covers all the RDs that your system has.

> > >
> > > No GICC, GICH, and GICV?
> >
> > will be added later ?
> 
> OK.

I seriously doubt you can have these regions, unless you have attached
a GIC700 to an ancient core such as A53. Here, you seem to have a
bunch of A720, which will *not* have the GICv2 compat regions.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Kuninori Morimoto]

Hi Geert

> > > > +                       reg = <0 0xc0700000 0 0x40>;
> > > > +                       interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
> > > > +                       clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
> > > > +                       clock-names = "fck", "brg_int", "scif_clk";
> > >
> > > "fck" on SCIF should be (derived from) SGASYNCD16 (66.666 MHz).
> > (snip)
> > > "fck" on HSCIF should be (derived from) SGASYNCD8 (133.33 MHz).
> >
> > In the early phase, there is no clock control support, so assume that
> > the clocks are enabled by default. Therefore, dummy clocks are used.
> > But indeed the naming seems strange. Will use just "dummy-clk".
> 
> I know.  But currently the clock rate for the dummy "fck" clocks does
> not match reality.  As the SCIF driver tries hard to find the best
> clock and divider for the requested transfer rate, it might pick "fck",
> breaking serial communication.
> So please add dummy clocks for SGASYNCD16 and SGASYNCD8, and use them as
> "fck" clocks for SCIF resp. HSCIF.

OK, will fix

> > > According to the DT bindings, "power-domains" and "resets" are missing.
> >
> > Unfortunately, can't use for now. It needs SCP support but is under
> > development. How should I do in this case ? Maybe use dummy device,
> > but can we use it ??
> 
> Just leave them out for now, but be prepared to receive complaints
> from the dtbs_check bots ;-)

OK, but I wonder does these really mandatory (= ) property ?
I'm asking because it works without these...

Thank you for your help !!

Best regards
---
Kuninori Morimoto

Re: [PATCH v2 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Geert Uytterhoeven]

Hi Morimoto-san,

On Tue, 16 Sept 2025 at 02:52, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> > > > > +                       reg = <0 0xc0700000 0 0x40>;
> > > > > +                       interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                       clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
> > > > > +                       clock-names = "fck", "brg_int", "scif_clk";

> > > > According to the DT bindings, "power-domains" and "resets" are missing.
> > >
> > > Unfortunately, can't use for now. It needs SCP support but is under
> > > development. How should I do in this case ? Maybe use dummy device,
> > > but can we use it ??
> >
> > Just leave them out for now, but be prepared to receive complaints
> > from the dtbs_check bots ;-)
>
> OK, but I wonder does these really mandatory (= ) property ?

DT describes hardware, and SCIF is part of the always-on Clock Domain.
I am not so sure about the module reset, but you made it required
in commit 6ac1d60473727931 ("dt-bindings: serial: sh-sci: Document
r8a78000 bindings")?

> I'm asking because it works without these...

Sure it works: SCIF is in the always-on power area, all clocks are
dummies (the real ones are enabled by the boot loader), and the Linux
driver doesn't use resets...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 3/4] arm64: dts: renesas: Add R8A78000 X5H DTs

[Kuninori Morimoto]

Hi Geert

> Sure it works: SCIF is in the always-on power area, all clocks are
> dummies (the real ones are enabled by the boot loader), and the Linux
> driver doesn't use resets...

SCIF DT is converted from txt to json by this commit

	384d00fae8e51f8ff812937b2e654ba3da858227
	("dt-bindings: serial: sh-sci: Convert to json-schema")

It seems original txt didn't indicate about "resets", but new json set it
as "required". I guess it is too much ?

Thank you for your help !!

Best regards
---
Kuninori Morimoto

[PATCH v2 4/4] arm64: renesas: Add R8A78000 Ironhide board code

[Kuninori Morimoto]

From: Hai Pham <hai.pham.ud@renesas.com>

Add the initial support for Renesas R8A7800 board code.

[Kuninori: tidyup for upstreaming]

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  2 +
 .../boot/dts/renesas/r8a78000-ironhide.dts    | 87 +++++++++++++++++++
 2 files changed, 89 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 6093d5f6e548..8b31cc70880d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -182,3 +182,5 @@ dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
 
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo
+
+dtb-$(CONFIG_ARCH_R8A78000) += r8a78000-ironhide.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
new file mode 100644
index 000000000000..de820a84172a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the Ironhide board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a78000.dtsi"
+
+/ {
+	model = "Renesas Ironhide board based on r8a78000";
+	compatible = "renesas,ironhide", "renesas,r8a78000";
+
+	aliases {
+		serial0 = &hscif0;
+	};
+
+	chosen {
+		bootargs = "maxcpus=1"; /* FIXME */
+		stdout-path = "serial0:1843200n8";
+	};
+
+	memory@60600000 {
+		device_type = "memory";
+		/* first 518MB is reserved for other purposes. */
+		reg = <0x0 0x60600000 0x0 0x5fa00000>;
+	};
+
+	memory@1080000000 {
+		device_type = "memory";
+		reg = <0x10 0x80000000 0x0 0x80000000>;
+	};
+
+	memory@1200000000 {
+		device_type = "memory";
+		reg = <0x12 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1400000000 {
+		device_type = "memory";
+		reg = <0x14 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1600000000 {
+		device_type = "memory";
+		reg = <0x16 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1800000000 {
+		device_type = "memory";
+		reg = <0x18 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1a00000000 {
+		device_type = "memory";
+		reg = <0x1a 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1c00000000 {
+		device_type = "memory";
+		reg = <0x1c 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1e00000000 {
+		device_type = "memory";
+		reg = <0x1e 0x00000000 0x1 0x00000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
+&hscif0 {
+	uart-has-rtscts;
+	/* Please use exclusively to the scif0 node */
+	status = "okay";
+};
+
+&scif_clk {
+	clock-frequency = <26000000>;
+};
-- 
2.43.0

Re: [PATCH v2 4/4] arm64: renesas: Add R8A78000 Ironhide board code

[Geert Uytterhoeven]

Hi Morimoto-san,

Thanks for your patch!

One-line summary should be e.g. "arm64: dts: renesas: r8a78000: Add
initial Ironhide support".

On Wed, 10 Sept 2025 at 04:02, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Hai Pham <hai.pham.ud@renesas.com>
>
> Add the initial support for Renesas R8A7800 board code.

board code?

>
> [Kuninori: tidyup for upstreaming]
>
> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
> Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
> Signed-off-by: Huy Bui <huy.bui.wm@renesas.com>
> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

> --- a/arch/arm64/boot/dts/renesas/Makefile
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -182,3 +182,5 @@ dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
>
>  dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
>  dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo
> +
> +dtb-$(CONFIG_ARCH_R8A78000) += r8a78000-ironhide.dtb

Please insert this after the last R8A77* line, and before the first
R9A* line.

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts

> +       chosen {
> +               bootargs = "maxcpus=1"; /* FIXME */

I'd rather drop all CPU nodes except for the first from r8a78000.dtsi.
They can be added later, when SMP works.

> +               stdout-path = "serial0:1843200n8";
> +       };
> +
> +       memory@60600000 {
> +               device_type = "memory";
> +               /* first 518MB is reserved for other purposes. */

MiB

(0x20600000 = ca. 543.2 MB ;-)

> +               reg = <0x0 0x60600000 0x0 0x5fa00000>;
> +       };

> +&extal_clk {
> +       clock-frequency = <16666666>;

Schematics says 16666600 Mhz (accuracy is only 50ppm anyway).

> +};

> +&hscif0 {
> +       uart-has-rtscts;
> +       /* Please use exclusively to the scif0 node */

Please drop this comment, as there is no scif0 node yet in this file.

> +       status = "okay";
> +};

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds