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From: Michael Opdenacker <michael.opdenacker@rootcommit.com>
To: Joshua Milas <josh.milas@gmail.com>
Cc: michael.opdenacker@rootcommit.com, tglx@kernel.org,
	robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	pjw@kernel.org, samuel.holland@sifive.com,
	unicorn_wang@outlook.com, inochiama@gmail.com,
	daniel.lezcano@linaro.org, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr,
	liujingqi@lanxincomputing.com, alexander.sverdlin@gmail.com,
	rabenda.cn@gmail.com, dlan@kernel.org, chao.wei@sophgo.com,
	anup@brainfault.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	sophgo@lists.linux.dev, hanguidong02@gmail.com
Subject: Re: [PATCH v4 0/5] Add initial Milk-V Duo S board support
Date: Thu,  2 Apr 2026 13:47:32 +0000 (UTC)	[thread overview]
Message-ID: <86b01b44-d030-4201-89da-0c8fc5282c92@rootcommit.com> (raw)
In-Reply-To: <ac5hFgLav_4oB2QA@sleek>

Hi Joshua

On 4/2/26 2:29 PM, Joshua Milas wrote:
> Hi Michael,
>
> Thanks for testing this. I am not seeing that issue on my arm64 or riscv side.
> I am able to add an IP and do anything I can think of on the arm64 side.
>
> [   96.618687] stmmaceth 4070000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
> [   96.633977] stmmaceth 4070000.ethernet eth0: PHY [mdio_mux-0.0:01] driver [Generic PHY] (irq=POLL)
> [   96.676436] dwmac1000: Master AXI performs any burst length
> [   96.702852] stmmaceth 4070000.ethernet eth0: No Safety Features support found
> [   96.748740] stmmaceth 4070000.ethernet eth0: IEEE 1588-2002 Timestamp supported
> [   96.772880] stmmaceth 4070000.ethernet eth0: configuring for phy/internal link mode
> [ 1359.377528] stmmaceth 4070000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off
>
> I can do the same on the riscv side but get a unhandled signal for TLS traffic
> which I believe is unrelated as it doesn't happen on adding an IP.
>
> I'll send over my configs to see if that helps.

I confirmed I managed to test the eth0 network interface on the riscv 
side using the configuration you shared. It would take me more time to 
test on arm64 :D|
You can send a update with your checkpatch fixes.

Tested-by: Michael Opdenacker <michael.opdenacker@rootcommit.com>

Thanks for everything!
Cheers
Michael.

-- 
Root Commit
Embedded Linux Training and Consulting
https://rootcommit.com


WARNING: multiple messages have this Message-ID (diff)
From: Michael Opdenacker <michael.opdenacker@rootcommit.com>
To: Joshua Milas <josh.milas@gmail.com>
Cc: michael.opdenacker@rootcommit.com, tglx@kernel.org,
	robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	pjw@kernel.org, samuel.holland@sifive.com,
	unicorn_wang@outlook.com, inochiama@gmail.com,
	daniel.lezcano@linaro.org, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr,
	liujingqi@lanxincomputing.com, alexander.sverdlin@gmail.com,
	rabenda.cn@gmail.com, dlan@kernel.org, chao.wei@sophgo.com,
	anup@brainfault.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	sophgo@lists.linux.dev, hanguidong02@gmail.com
Subject: Re: [PATCH v4 0/5] Add initial Milk-V Duo S board support
Date: Thu,  2 Apr 2026 13:47:32 +0000 (UTC)	[thread overview]
Message-ID: <86b01b44-d030-4201-89da-0c8fc5282c92@rootcommit.com> (raw)
In-Reply-To: <ac5hFgLav_4oB2QA@sleek>

Hi Joshua

On 4/2/26 2:29 PM, Joshua Milas wrote:
> Hi Michael,
>
> Thanks for testing this. I am not seeing that issue on my arm64 or riscv side.
> I am able to add an IP and do anything I can think of on the arm64 side.
>
> [   96.618687] stmmaceth 4070000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
> [   96.633977] stmmaceth 4070000.ethernet eth0: PHY [mdio_mux-0.0:01] driver [Generic PHY] (irq=POLL)
> [   96.676436] dwmac1000: Master AXI performs any burst length
> [   96.702852] stmmaceth 4070000.ethernet eth0: No Safety Features support found
> [   96.748740] stmmaceth 4070000.ethernet eth0: IEEE 1588-2002 Timestamp supported
> [   96.772880] stmmaceth 4070000.ethernet eth0: configuring for phy/internal link mode
> [ 1359.377528] stmmaceth 4070000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off
>
> I can do the same on the riscv side but get a unhandled signal for TLS traffic
> which I believe is unrelated as it doesn't happen on adding an IP.
>
> I'll send over my configs to see if that helps.

I confirmed I managed to test the eth0 network interface on the riscv 
side using the configuration you shared. It would take me more time to 
test on arm64 :D|
You can send a update with your checkpatch fixes.

Tested-by: Michael Opdenacker <michael.opdenacker@rootcommit.com>

Thanks for everything!
Cheers
Michael.

-- 
Root Commit
Embedded Linux Training and Consulting
https://rootcommit.com


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-04-02 13:47 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-28 17:34 [PATCH v4 0/5] Add initial Milk-V Duo S board support Joshua Milas
2026-03-28 17:34 ` Joshua Milas
2026-03-28 17:34 ` [PATCH v4 1/5] dt-bindings: soc: sophgo: add Milk-V Duo S board compatibles Joshua Milas
2026-03-28 17:34   ` Joshua Milas
2026-03-28 17:34 ` [PATCH v4 2/5] arm64: dts: sophgo: add initial Milk-V Duo S board support Joshua Milas
2026-03-28 17:34   ` Joshua Milas
2026-03-29 20:21   ` Michael Opdenacker
2026-03-29 20:21     ` Michael Opdenacker
2026-04-02 12:14     ` Joshua Milas
2026-04-02 12:14       ` Joshua Milas
2026-03-28 17:34 ` [PATCH v4 3/5] dt-bindings: soc: sophgo: add sg2000 plic and clint documentation Joshua Milas
2026-03-28 17:34   ` Joshua Milas
2026-03-28 17:34 ` [PATCH v4 4/5] riscv64: dts: sophgo: add SG2000 dtsi Joshua Milas
2026-03-28 17:34   ` Joshua Milas
2026-03-28 17:34 ` [PATCH v4 5/5] riscv64: dts: sophgo: add initial Milk-V Duo S board support Joshua Milas
2026-03-28 17:34   ` Joshua Milas
2026-03-29 21:14 ` [PATCH v4 0/5] Add " Michael Opdenacker
2026-03-29 21:14   ` Michael Opdenacker
2026-04-02 12:29   ` Joshua Milas
2026-04-02 12:29     ` Joshua Milas
2026-04-02 13:47     ` Michael Opdenacker [this message]
2026-04-02 13:47       ` Michael Opdenacker

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