Re: [PATCH v5 04/12] arm64: Add ARM64_HAS_LPA2 CPU capability

From: Marc Zyngier <maz@kernel.org>
To: Ryan Roberts <ryan.roberts@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Oliver Upton <oliver.upton@linux.dev>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	James Morse <james.morse@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev
Subject: Re: [PATCH v5 04/12] arm64: Add ARM64_HAS_LPA2 CPU capability
Date: Wed, 22 Nov 2023 15:14:52 +0000	[thread overview]
Message-ID: <86h6ldzuoj.wl-maz@kernel.org> (raw)
In-Reply-To: <20231116142931.1675485-5-ryan.roberts@arm.com>

On Thu, 16 Nov 2023 14:29:23 +0000,
Ryan Roberts <ryan.roberts@arm.com> wrote:
> 
> Expose FEAT_LPA2 as a capability so that we can take advantage of
> alternatives patching in the hypervisor.
> 
> Although FEAT_LPA2 presence is advertised separately for stage1 and
> stage2, the expectation is that in practice both stages will either
> support or not support it. Therefore, we combine both into a single
> capability, allowing us to simplify the implementation. KVM requires
> support in both stages in order to use LPA2 since the same library is
> used for hyp stage 1 and guest stage 2 pgtables.
> 
> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
> ---
>  arch/arm64/include/asm/cpufeature.h |  5 ++++
>  arch/arm64/kernel/cpufeature.c      | 39 +++++++++++++++++++++++++++++
>  arch/arm64/tools/cpucaps            |  1 +
>  3 files changed, 45 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> index f6d416fe49b0..acf109581ac0 100644
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -819,6 +819,11 @@ static inline bool system_supports_tlb_range(void)
>  	return alternative_has_cap_unlikely(ARM64_HAS_TLB_RANGE);
>  }
>  
> +static inline bool system_supports_lpa2(void)
> +{
> +	return cpus_have_final_cap(ARM64_HAS_LPA2);
> +}
> +
>  int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
>  bool try_emulate_mrs(struct pt_regs *regs, u32 isn);
>  
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 0e7d0c2bab36..38dfdaff8176 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1768,6 +1768,39 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
>  	return !meltdown_safe;
>  }
>  
> +#if defined(CONFIG_ARM64_4K_PAGES) || defined(CONFIG_ARM64_16K_PAGES)

nit: if you move patch #5 before this one, this can be gated by the
actual definition of ID_AA64MMFR0_EL1_TGRAN_{,2_}LPA2 instead of the
page size indirection. I personally would find it slightly more
readable.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.