* [PATCH 0/2] KVM: arm64: syreg cleanups/fixes
@ 2022-12-21 18:06 ` Mark Brown
0 siblings, 0 replies; 15+ messages in thread
From: Mark Brown @ 2022-12-21 18:06 UTC (permalink / raw)
To: Marc Zyngier, James Morse, Alexandru Elisei, Suzuki K Poulose,
Oliver Upton, Catalin Marinas, Will Deacon
Cc: kvmarm, Mark Brown, kvmarm, linux-arm-kernel, linux-kernel
While looking at the KVM ID register handling I realised that the
ARM64_FEATURE_MASK() macro which is extensively used there assumes that
all ID register fields are 4 bits wide which is sadly no longer true.
Fixing this just in the macro results in something that asked for
further cleanup so I went and did that. The end result is this series
which replaces code like:
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC);
val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1);
with:
val &= ~ID_AA64PFR0_EL1_GIC_MASK;
val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, GIC, 1);
which is if nothing else shorter with less boilerplate, and as a side
effect removes the assumption that all feature fields are 4 bits wide
that was what got me started.
At least one other assumption that fields are 4 bits wide exists in the
pKVM code in get_restricture_features_unsigned(). I have left this for
now since it is a much less mechanical change so probably belongs in a
separate series, I will work on that separately. The one register I am
aware of with fields that are impacted is ID_AA64SMFR0_EL1 so should
only become relevant in the event that we expose SME to pKVM guests.
There are some similar changes to use SYS_FIELD_ that could be done in
the GIC code but this is already far larger than would be expected for
the original fix and updating the GIC code will need the GIC registers
converting to generation which would really increase the size of the
series. The GIC also doesn't use ARM64_FEATURE_MASK() which was the
original issue. I will also send updates for the GIC separately.
Since this is highly likely to generate conflicts I'm posting during the
merge window to try to get a head start on review, I'll rebase against
-rc1 once that appears.
To: Marc Zyngier <maz@kernel.org>
To: James Morse <james.morse@arm.com>
To: Alexandru Elisei <alexandru.elisei@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Oliver Upton <oliver.upton@linux.dev>
To: Catalin Marinas <catalin.marinas@arm.com>
To: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.linux.dev
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Mark Brown (2):
KVM: arm64: Convert non-GIC code to SYS_FIELD_{GET,PREP}
KVM: arm64: Remove use of ARM64_FEATURE_MASK()
arch/arm64/include/asm/sysreg.h | 3 -
arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 120 ++++++++++++-------------
arch/arm64/kvm/hyp/nvhe/pkvm.c | 40 ++++-----
arch/arm64/kvm/hyp/nvhe/sys_regs.c | 26 +++---
arch/arm64/kvm/pmu-emul.c | 2 +-
arch/arm64/kvm/sys_regs.c | 66 +++++++-------
6 files changed, 128 insertions(+), 129 deletions(-)
---
base-commit: e45fb347b630ee76482fe938ba76cf8eab811290
change-id: 20221221-kvm-sysreg-cleanup-dd618baabebb
Best regards,
--
Mark Brown <broonie@kernel.org>
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 0/2] KVM: arm64: syreg cleanups/fixes @ 2022-12-21 18:06 ` Mark Brown 0 siblings, 0 replies; 15+ messages in thread From: Mark Brown @ 2022-12-21 18:06 UTC (permalink / raw) To: Marc Zyngier, James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon Cc: linux-arm-kernel, kvmarm, kvmarm, linux-kernel, Mark Brown While looking at the KVM ID register handling I realised that the ARM64_FEATURE_MASK() macro which is extensively used there assumes that all ID register fields are 4 bits wide which is sadly no longer true. Fixing this just in the macro results in something that asked for further cleanup so I went and did that. The end result is this series which replaces code like: val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1); with: val &= ~ID_AA64PFR0_EL1_GIC_MASK; val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, GIC, 1); which is if nothing else shorter with less boilerplate, and as a side effect removes the assumption that all feature fields are 4 bits wide that was what got me started. At least one other assumption that fields are 4 bits wide exists in the pKVM code in get_restricture_features_unsigned(). I have left this for now since it is a much less mechanical change so probably belongs in a separate series, I will work on that separately. The one register I am aware of with fields that are impacted is ID_AA64SMFR0_EL1 so should only become relevant in the event that we expose SME to pKVM guests. There are some similar changes to use SYS_FIELD_ that could be done in the GIC code but this is already far larger than would be expected for the original fix and updating the GIC code will need the GIC registers converting to generation which would really increase the size of the series. The GIC also doesn't use ARM64_FEATURE_MASK() which was the original issue. I will also send updates for the GIC separately. Since this is highly likely to generate conflicts I'm posting during the merge window to try to get a head start on review, I'll rebase against -rc1 once that appears. To: Marc Zyngier <maz@kernel.org> To: James Morse <james.morse@arm.com> To: Alexandru Elisei <alexandru.elisei@arm.com> To: Suzuki K Poulose <suzuki.poulose@arm.com> To: Oliver Upton <oliver.upton@linux.dev> To: Catalin Marinas <catalin.marinas@arm.com> To: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.linux.dev Cc: kvmarm@lists.cs.columbia.edu Cc: linux-kernel@vger.kernel.org Signed-off-by: Mark Brown <broonie@kernel.org> --- Mark Brown (2): KVM: arm64: Convert non-GIC code to SYS_FIELD_{GET,PREP} KVM: arm64: Remove use of ARM64_FEATURE_MASK() arch/arm64/include/asm/sysreg.h | 3 - arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 120 ++++++++++++------------- arch/arm64/kvm/hyp/nvhe/pkvm.c | 40 ++++----- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 26 +++--- arch/arm64/kvm/pmu-emul.c | 2 +- arch/arm64/kvm/sys_regs.c | 66 +++++++------- 6 files changed, 128 insertions(+), 129 deletions(-) --- base-commit: e45fb347b630ee76482fe938ba76cf8eab811290 change-id: 20221221-kvm-sysreg-cleanup-dd618baabebb Best regards, -- Mark Brown <broonie@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 0/2] KVM: arm64: syreg cleanups/fixes @ 2022-12-21 18:06 ` Mark Brown 0 siblings, 0 replies; 15+ messages in thread From: Mark Brown @ 2022-12-21 18:06 UTC (permalink / raw) To: Marc Zyngier, James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon Cc: linux-arm-kernel, kvmarm, kvmarm, linux-kernel, Mark Brown While looking at the KVM ID register handling I realised that the ARM64_FEATURE_MASK() macro which is extensively used there assumes that all ID register fields are 4 bits wide which is sadly no longer true. Fixing this just in the macro results in something that asked for further cleanup so I went and did that. The end result is this series which replaces code like: val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1); with: val &= ~ID_AA64PFR0_EL1_GIC_MASK; val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, GIC, 1); which is if nothing else shorter with less boilerplate, and as a side effect removes the assumption that all feature fields are 4 bits wide that was what got me started. At least one other assumption that fields are 4 bits wide exists in the pKVM code in get_restricture_features_unsigned(). I have left this for now since it is a much less mechanical change so probably belongs in a separate series, I will work on that separately. The one register I am aware of with fields that are impacted is ID_AA64SMFR0_EL1 so should only become relevant in the event that we expose SME to pKVM guests. There are some similar changes to use SYS_FIELD_ that could be done in the GIC code but this is already far larger than would be expected for the original fix and updating the GIC code will need the GIC registers converting to generation which would really increase the size of the series. The GIC also doesn't use ARM64_FEATURE_MASK() which was the original issue. I will also send updates for the GIC separately. Since this is highly likely to generate conflicts I'm posting during the merge window to try to get a head start on review, I'll rebase against -rc1 once that appears. To: Marc Zyngier <maz@kernel.org> To: James Morse <james.morse@arm.com> To: Alexandru Elisei <alexandru.elisei@arm.com> To: Suzuki K Poulose <suzuki.poulose@arm.com> To: Oliver Upton <oliver.upton@linux.dev> To: Catalin Marinas <catalin.marinas@arm.com> To: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.linux.dev Cc: kvmarm@lists.cs.columbia.edu Cc: linux-kernel@vger.kernel.org Signed-off-by: Mark Brown <broonie@kernel.org> --- Mark Brown (2): KVM: arm64: Convert non-GIC code to SYS_FIELD_{GET,PREP} KVM: arm64: Remove use of ARM64_FEATURE_MASK() arch/arm64/include/asm/sysreg.h | 3 - arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 120 ++++++++++++------------- arch/arm64/kvm/hyp/nvhe/pkvm.c | 40 ++++----- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 26 +++--- arch/arm64/kvm/pmu-emul.c | 2 +- arch/arm64/kvm/sys_regs.c | 66 +++++++------- 6 files changed, 128 insertions(+), 129 deletions(-) --- base-commit: e45fb347b630ee76482fe938ba76cf8eab811290 change-id: 20221221-kvm-sysreg-cleanup-dd618baabebb Best regards, -- Mark Brown <broonie@kernel.org> ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/2] KVM: arm64: Convert non-GIC code to SYS_FIELD_{GET,PREP} @ 2022-12-21 18:06 ` Mark Brown 0 siblings, 0 replies; 15+ messages in thread From: Mark Brown @ 2022-12-21 18:06 UTC (permalink / raw) To: Marc Zyngier, James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon Cc: kvmarm, Mark Brown, kvmarm, linux-arm-kernel, linux-kernel A while ago we introduced helpers which build on the generated defines for the system registers which use token pasting to let us do FIELD_PREP() and FIELD_GET() in a shorter and hopefully easier to read format, including one specifically for enumerations. Update the bulk of the KVM code to use these where the registers have already been converted, the remaining uses are in the GIC code and will need conversions of the GIC registers. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> --- arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 14 ++++----- arch/arm64/kvm/hyp/nvhe/pkvm.c | 40 +++++++++++++------------- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 12 ++++---- arch/arm64/kvm/pmu-emul.c | 2 +- arch/arm64/kvm/sys_regs.c | 22 +++++++------- 5 files changed, 46 insertions(+), 44 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index 07edfc7524c9..f42cd1bdb45b 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -49,11 +49,11 @@ * Supported by KVM */ #define PVM_ID_AA64PFR0_RESTRICT_UNSIGNED (\ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL2), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL3), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), ID_AA64PFR0_EL1_RAS_IMP) \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL0, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL1, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL2, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL3, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, RAS, IMP) \ ) /* @@ -86,8 +86,8 @@ * - 16-bit ASID */ #define PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED (\ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \ + SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, PARANGE, 40) | \ + SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, ASIDBITS, 16) \ ) /* diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index a06ece14a6d8..eec461e2c5d5 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -29,35 +29,35 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu) u64 cptr_set = 0; /* Protected KVM does not support AArch32 guests. */ - BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), - PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); - BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), - PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); + BUILD_BUG_ON(SYS_FIELD_GET(ID_AA64PFR0_EL1, EL0, + PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); + BUILD_BUG_ON(SYS_FIELD_GET(ID_AA64PFR0_EL1, EL1, + PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); /* * Linux guests assume support for floating-point and Advanced SIMD. Do * not change the trapping behavior for these from the KVM default. */ - BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP), - PVM_ID_AA64PFR0_ALLOW)); - BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD), - PVM_ID_AA64PFR0_ALLOW)); + BUILD_BUG_ON(!SYS_FIELD_GET(ID_AA64PFR0_EL1, FP, + PVM_ID_AA64PFR0_ALLOW)); + BUILD_BUG_ON(!SYS_FIELD_GET(ID_AA64PFR0_EL1, AdvSIMD, + PVM_ID_AA64PFR0_ALLOW)); /* Trap RAS unless all current versions are supported */ - if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), feature_ids) < + if (SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, feature_ids) < ID_AA64PFR0_EL1_RAS_V1P1) { hcr_set |= HCR_TERR | HCR_TEA; hcr_clear |= HCR_FIEN; } /* Trap AMU */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU), feature_ids)) { + if (!SYS_FIELD_GET(ID_AA64PFR0_EL1, AMU, feature_ids)) { hcr_clear |= HCR_AMVOFFEN; cptr_set |= CPTR_EL2_TAM; } /* Trap SVE */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64PFR0_EL1, SVE, feature_ids)) cptr_set |= CPTR_EL2_TZ; vcpu->arch.hcr_el2 |= hcr_set; @@ -75,7 +75,7 @@ static void pvm_init_traps_aa64pfr1(struct kvm_vcpu *vcpu) u64 hcr_clear = 0; /* Memory Tagging: Trap and Treat as Untagged if not supported. */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE), feature_ids)) { + if (SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE, feature_ids)) { hcr_set |= HCR_TID5; hcr_clear |= HCR_DCT | HCR_ATA; } @@ -95,32 +95,32 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu) u64 cptr_set = 0; /* Trap/constrain PMU */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), feature_ids)) { + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, feature_ids)) { mdcr_set |= MDCR_EL2_TPM | MDCR_EL2_TPMCR; mdcr_clear |= MDCR_EL2_HPME | MDCR_EL2_MTPME | MDCR_EL2_HPMN_MASK; } /* Trap Debug */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, feature_ids)) mdcr_set |= MDCR_EL2_TDRA | MDCR_EL2_TDA | MDCR_EL2_TDE; /* Trap OS Double Lock */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DoubleLock), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, feature_ids)) mdcr_set |= MDCR_EL2_TDOSA; /* Trap SPE */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer), feature_ids)) { + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, PMSVer, feature_ids)) { mdcr_set |= MDCR_EL2_TPMS; mdcr_clear |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT; } /* Trap Trace Filter */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceFilt), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, TraceFilt, feature_ids)) mdcr_set |= MDCR_EL2_TTRF; /* Trap Trace */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceVer), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, TraceVer, feature_ids)) cptr_set |= CPTR_EL2_TTA; vcpu->arch.mdcr_el2 |= mdcr_set; @@ -137,7 +137,7 @@ static void pvm_init_traps_aa64mmfr0(struct kvm_vcpu *vcpu) u64 mdcr_set = 0; /* Trap Debug Communications Channel registers */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_FGT), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64MMFR0_EL1, FGT, feature_ids)) mdcr_set |= MDCR_EL2_TDCC; vcpu->arch.mdcr_el2 |= mdcr_set; @@ -152,7 +152,7 @@ static void pvm_init_traps_aa64mmfr1(struct kvm_vcpu *vcpu) u64 hcr_set = 0; /* Trap LOR */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_LO), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64MMFR1_EL1, LO, feature_ids)) hcr_set |= HCR_TLOR; vcpu->arch.hcr_el2 |= hcr_set; diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 0f9ac25afdf4..1e656d928819 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -92,10 +92,10 @@ static u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu) PVM_ID_AA64PFR0_RESTRICT_UNSIGNED); /* Spectre and Meltdown mitigation in KVM */ - set_mask |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), - (u64)kvm->arch.pfr0_csv2); - set_mask |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), - (u64)kvm->arch.pfr0_csv3); + set_mask |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV2, + (u64)kvm->arch.pfr0_csv2); + set_mask |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV3, + (u64)kvm->arch.pfr0_csv3); return (id_aa64pfr0_el1_sys_val & allow_mask) | set_mask; } @@ -281,8 +281,8 @@ static bool pvm_access_id_aarch32(struct kvm_vcpu *vcpu, * No support for AArch32 guests, therefore, pKVM has no sanitized copy * of AArch32 feature id registers. */ - BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), - PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) > ID_AA64PFR0_EL1_ELx_64BIT_ONLY); + BUILD_BUG_ON(SYS_FIELD_GET(ID_AA64PFR0_EL1, EL1, + PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) > ID_AA64PFR0_EL1_ELx_64BIT_ONLY); return pvm_access_raz_wi(vcpu, p, r); } diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 24908400e190..ba2be9af0206 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -1058,5 +1058,5 @@ u8 kvm_arm_pmu_get_pmuver_limit(void) tmp = cpuid_feature_cap_perfmon_field(tmp, ID_AA64DFR0_EL1_PMUVer_SHIFT, ID_AA64DFR0_EL1_PMUVer_V3P5); - return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), tmp); + return SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, tmp); } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d5ee52d6bf73..f97695bb8f64 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1111,12 +1111,14 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE); val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); + val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV2, + (u64)vcpu->kvm->arch.pfr0_csv2); val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); + val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV3, + (u64)vcpu->kvm->arch.pfr0_csv3); if (kvm_vgic_global_state.type == VGIC_V3) { val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1); + val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, GIC, 1); } break; case SYS_ID_AA64PFR1_EL1: @@ -1142,18 +1144,18 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6); + val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, DebugVer, 6); /* Set PMUver to the required version */ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), - vcpu_pmuver(vcpu)); + val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, + vcpu_pmuver(vcpu)); /* Hide SPE from guests */ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); break; case SYS_ID_DFR0_EL1: val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), - pmuver_to_perfmon(vcpu_pmuver(vcpu))); + val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, + pmuver_to_perfmon(vcpu_pmuver(vcpu))); break; } @@ -1268,7 +1270,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, * allow an IMPDEF PMU though, only if no PMU is supported * (KVM backward compatibility handling). */ - pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val); + pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver)) return -EINVAL; @@ -1307,7 +1309,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, * AArch64 side (as everything is emulated with that), and * that this is a PMUv3. */ - perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val); + perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) || (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)) return -EINVAL; -- 2.30.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/2] KVM: arm64: Convert non-GIC code to SYS_FIELD_{GET,PREP} @ 2022-12-21 18:06 ` Mark Brown 0 siblings, 0 replies; 15+ messages in thread From: Mark Brown @ 2022-12-21 18:06 UTC (permalink / raw) To: Marc Zyngier, James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon Cc: linux-arm-kernel, kvmarm, kvmarm, linux-kernel, Mark Brown A while ago we introduced helpers which build on the generated defines for the system registers which use token pasting to let us do FIELD_PREP() and FIELD_GET() in a shorter and hopefully easier to read format, including one specifically for enumerations. Update the bulk of the KVM code to use these where the registers have already been converted, the remaining uses are in the GIC code and will need conversions of the GIC registers. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> --- arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 14 ++++----- arch/arm64/kvm/hyp/nvhe/pkvm.c | 40 +++++++++++++------------- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 12 ++++---- arch/arm64/kvm/pmu-emul.c | 2 +- arch/arm64/kvm/sys_regs.c | 22 +++++++------- 5 files changed, 46 insertions(+), 44 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index 07edfc7524c9..f42cd1bdb45b 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -49,11 +49,11 @@ * Supported by KVM */ #define PVM_ID_AA64PFR0_RESTRICT_UNSIGNED (\ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL2), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL3), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), ID_AA64PFR0_EL1_RAS_IMP) \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL0, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL1, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL2, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL3, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, RAS, IMP) \ ) /* @@ -86,8 +86,8 @@ * - 16-bit ASID */ #define PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED (\ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \ + SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, PARANGE, 40) | \ + SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, ASIDBITS, 16) \ ) /* diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index a06ece14a6d8..eec461e2c5d5 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -29,35 +29,35 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu) u64 cptr_set = 0; /* Protected KVM does not support AArch32 guests. */ - BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), - PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); - BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), - PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); + BUILD_BUG_ON(SYS_FIELD_GET(ID_AA64PFR0_EL1, EL0, + PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); + BUILD_BUG_ON(SYS_FIELD_GET(ID_AA64PFR0_EL1, EL1, + PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); /* * Linux guests assume support for floating-point and Advanced SIMD. Do * not change the trapping behavior for these from the KVM default. */ - BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP), - PVM_ID_AA64PFR0_ALLOW)); - BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD), - PVM_ID_AA64PFR0_ALLOW)); + BUILD_BUG_ON(!SYS_FIELD_GET(ID_AA64PFR0_EL1, FP, + PVM_ID_AA64PFR0_ALLOW)); + BUILD_BUG_ON(!SYS_FIELD_GET(ID_AA64PFR0_EL1, AdvSIMD, + PVM_ID_AA64PFR0_ALLOW)); /* Trap RAS unless all current versions are supported */ - if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), feature_ids) < + if (SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, feature_ids) < ID_AA64PFR0_EL1_RAS_V1P1) { hcr_set |= HCR_TERR | HCR_TEA; hcr_clear |= HCR_FIEN; } /* Trap AMU */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU), feature_ids)) { + if (!SYS_FIELD_GET(ID_AA64PFR0_EL1, AMU, feature_ids)) { hcr_clear |= HCR_AMVOFFEN; cptr_set |= CPTR_EL2_TAM; } /* Trap SVE */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64PFR0_EL1, SVE, feature_ids)) cptr_set |= CPTR_EL2_TZ; vcpu->arch.hcr_el2 |= hcr_set; @@ -75,7 +75,7 @@ static void pvm_init_traps_aa64pfr1(struct kvm_vcpu *vcpu) u64 hcr_clear = 0; /* Memory Tagging: Trap and Treat as Untagged if not supported. */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE), feature_ids)) { + if (SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE, feature_ids)) { hcr_set |= HCR_TID5; hcr_clear |= HCR_DCT | HCR_ATA; } @@ -95,32 +95,32 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu) u64 cptr_set = 0; /* Trap/constrain PMU */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), feature_ids)) { + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, feature_ids)) { mdcr_set |= MDCR_EL2_TPM | MDCR_EL2_TPMCR; mdcr_clear |= MDCR_EL2_HPME | MDCR_EL2_MTPME | MDCR_EL2_HPMN_MASK; } /* Trap Debug */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, feature_ids)) mdcr_set |= MDCR_EL2_TDRA | MDCR_EL2_TDA | MDCR_EL2_TDE; /* Trap OS Double Lock */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DoubleLock), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, feature_ids)) mdcr_set |= MDCR_EL2_TDOSA; /* Trap SPE */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer), feature_ids)) { + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, PMSVer, feature_ids)) { mdcr_set |= MDCR_EL2_TPMS; mdcr_clear |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT; } /* Trap Trace Filter */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceFilt), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, TraceFilt, feature_ids)) mdcr_set |= MDCR_EL2_TTRF; /* Trap Trace */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceVer), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, TraceVer, feature_ids)) cptr_set |= CPTR_EL2_TTA; vcpu->arch.mdcr_el2 |= mdcr_set; @@ -137,7 +137,7 @@ static void pvm_init_traps_aa64mmfr0(struct kvm_vcpu *vcpu) u64 mdcr_set = 0; /* Trap Debug Communications Channel registers */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_FGT), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64MMFR0_EL1, FGT, feature_ids)) mdcr_set |= MDCR_EL2_TDCC; vcpu->arch.mdcr_el2 |= mdcr_set; @@ -152,7 +152,7 @@ static void pvm_init_traps_aa64mmfr1(struct kvm_vcpu *vcpu) u64 hcr_set = 0; /* Trap LOR */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_LO), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64MMFR1_EL1, LO, feature_ids)) hcr_set |= HCR_TLOR; vcpu->arch.hcr_el2 |= hcr_set; diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 0f9ac25afdf4..1e656d928819 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -92,10 +92,10 @@ static u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu) PVM_ID_AA64PFR0_RESTRICT_UNSIGNED); /* Spectre and Meltdown mitigation in KVM */ - set_mask |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), - (u64)kvm->arch.pfr0_csv2); - set_mask |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), - (u64)kvm->arch.pfr0_csv3); + set_mask |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV2, + (u64)kvm->arch.pfr0_csv2); + set_mask |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV3, + (u64)kvm->arch.pfr0_csv3); return (id_aa64pfr0_el1_sys_val & allow_mask) | set_mask; } @@ -281,8 +281,8 @@ static bool pvm_access_id_aarch32(struct kvm_vcpu *vcpu, * No support for AArch32 guests, therefore, pKVM has no sanitized copy * of AArch32 feature id registers. */ - BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), - PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) > ID_AA64PFR0_EL1_ELx_64BIT_ONLY); + BUILD_BUG_ON(SYS_FIELD_GET(ID_AA64PFR0_EL1, EL1, + PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) > ID_AA64PFR0_EL1_ELx_64BIT_ONLY); return pvm_access_raz_wi(vcpu, p, r); } diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 24908400e190..ba2be9af0206 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -1058,5 +1058,5 @@ u8 kvm_arm_pmu_get_pmuver_limit(void) tmp = cpuid_feature_cap_perfmon_field(tmp, ID_AA64DFR0_EL1_PMUVer_SHIFT, ID_AA64DFR0_EL1_PMUVer_V3P5); - return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), tmp); + return SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, tmp); } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d5ee52d6bf73..f97695bb8f64 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1111,12 +1111,14 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE); val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); + val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV2, + (u64)vcpu->kvm->arch.pfr0_csv2); val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); + val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV3, + (u64)vcpu->kvm->arch.pfr0_csv3); if (kvm_vgic_global_state.type == VGIC_V3) { val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1); + val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, GIC, 1); } break; case SYS_ID_AA64PFR1_EL1: @@ -1142,18 +1144,18 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6); + val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, DebugVer, 6); /* Set PMUver to the required version */ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), - vcpu_pmuver(vcpu)); + val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, + vcpu_pmuver(vcpu)); /* Hide SPE from guests */ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); break; case SYS_ID_DFR0_EL1: val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), - pmuver_to_perfmon(vcpu_pmuver(vcpu))); + val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, + pmuver_to_perfmon(vcpu_pmuver(vcpu))); break; } @@ -1268,7 +1270,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, * allow an IMPDEF PMU though, only if no PMU is supported * (KVM backward compatibility handling). */ - pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val); + pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver)) return -EINVAL; @@ -1307,7 +1309,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, * AArch64 side (as everything is emulated with that), and * that this is a PMUv3. */ - perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val); + perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) || (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)) return -EINVAL; -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/2] KVM: arm64: Convert non-GIC code to SYS_FIELD_{GET,PREP} @ 2022-12-21 18:06 ` Mark Brown 0 siblings, 0 replies; 15+ messages in thread From: Mark Brown @ 2022-12-21 18:06 UTC (permalink / raw) To: Marc Zyngier, James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon Cc: linux-arm-kernel, kvmarm, kvmarm, linux-kernel, Mark Brown A while ago we introduced helpers which build on the generated defines for the system registers which use token pasting to let us do FIELD_PREP() and FIELD_GET() in a shorter and hopefully easier to read format, including one specifically for enumerations. Update the bulk of the KVM code to use these where the registers have already been converted, the remaining uses are in the GIC code and will need conversions of the GIC registers. No functional changes. Signed-off-by: Mark Brown <broonie@kernel.org> --- arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 14 ++++----- arch/arm64/kvm/hyp/nvhe/pkvm.c | 40 +++++++++++++------------- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 12 ++++---- arch/arm64/kvm/pmu-emul.c | 2 +- arch/arm64/kvm/sys_regs.c | 22 +++++++------- 5 files changed, 46 insertions(+), 44 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index 07edfc7524c9..f42cd1bdb45b 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -49,11 +49,11 @@ * Supported by KVM */ #define PVM_ID_AA64PFR0_RESTRICT_UNSIGNED (\ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL2), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL3), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), ID_AA64PFR0_EL1_RAS_IMP) \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL0, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL1, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL2, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL3, IMP) | \ + SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, RAS, IMP) \ ) /* @@ -86,8 +86,8 @@ * - 16-bit ASID */ #define PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED (\ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \ - FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \ + SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, PARANGE, 40) | \ + SYS_FIELD_PREP_ENUM(ID_AA64MMFR0_EL1, ASIDBITS, 16) \ ) /* diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index a06ece14a6d8..eec461e2c5d5 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -29,35 +29,35 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu) u64 cptr_set = 0; /* Protected KVM does not support AArch32 guests. */ - BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), - PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); - BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), - PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); + BUILD_BUG_ON(SYS_FIELD_GET(ID_AA64PFR0_EL1, EL0, + PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); + BUILD_BUG_ON(SYS_FIELD_GET(ID_AA64PFR0_EL1, EL1, + PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY); /* * Linux guests assume support for floating-point and Advanced SIMD. Do * not change the trapping behavior for these from the KVM default. */ - BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP), - PVM_ID_AA64PFR0_ALLOW)); - BUILD_BUG_ON(!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD), - PVM_ID_AA64PFR0_ALLOW)); + BUILD_BUG_ON(!SYS_FIELD_GET(ID_AA64PFR0_EL1, FP, + PVM_ID_AA64PFR0_ALLOW)); + BUILD_BUG_ON(!SYS_FIELD_GET(ID_AA64PFR0_EL1, AdvSIMD, + PVM_ID_AA64PFR0_ALLOW)); /* Trap RAS unless all current versions are supported */ - if (FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), feature_ids) < + if (SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, feature_ids) < ID_AA64PFR0_EL1_RAS_V1P1) { hcr_set |= HCR_TERR | HCR_TEA; hcr_clear |= HCR_FIEN; } /* Trap AMU */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU), feature_ids)) { + if (!SYS_FIELD_GET(ID_AA64PFR0_EL1, AMU, feature_ids)) { hcr_clear |= HCR_AMVOFFEN; cptr_set |= CPTR_EL2_TAM; } /* Trap SVE */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64PFR0_EL1, SVE, feature_ids)) cptr_set |= CPTR_EL2_TZ; vcpu->arch.hcr_el2 |= hcr_set; @@ -75,7 +75,7 @@ static void pvm_init_traps_aa64pfr1(struct kvm_vcpu *vcpu) u64 hcr_clear = 0; /* Memory Tagging: Trap and Treat as Untagged if not supported. */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE), feature_ids)) { + if (SYS_FIELD_GET(ID_AA64PFR1_EL1, MTE, feature_ids)) { hcr_set |= HCR_TID5; hcr_clear |= HCR_DCT | HCR_ATA; } @@ -95,32 +95,32 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu) u64 cptr_set = 0; /* Trap/constrain PMU */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), feature_ids)) { + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, feature_ids)) { mdcr_set |= MDCR_EL2_TPM | MDCR_EL2_TPMCR; mdcr_clear |= MDCR_EL2_HPME | MDCR_EL2_MTPME | MDCR_EL2_HPMN_MASK; } /* Trap Debug */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, feature_ids)) mdcr_set |= MDCR_EL2_TDRA | MDCR_EL2_TDA | MDCR_EL2_TDE; /* Trap OS Double Lock */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DoubleLock), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, DoubleLock, feature_ids)) mdcr_set |= MDCR_EL2_TDOSA; /* Trap SPE */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer), feature_ids)) { + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, PMSVer, feature_ids)) { mdcr_set |= MDCR_EL2_TPMS; mdcr_clear |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT; } /* Trap Trace Filter */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceFilt), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, TraceFilt, feature_ids)) mdcr_set |= MDCR_EL2_TTRF; /* Trap Trace */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceVer), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64DFR0_EL1, TraceVer, feature_ids)) cptr_set |= CPTR_EL2_TTA; vcpu->arch.mdcr_el2 |= mdcr_set; @@ -137,7 +137,7 @@ static void pvm_init_traps_aa64mmfr0(struct kvm_vcpu *vcpu) u64 mdcr_set = 0; /* Trap Debug Communications Channel registers */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_FGT), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64MMFR0_EL1, FGT, feature_ids)) mdcr_set |= MDCR_EL2_TDCC; vcpu->arch.mdcr_el2 |= mdcr_set; @@ -152,7 +152,7 @@ static void pvm_init_traps_aa64mmfr1(struct kvm_vcpu *vcpu) u64 hcr_set = 0; /* Trap LOR */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_LO), feature_ids)) + if (!SYS_FIELD_GET(ID_AA64MMFR1_EL1, LO, feature_ids)) hcr_set |= HCR_TLOR; vcpu->arch.hcr_el2 |= hcr_set; diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 0f9ac25afdf4..1e656d928819 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -92,10 +92,10 @@ static u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu) PVM_ID_AA64PFR0_RESTRICT_UNSIGNED); /* Spectre and Meltdown mitigation in KVM */ - set_mask |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), - (u64)kvm->arch.pfr0_csv2); - set_mask |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), - (u64)kvm->arch.pfr0_csv3); + set_mask |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV2, + (u64)kvm->arch.pfr0_csv2); + set_mask |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV3, + (u64)kvm->arch.pfr0_csv3); return (id_aa64pfr0_el1_sys_val & allow_mask) | set_mask; } @@ -281,8 +281,8 @@ static bool pvm_access_id_aarch32(struct kvm_vcpu *vcpu, * No support for AArch32 guests, therefore, pKVM has no sanitized copy * of AArch32 feature id registers. */ - BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), - PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) > ID_AA64PFR0_EL1_ELx_64BIT_ONLY); + BUILD_BUG_ON(SYS_FIELD_GET(ID_AA64PFR0_EL1, EL1, + PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) > ID_AA64PFR0_EL1_ELx_64BIT_ONLY); return pvm_access_raz_wi(vcpu, p, r); } diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 24908400e190..ba2be9af0206 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -1058,5 +1058,5 @@ u8 kvm_arm_pmu_get_pmuver_limit(void) tmp = cpuid_feature_cap_perfmon_field(tmp, ID_AA64DFR0_EL1_PMUVer_SHIFT, ID_AA64DFR0_EL1_PMUVer_V3P5); - return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), tmp); + return SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, tmp); } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d5ee52d6bf73..f97695bb8f64 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1111,12 +1111,14 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE); val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); + val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV2, + (u64)vcpu->kvm->arch.pfr0_csv2); val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); + val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV3, + (u64)vcpu->kvm->arch.pfr0_csv3); if (kvm_vgic_global_state.type == VGIC_V3) { val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), 1); + val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, GIC, 1); } break; case SYS_ID_AA64PFR1_EL1: @@ -1142,18 +1144,18 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), 6); + val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, DebugVer, 6); /* Set PMUver to the required version */ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), - vcpu_pmuver(vcpu)); + val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, + vcpu_pmuver(vcpu)); /* Hide SPE from guests */ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); break; case SYS_ID_DFR0_EL1: val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), - pmuver_to_perfmon(vcpu_pmuver(vcpu))); + val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, + pmuver_to_perfmon(vcpu_pmuver(vcpu))); break; } @@ -1268,7 +1270,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, * allow an IMPDEF PMU though, only if no PMU is supported * (KVM backward compatibility handling). */ - pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val); + pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver)) return -EINVAL; @@ -1307,7 +1309,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, * AArch64 side (as everything is emulated with that), and * that this is a PMUv3. */ - perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon), val); + perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); if ((perfmon != ID_DFR0_EL1_PerfMon_IMPDEF && perfmon > host_perfmon) || (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)) return -EINVAL; -- 2.30.2 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/2] KVM: arm64: Remove use of ARM64_FEATURE_MASK() @ 2022-12-21 18:06 ` Mark Brown 0 siblings, 0 replies; 15+ messages in thread From: Mark Brown @ 2022-12-21 18:06 UTC (permalink / raw) To: Marc Zyngier, James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon Cc: kvmarm, Mark Brown, kvmarm, linux-arm-kernel, linux-kernel The KVM code makes extensive use of ARM64_FEATURE_MASK() to generate a mask for fields in the ID registers. This macro has the assumption that all feature fields are 4 bits wide but the architecture has evolved to add fields with other widths, such as the 1 bit fields in ID_AA64SMFR0_EL1, so we need to adjust the We could fix this by making ARM64_FEATURE_MASK() use the generated macros that we have now but since one of these is a direct _MASK constant the result is something that's more verbose and less direct than just updating the users to directly use the generated mask macros, writing #define ARM64_FEATURE_MASK(x) (x##_MASK) obviously looks redundant and if we look at the users updating them turns val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); into the more direct val &= ~ID_AA64PFR0_EL1_CSV3_MASK; rather than updating the macro just remove the users. This is a relatively large code change but very mechanical. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> --- arch/arm64/include/asm/sysreg.h | 3 - arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 106 ++++++++++++------------- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 14 ++-- arch/arm64/kvm/sys_regs.c | 44 +++++----- 4 files changed, 82 insertions(+), 85 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 1312fb48f18b..3ac6ed1921c7 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -809,9 +809,6 @@ #define ARM64_FEATURE_FIELD_BITS 4 -/* Create a mask for the feature bits of the specified feature. */ -#define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT)) - #ifdef __ASSEMBLY__ .macro mrs_s, rt, sreg diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index f42cd1bdb45b..a8aa9efe6581 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -35,9 +35,9 @@ * - Data Independent Timing */ #define PVM_ID_AA64PFR0_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP) | \ - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD) | \ - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_DIT) \ + ID_AA64PFR0_EL1_FP_MASK | \ + ID_AA64PFR0_EL1_AdvSIMD_MASK | \ + ID_AA64PFR0_EL1_DIT_MASK \ ) /* @@ -62,8 +62,8 @@ * - Speculative Store Bypassing */ #define PVM_ID_AA64PFR1_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_BT) | \ - ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SSBS) \ + ID_AA64PFR1_EL1_BT_MASK | \ + ID_AA64PFR1_EL1_SSBS_MASK \ ) /* @@ -74,10 +74,10 @@ * - Non-context synchronizing exception entry and exit */ #define PVM_ID_AA64MMFR0_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGEND) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_SNSMEM) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGENDEL0) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_EXS) \ + ID_AA64MMFR0_EL1_BIGEND_MASK | \ + ID_AA64MMFR0_EL1_SNSMEM_MASK | \ + ID_AA64MMFR0_EL1_BIGENDEL0_MASK | \ + ID_AA64MMFR0_EL1_EXS_MASK \ ) /* @@ -100,12 +100,12 @@ * - Enhanced Translation Synchronization */ #define PVM_ID_AA64MMFR1_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_VMIDBits) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HPDS) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_PAN) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_SpecSEI) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_ETS) \ + ID_AA64MMFR1_EL1_HAFDBS_MASK | \ + ID_AA64MMFR1_EL1_VMIDBits_MASK | \ + ID_AA64MMFR1_EL1_HPDS_MASK | \ + ID_AA64MMFR1_EL1_PAN_MASK | \ + ID_AA64MMFR1_EL1_SpecSEI_MASK | \ + ID_AA64MMFR1_EL1_ETS_MASK \ ) /* @@ -120,14 +120,14 @@ * - E0PDx mechanism */ #define PVM_ID_AA64MMFR2_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_CnP) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_UAO) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IESB) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_AT) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IDS) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_TTL) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_BBM) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_E0PD) \ + ID_AA64MMFR2_EL1_CnP_MASK | \ + ID_AA64MMFR2_EL1_UAO_MASK | \ + ID_AA64MMFR2_EL1_IESB_MASK | \ + ID_AA64MMFR2_EL1_AT_MASK | \ + ID_AA64MMFR2_EL1_IDS_MASK | \ + ID_AA64MMFR2_EL1_TTL_MASK | \ + ID_AA64MMFR2_EL1_BBM_MASK | \ + ID_AA64MMFR2_EL1_E0PD_MASK \ ) /* @@ -159,42 +159,42 @@ * No restrictions on instructions implemented in AArch64. */ #define PVM_ID_AA64ISAR0_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_AES) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA1) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA2) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_CRC32) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMIC) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RDM) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM4) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_DP) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_FHM) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TS) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TLB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RNDR) \ + ID_AA64ISAR0_EL1_AES_MASK | \ + ID_AA64ISAR0_EL1_SHA1_MASK | \ + ID_AA64ISAR0_EL1_SHA2_MASK | \ + ID_AA64ISAR0_EL1_CRC32_MASK | \ + ID_AA64ISAR0_EL1_ATOMIC_MASK | \ + ID_AA64ISAR0_EL1_RDM_MASK | \ + ID_AA64ISAR0_EL1_SHA3_MASK | \ + ID_AA64ISAR0_EL1_SM3_MASK | \ + ID_AA64ISAR0_EL1_SM4_MASK | \ + ID_AA64ISAR0_EL1_DP_MASK | \ + ID_AA64ISAR0_EL1_FHM_MASK | \ + ID_AA64ISAR0_EL1_TS_MASK | \ + ID_AA64ISAR0_EL1_TLB_MASK | \ + ID_AA64ISAR0_EL1_RNDR_MASK \ ) #define PVM_ID_AA64ISAR1_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FCMA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_LRCPC) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FRINTTS) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SPECRES) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_BF16) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DGH) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) \ + ID_AA64ISAR1_EL1_DPB_MASK | \ + ID_AA64ISAR1_EL1_APA_MASK | \ + ID_AA64ISAR1_EL1_API_MASK | \ + ID_AA64ISAR1_EL1_JSCVT_MASK | \ + ID_AA64ISAR1_EL1_FCMA_MASK | \ + ID_AA64ISAR1_EL1_LRCPC_MASK | \ + ID_AA64ISAR1_EL1_GPA_MASK | \ + ID_AA64ISAR1_EL1_GPI_MASK | \ + ID_AA64ISAR1_EL1_FRINTTS_MASK | \ + ID_AA64ISAR1_EL1_SB_MASK | \ + ID_AA64ISAR1_EL1_SPECRES_MASK | \ + ID_AA64ISAR1_EL1_BF16_MASK | \ + ID_AA64ISAR1_EL1_DGH_MASK | \ + ID_AA64ISAR1_EL1_I8MM_MASK \ ) #define PVM_ID_AA64ISAR2_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) \ + ID_AA64ISAR2_EL1_GPA3_MASK | \ + ID_AA64ISAR2_EL1_APA3_MASK \ ) u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id); diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 1e656d928819..bb024e0a5f75 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -106,7 +106,7 @@ static u64 get_pvm_id_aa64pfr1(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64PFR1_ALLOW; if (!kvm_has_mte(kvm)) - allow_mask &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); + allow_mask &= ~ID_AA64PFR1_EL1_MTE_MASK; return id_aa64pfr1_el1_sys_val & allow_mask; } @@ -171,10 +171,10 @@ static u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64ISAR1_ALLOW; if (!vcpu_has_ptrauth(vcpu)) - allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); + allow_mask &= ~(ID_AA64ISAR1_EL1_APA_MASK | + ID_AA64ISAR1_EL1_API_MASK | + ID_AA64ISAR1_EL1_GPA_MASK | + ID_AA64ISAR1_EL1_GPI_MASK); return id_aa64isar1_el1_sys_val & allow_mask; } @@ -184,8 +184,8 @@ static u64 get_pvm_id_aa64isar2(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64ISAR2_ALLOW; if (!vcpu_has_ptrauth(vcpu)) - allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); + allow_mask &= ~(ID_AA64ISAR2_EL1_APA3_MASK | + ID_AA64ISAR2_EL1_GPA3_MASK); return id_aa64isar2_el1_sys_val & allow_mask; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f97695bb8f64..12731ec000d2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1108,52 +1108,52 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r switch (id) { case SYS_ID_AA64PFR0_EL1: if (!vcpu_has_sve(vcpu)) - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2); + val &= ~ID_AA64PFR0_EL1_SVE_MASK; + val &= ~ID_AA64PFR0_EL1_AMU_MASK; + val &= ~ID_AA64PFR0_EL1_CSV2_MASK; val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV2, (u64)vcpu->kvm->arch.pfr0_csv2); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); + val &= ~ID_AA64PFR0_EL1_CSV3_MASK; val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV3, (u64)vcpu->kvm->arch.pfr0_csv3); if (kvm_vgic_global_state.type == VGIC_V3) { - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); + val &= ~ID_AA64PFR0_EL1_GIC_MASK; val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, GIC, 1); } break; case SYS_ID_AA64PFR1_EL1: if (!kvm_has_mte(vcpu->kvm)) - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); + val &= ~ID_AA64PFR1_EL1_MTE_MASK; - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); + val &= ~ID_AA64PFR1_EL1_SME_MASK; break; case SYS_ID_AA64ISAR1_EL1: if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); + val &= ~(ID_AA64ISAR1_EL1_APA_MASK | + ID_AA64ISAR1_EL1_API_MASK | + ID_AA64ISAR1_EL1_GPA_MASK | + ID_AA64ISAR1_EL1_GPI_MASK); break; case SYS_ID_AA64ISAR2_EL1: if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); + val &= ~(ID_AA64ISAR2_EL1_APA3_MASK | + ID_AA64ISAR2_EL1_GPA3_MASK); if (!cpus_have_final_cap(ARM64_HAS_WFXT)) - val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); + val &= ~ID_AA64ISAR2_EL1_WFxT_MASK; break; case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); + val &= ~ID_AA64DFR0_EL1_DebugVer_MASK; val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, DebugVer, 6); /* Set PMUver to the required version */ - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); + val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, vcpu_pmuver(vcpu)); /* Hide SPE from guests */ - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); + val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; break; case SYS_ID_DFR0_EL1: - val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); + val &= ~ID_DFR0_EL1_PerfMon_MASK; val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, pmuver_to_perfmon(vcpu_pmuver(vcpu))); break; @@ -1244,8 +1244,8 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, /* We can only differ with CSV[23], and anything else is an error */ val ^= read_id_reg(vcpu, rd); - val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) | - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3)); + val &= ~(ID_AA64PFR0_EL1_CSV2_MASK | + ID_AA64PFR0_EL1_CSV3_MASK); if (val) return -EINVAL; @@ -1282,7 +1282,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, /* We can only differ with PMUver, and anything else is an error */ val ^= read_id_reg(vcpu, rd); - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); + val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; if (val) return -EINVAL; @@ -1322,7 +1322,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, /* We can only differ with PerfMon, and anything else is an error */ val ^= read_id_reg(vcpu, rd); - val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); + val &= ~ID_DFR0_EL1_PerfMon_MASK; if (val) return -EINVAL; -- 2.30.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/2] KVM: arm64: Remove use of ARM64_FEATURE_MASK() @ 2022-12-21 18:06 ` Mark Brown 0 siblings, 0 replies; 15+ messages in thread From: Mark Brown @ 2022-12-21 18:06 UTC (permalink / raw) To: Marc Zyngier, James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon Cc: linux-arm-kernel, kvmarm, kvmarm, linux-kernel, Mark Brown The KVM code makes extensive use of ARM64_FEATURE_MASK() to generate a mask for fields in the ID registers. This macro has the assumption that all feature fields are 4 bits wide but the architecture has evolved to add fields with other widths, such as the 1 bit fields in ID_AA64SMFR0_EL1, so we need to adjust the We could fix this by making ARM64_FEATURE_MASK() use the generated macros that we have now but since one of these is a direct _MASK constant the result is something that's more verbose and less direct than just updating the users to directly use the generated mask macros, writing #define ARM64_FEATURE_MASK(x) (x##_MASK) obviously looks redundant and if we look at the users updating them turns val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); into the more direct val &= ~ID_AA64PFR0_EL1_CSV3_MASK; rather than updating the macro just remove the users. This is a relatively large code change but very mechanical. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> --- arch/arm64/include/asm/sysreg.h | 3 - arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 106 ++++++++++++------------- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 14 ++-- arch/arm64/kvm/sys_regs.c | 44 +++++----- 4 files changed, 82 insertions(+), 85 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 1312fb48f18b..3ac6ed1921c7 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -809,9 +809,6 @@ #define ARM64_FEATURE_FIELD_BITS 4 -/* Create a mask for the feature bits of the specified feature. */ -#define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT)) - #ifdef __ASSEMBLY__ .macro mrs_s, rt, sreg diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index f42cd1bdb45b..a8aa9efe6581 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -35,9 +35,9 @@ * - Data Independent Timing */ #define PVM_ID_AA64PFR0_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP) | \ - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD) | \ - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_DIT) \ + ID_AA64PFR0_EL1_FP_MASK | \ + ID_AA64PFR0_EL1_AdvSIMD_MASK | \ + ID_AA64PFR0_EL1_DIT_MASK \ ) /* @@ -62,8 +62,8 @@ * - Speculative Store Bypassing */ #define PVM_ID_AA64PFR1_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_BT) | \ - ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SSBS) \ + ID_AA64PFR1_EL1_BT_MASK | \ + ID_AA64PFR1_EL1_SSBS_MASK \ ) /* @@ -74,10 +74,10 @@ * - Non-context synchronizing exception entry and exit */ #define PVM_ID_AA64MMFR0_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGEND) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_SNSMEM) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGENDEL0) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_EXS) \ + ID_AA64MMFR0_EL1_BIGEND_MASK | \ + ID_AA64MMFR0_EL1_SNSMEM_MASK | \ + ID_AA64MMFR0_EL1_BIGENDEL0_MASK | \ + ID_AA64MMFR0_EL1_EXS_MASK \ ) /* @@ -100,12 +100,12 @@ * - Enhanced Translation Synchronization */ #define PVM_ID_AA64MMFR1_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_VMIDBits) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HPDS) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_PAN) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_SpecSEI) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_ETS) \ + ID_AA64MMFR1_EL1_HAFDBS_MASK | \ + ID_AA64MMFR1_EL1_VMIDBits_MASK | \ + ID_AA64MMFR1_EL1_HPDS_MASK | \ + ID_AA64MMFR1_EL1_PAN_MASK | \ + ID_AA64MMFR1_EL1_SpecSEI_MASK | \ + ID_AA64MMFR1_EL1_ETS_MASK \ ) /* @@ -120,14 +120,14 @@ * - E0PDx mechanism */ #define PVM_ID_AA64MMFR2_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_CnP) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_UAO) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IESB) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_AT) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IDS) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_TTL) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_BBM) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_E0PD) \ + ID_AA64MMFR2_EL1_CnP_MASK | \ + ID_AA64MMFR2_EL1_UAO_MASK | \ + ID_AA64MMFR2_EL1_IESB_MASK | \ + ID_AA64MMFR2_EL1_AT_MASK | \ + ID_AA64MMFR2_EL1_IDS_MASK | \ + ID_AA64MMFR2_EL1_TTL_MASK | \ + ID_AA64MMFR2_EL1_BBM_MASK | \ + ID_AA64MMFR2_EL1_E0PD_MASK \ ) /* @@ -159,42 +159,42 @@ * No restrictions on instructions implemented in AArch64. */ #define PVM_ID_AA64ISAR0_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_AES) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA1) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA2) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_CRC32) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMIC) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RDM) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM4) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_DP) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_FHM) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TS) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TLB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RNDR) \ + ID_AA64ISAR0_EL1_AES_MASK | \ + ID_AA64ISAR0_EL1_SHA1_MASK | \ + ID_AA64ISAR0_EL1_SHA2_MASK | \ + ID_AA64ISAR0_EL1_CRC32_MASK | \ + ID_AA64ISAR0_EL1_ATOMIC_MASK | \ + ID_AA64ISAR0_EL1_RDM_MASK | \ + ID_AA64ISAR0_EL1_SHA3_MASK | \ + ID_AA64ISAR0_EL1_SM3_MASK | \ + ID_AA64ISAR0_EL1_SM4_MASK | \ + ID_AA64ISAR0_EL1_DP_MASK | \ + ID_AA64ISAR0_EL1_FHM_MASK | \ + ID_AA64ISAR0_EL1_TS_MASK | \ + ID_AA64ISAR0_EL1_TLB_MASK | \ + ID_AA64ISAR0_EL1_RNDR_MASK \ ) #define PVM_ID_AA64ISAR1_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FCMA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_LRCPC) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FRINTTS) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SPECRES) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_BF16) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DGH) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) \ + ID_AA64ISAR1_EL1_DPB_MASK | \ + ID_AA64ISAR1_EL1_APA_MASK | \ + ID_AA64ISAR1_EL1_API_MASK | \ + ID_AA64ISAR1_EL1_JSCVT_MASK | \ + ID_AA64ISAR1_EL1_FCMA_MASK | \ + ID_AA64ISAR1_EL1_LRCPC_MASK | \ + ID_AA64ISAR1_EL1_GPA_MASK | \ + ID_AA64ISAR1_EL1_GPI_MASK | \ + ID_AA64ISAR1_EL1_FRINTTS_MASK | \ + ID_AA64ISAR1_EL1_SB_MASK | \ + ID_AA64ISAR1_EL1_SPECRES_MASK | \ + ID_AA64ISAR1_EL1_BF16_MASK | \ + ID_AA64ISAR1_EL1_DGH_MASK | \ + ID_AA64ISAR1_EL1_I8MM_MASK \ ) #define PVM_ID_AA64ISAR2_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) \ + ID_AA64ISAR2_EL1_GPA3_MASK | \ + ID_AA64ISAR2_EL1_APA3_MASK \ ) u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id); diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 1e656d928819..bb024e0a5f75 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -106,7 +106,7 @@ static u64 get_pvm_id_aa64pfr1(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64PFR1_ALLOW; if (!kvm_has_mte(kvm)) - allow_mask &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); + allow_mask &= ~ID_AA64PFR1_EL1_MTE_MASK; return id_aa64pfr1_el1_sys_val & allow_mask; } @@ -171,10 +171,10 @@ static u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64ISAR1_ALLOW; if (!vcpu_has_ptrauth(vcpu)) - allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); + allow_mask &= ~(ID_AA64ISAR1_EL1_APA_MASK | + ID_AA64ISAR1_EL1_API_MASK | + ID_AA64ISAR1_EL1_GPA_MASK | + ID_AA64ISAR1_EL1_GPI_MASK); return id_aa64isar1_el1_sys_val & allow_mask; } @@ -184,8 +184,8 @@ static u64 get_pvm_id_aa64isar2(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64ISAR2_ALLOW; if (!vcpu_has_ptrauth(vcpu)) - allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); + allow_mask &= ~(ID_AA64ISAR2_EL1_APA3_MASK | + ID_AA64ISAR2_EL1_GPA3_MASK); return id_aa64isar2_el1_sys_val & allow_mask; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f97695bb8f64..12731ec000d2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1108,52 +1108,52 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r switch (id) { case SYS_ID_AA64PFR0_EL1: if (!vcpu_has_sve(vcpu)) - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2); + val &= ~ID_AA64PFR0_EL1_SVE_MASK; + val &= ~ID_AA64PFR0_EL1_AMU_MASK; + val &= ~ID_AA64PFR0_EL1_CSV2_MASK; val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV2, (u64)vcpu->kvm->arch.pfr0_csv2); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); + val &= ~ID_AA64PFR0_EL1_CSV3_MASK; val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV3, (u64)vcpu->kvm->arch.pfr0_csv3); if (kvm_vgic_global_state.type == VGIC_V3) { - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); + val &= ~ID_AA64PFR0_EL1_GIC_MASK; val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, GIC, 1); } break; case SYS_ID_AA64PFR1_EL1: if (!kvm_has_mte(vcpu->kvm)) - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); + val &= ~ID_AA64PFR1_EL1_MTE_MASK; - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); + val &= ~ID_AA64PFR1_EL1_SME_MASK; break; case SYS_ID_AA64ISAR1_EL1: if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); + val &= ~(ID_AA64ISAR1_EL1_APA_MASK | + ID_AA64ISAR1_EL1_API_MASK | + ID_AA64ISAR1_EL1_GPA_MASK | + ID_AA64ISAR1_EL1_GPI_MASK); break; case SYS_ID_AA64ISAR2_EL1: if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); + val &= ~(ID_AA64ISAR2_EL1_APA3_MASK | + ID_AA64ISAR2_EL1_GPA3_MASK); if (!cpus_have_final_cap(ARM64_HAS_WFXT)) - val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); + val &= ~ID_AA64ISAR2_EL1_WFxT_MASK; break; case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); + val &= ~ID_AA64DFR0_EL1_DebugVer_MASK; val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, DebugVer, 6); /* Set PMUver to the required version */ - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); + val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, vcpu_pmuver(vcpu)); /* Hide SPE from guests */ - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); + val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; break; case SYS_ID_DFR0_EL1: - val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); + val &= ~ID_DFR0_EL1_PerfMon_MASK; val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, pmuver_to_perfmon(vcpu_pmuver(vcpu))); break; @@ -1244,8 +1244,8 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, /* We can only differ with CSV[23], and anything else is an error */ val ^= read_id_reg(vcpu, rd); - val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) | - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3)); + val &= ~(ID_AA64PFR0_EL1_CSV2_MASK | + ID_AA64PFR0_EL1_CSV3_MASK); if (val) return -EINVAL; @@ -1282,7 +1282,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, /* We can only differ with PMUver, and anything else is an error */ val ^= read_id_reg(vcpu, rd); - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); + val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; if (val) return -EINVAL; @@ -1322,7 +1322,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, /* We can only differ with PerfMon, and anything else is an error */ val ^= read_id_reg(vcpu, rd); - val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); + val &= ~ID_DFR0_EL1_PerfMon_MASK; if (val) return -EINVAL; -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/2] KVM: arm64: Remove use of ARM64_FEATURE_MASK() @ 2022-12-21 18:06 ` Mark Brown 0 siblings, 0 replies; 15+ messages in thread From: Mark Brown @ 2022-12-21 18:06 UTC (permalink / raw) To: Marc Zyngier, James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon Cc: linux-arm-kernel, kvmarm, kvmarm, linux-kernel, Mark Brown The KVM code makes extensive use of ARM64_FEATURE_MASK() to generate a mask for fields in the ID registers. This macro has the assumption that all feature fields are 4 bits wide but the architecture has evolved to add fields with other widths, such as the 1 bit fields in ID_AA64SMFR0_EL1, so we need to adjust the We could fix this by making ARM64_FEATURE_MASK() use the generated macros that we have now but since one of these is a direct _MASK constant the result is something that's more verbose and less direct than just updating the users to directly use the generated mask macros, writing #define ARM64_FEATURE_MASK(x) (x##_MASK) obviously looks redundant and if we look at the users updating them turns val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); into the more direct val &= ~ID_AA64PFR0_EL1_CSV3_MASK; rather than updating the macro just remove the users. This is a relatively large code change but very mechanical. No functional change. Signed-off-by: Mark Brown <broonie@kernel.org> --- arch/arm64/include/asm/sysreg.h | 3 - arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 106 ++++++++++++------------- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 14 ++-- arch/arm64/kvm/sys_regs.c | 44 +++++----- 4 files changed, 82 insertions(+), 85 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 1312fb48f18b..3ac6ed1921c7 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -809,9 +809,6 @@ #define ARM64_FEATURE_FIELD_BITS 4 -/* Create a mask for the feature bits of the specified feature. */ -#define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT)) - #ifdef __ASSEMBLY__ .macro mrs_s, rt, sreg diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h index f42cd1bdb45b..a8aa9efe6581 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h @@ -35,9 +35,9 @@ * - Data Independent Timing */ #define PVM_ID_AA64PFR0_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_FP) | \ - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AdvSIMD) | \ - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_DIT) \ + ID_AA64PFR0_EL1_FP_MASK | \ + ID_AA64PFR0_EL1_AdvSIMD_MASK | \ + ID_AA64PFR0_EL1_DIT_MASK \ ) /* @@ -62,8 +62,8 @@ * - Speculative Store Bypassing */ #define PVM_ID_AA64PFR1_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_BT) | \ - ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SSBS) \ + ID_AA64PFR1_EL1_BT_MASK | \ + ID_AA64PFR1_EL1_SSBS_MASK \ ) /* @@ -74,10 +74,10 @@ * - Non-context synchronizing exception entry and exit */ #define PVM_ID_AA64MMFR0_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGEND) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_SNSMEM) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGENDEL0) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_EXS) \ + ID_AA64MMFR0_EL1_BIGEND_MASK | \ + ID_AA64MMFR0_EL1_SNSMEM_MASK | \ + ID_AA64MMFR0_EL1_BIGENDEL0_MASK | \ + ID_AA64MMFR0_EL1_EXS_MASK \ ) /* @@ -100,12 +100,12 @@ * - Enhanced Translation Synchronization */ #define PVM_ID_AA64MMFR1_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_VMIDBits) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HPDS) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_PAN) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_SpecSEI) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_ETS) \ + ID_AA64MMFR1_EL1_HAFDBS_MASK | \ + ID_AA64MMFR1_EL1_VMIDBits_MASK | \ + ID_AA64MMFR1_EL1_HPDS_MASK | \ + ID_AA64MMFR1_EL1_PAN_MASK | \ + ID_AA64MMFR1_EL1_SpecSEI_MASK | \ + ID_AA64MMFR1_EL1_ETS_MASK \ ) /* @@ -120,14 +120,14 @@ * - E0PDx mechanism */ #define PVM_ID_AA64MMFR2_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_CnP) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_UAO) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IESB) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_AT) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IDS) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_TTL) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_BBM) | \ - ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_E0PD) \ + ID_AA64MMFR2_EL1_CnP_MASK | \ + ID_AA64MMFR2_EL1_UAO_MASK | \ + ID_AA64MMFR2_EL1_IESB_MASK | \ + ID_AA64MMFR2_EL1_AT_MASK | \ + ID_AA64MMFR2_EL1_IDS_MASK | \ + ID_AA64MMFR2_EL1_TTL_MASK | \ + ID_AA64MMFR2_EL1_BBM_MASK | \ + ID_AA64MMFR2_EL1_E0PD_MASK \ ) /* @@ -159,42 +159,42 @@ * No restrictions on instructions implemented in AArch64. */ #define PVM_ID_AA64ISAR0_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_AES) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA1) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA2) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_CRC32) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMIC) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RDM) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM4) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_DP) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_FHM) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TS) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TLB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RNDR) \ + ID_AA64ISAR0_EL1_AES_MASK | \ + ID_AA64ISAR0_EL1_SHA1_MASK | \ + ID_AA64ISAR0_EL1_SHA2_MASK | \ + ID_AA64ISAR0_EL1_CRC32_MASK | \ + ID_AA64ISAR0_EL1_ATOMIC_MASK | \ + ID_AA64ISAR0_EL1_RDM_MASK | \ + ID_AA64ISAR0_EL1_SHA3_MASK | \ + ID_AA64ISAR0_EL1_SM3_MASK | \ + ID_AA64ISAR0_EL1_SM4_MASK | \ + ID_AA64ISAR0_EL1_DP_MASK | \ + ID_AA64ISAR0_EL1_FHM_MASK | \ + ID_AA64ISAR0_EL1_TS_MASK | \ + ID_AA64ISAR0_EL1_TLB_MASK | \ + ID_AA64ISAR0_EL1_RNDR_MASK \ ) #define PVM_ID_AA64ISAR1_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FCMA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_LRCPC) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FRINTTS) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SB) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SPECRES) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_BF16) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DGH) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) \ + ID_AA64ISAR1_EL1_DPB_MASK | \ + ID_AA64ISAR1_EL1_APA_MASK | \ + ID_AA64ISAR1_EL1_API_MASK | \ + ID_AA64ISAR1_EL1_JSCVT_MASK | \ + ID_AA64ISAR1_EL1_FCMA_MASK | \ + ID_AA64ISAR1_EL1_LRCPC_MASK | \ + ID_AA64ISAR1_EL1_GPA_MASK | \ + ID_AA64ISAR1_EL1_GPI_MASK | \ + ID_AA64ISAR1_EL1_FRINTTS_MASK | \ + ID_AA64ISAR1_EL1_SB_MASK | \ + ID_AA64ISAR1_EL1_SPECRES_MASK | \ + ID_AA64ISAR1_EL1_BF16_MASK | \ + ID_AA64ISAR1_EL1_DGH_MASK | \ + ID_AA64ISAR1_EL1_I8MM_MASK \ ) #define PVM_ID_AA64ISAR2_ALLOW (\ - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \ - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) \ + ID_AA64ISAR2_EL1_GPA3_MASK | \ + ID_AA64ISAR2_EL1_APA3_MASK \ ) u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id); diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 1e656d928819..bb024e0a5f75 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -106,7 +106,7 @@ static u64 get_pvm_id_aa64pfr1(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64PFR1_ALLOW; if (!kvm_has_mte(kvm)) - allow_mask &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); + allow_mask &= ~ID_AA64PFR1_EL1_MTE_MASK; return id_aa64pfr1_el1_sys_val & allow_mask; } @@ -171,10 +171,10 @@ static u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64ISAR1_ALLOW; if (!vcpu_has_ptrauth(vcpu)) - allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); + allow_mask &= ~(ID_AA64ISAR1_EL1_APA_MASK | + ID_AA64ISAR1_EL1_API_MASK | + ID_AA64ISAR1_EL1_GPA_MASK | + ID_AA64ISAR1_EL1_GPI_MASK); return id_aa64isar1_el1_sys_val & allow_mask; } @@ -184,8 +184,8 @@ static u64 get_pvm_id_aa64isar2(const struct kvm_vcpu *vcpu) u64 allow_mask = PVM_ID_AA64ISAR2_ALLOW; if (!vcpu_has_ptrauth(vcpu)) - allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); + allow_mask &= ~(ID_AA64ISAR2_EL1_APA3_MASK | + ID_AA64ISAR2_EL1_GPA3_MASK); return id_aa64isar2_el1_sys_val & allow_mask; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f97695bb8f64..12731ec000d2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1108,52 +1108,52 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r switch (id) { case SYS_ID_AA64PFR0_EL1: if (!vcpu_has_sve(vcpu)) - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2); + val &= ~ID_AA64PFR0_EL1_SVE_MASK; + val &= ~ID_AA64PFR0_EL1_AMU_MASK; + val &= ~ID_AA64PFR0_EL1_CSV2_MASK; val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV2, (u64)vcpu->kvm->arch.pfr0_csv2); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); + val &= ~ID_AA64PFR0_EL1_CSV3_MASK; val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, CSV3, (u64)vcpu->kvm->arch.pfr0_csv3); if (kvm_vgic_global_state.type == VGIC_V3) { - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC); + val &= ~ID_AA64PFR0_EL1_GIC_MASK; val |= SYS_FIELD_PREP(ID_AA64PFR0_EL1, GIC, 1); } break; case SYS_ID_AA64PFR1_EL1: if (!kvm_has_mte(vcpu->kvm)) - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE); + val &= ~ID_AA64PFR1_EL1_MTE_MASK; - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); + val &= ~ID_AA64PFR1_EL1_SME_MASK; break; case SYS_ID_AA64ISAR1_EL1: if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI)); + val &= ~(ID_AA64ISAR1_EL1_APA_MASK | + ID_AA64ISAR1_EL1_API_MASK | + ID_AA64ISAR1_EL1_GPA_MASK | + ID_AA64ISAR1_EL1_GPI_MASK); break; case SYS_ID_AA64ISAR2_EL1: if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3)); + val &= ~(ID_AA64ISAR2_EL1_APA3_MASK | + ID_AA64ISAR2_EL1_GPA3_MASK); if (!cpus_have_final_cap(ARM64_HAS_WFXT)) - val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); + val &= ~ID_AA64ISAR2_EL1_WFxT_MASK; break; case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer); + val &= ~ID_AA64DFR0_EL1_DebugVer_MASK; val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, DebugVer, 6); /* Set PMUver to the required version */ - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); + val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer, vcpu_pmuver(vcpu)); /* Hide SPE from guests */ - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer); + val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; break; case SYS_ID_DFR0_EL1: - val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); + val &= ~ID_DFR0_EL1_PerfMon_MASK; val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, pmuver_to_perfmon(vcpu_pmuver(vcpu))); break; @@ -1244,8 +1244,8 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, /* We can only differ with CSV[23], and anything else is an error */ val ^= read_id_reg(vcpu, rd); - val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) | - ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3)); + val &= ~(ID_AA64PFR0_EL1_CSV2_MASK | + ID_AA64PFR0_EL1_CSV3_MASK); if (val) return -EINVAL; @@ -1282,7 +1282,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, /* We can only differ with PMUver, and anything else is an error */ val ^= read_id_reg(vcpu, rd); - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer); + val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; if (val) return -EINVAL; @@ -1322,7 +1322,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, /* We can only differ with PerfMon, and anything else is an error */ val ^= read_id_reg(vcpu, rd); - val &= ~ARM64_FEATURE_MASK(ID_DFR0_EL1_PerfMon); + val &= ~ID_DFR0_EL1_PerfMon_MASK; if (val) return -EINVAL; -- 2.30.2 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] KVM: arm64: Remove use of ARM64_FEATURE_MASK() @ 2022-12-22 12:23 ` Marc Zyngier 0 siblings, 0 replies; 15+ messages in thread From: Marc Zyngier @ 2022-12-22 12:23 UTC (permalink / raw) To: Mark Brown Cc: Will Deacon, linux-kernel, Catalin Marinas, kvmarm, kvmarm, linux-arm-kernel On Wed, 21 Dec 2022 18:06:10 +0000, Mark Brown <broonie@kernel.org> wrote: > > The KVM code makes extensive use of ARM64_FEATURE_MASK() to generate a > mask for fields in the ID registers. This macro has the assumption that > all feature fields are 4 bits wide but the architecture has evolved to > add fields with other widths, such as the 1 bit fields in ID_AA64SMFR0_EL1, > so we need to adjust the > > We could fix this by making ARM64_FEATURE_MASK() use the generated macros > that we have now but since one of these is a direct _MASK constant the > result is something that's more verbose and less direct than just updating > the users to directly use the generated mask macros, writing > > #define ARM64_FEATURE_MASK(x) (x##_MASK) > > obviously looks redundant and if we look at the users updating them turns > > val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); > > into the more direct > > val &= ~ID_AA64PFR0_EL1_CSV3_MASK; If the two are strictly equivalent, then let's use the former as it results in a tiny diff. Constantly repainting these files causes no end of conflicts when rebasing large series (pKVM, NV...), and makes backporting of fixes much harder than it should be. Specially considering that there is a single occcurence of an ID register with non-4bit fields. Just put a FIXME in the various files so that people do the repainting as they change this code. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] KVM: arm64: Remove use of ARM64_FEATURE_MASK() @ 2022-12-22 12:23 ` Marc Zyngier 0 siblings, 0 replies; 15+ messages in thread From: Marc Zyngier @ 2022-12-22 12:23 UTC (permalink / raw) To: Mark Brown Cc: James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon, linux-arm-kernel, kvmarm, kvmarm, linux-kernel On Wed, 21 Dec 2022 18:06:10 +0000, Mark Brown <broonie@kernel.org> wrote: > > The KVM code makes extensive use of ARM64_FEATURE_MASK() to generate a > mask for fields in the ID registers. This macro has the assumption that > all feature fields are 4 bits wide but the architecture has evolved to > add fields with other widths, such as the 1 bit fields in ID_AA64SMFR0_EL1, > so we need to adjust the > > We could fix this by making ARM64_FEATURE_MASK() use the generated macros > that we have now but since one of these is a direct _MASK constant the > result is something that's more verbose and less direct than just updating > the users to directly use the generated mask macros, writing > > #define ARM64_FEATURE_MASK(x) (x##_MASK) > > obviously looks redundant and if we look at the users updating them turns > > val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); > > into the more direct > > val &= ~ID_AA64PFR0_EL1_CSV3_MASK; If the two are strictly equivalent, then let's use the former as it results in a tiny diff. Constantly repainting these files causes no end of conflicts when rebasing large series (pKVM, NV...), and makes backporting of fixes much harder than it should be. Specially considering that there is a single occcurence of an ID register with non-4bit fields. Just put a FIXME in the various files so that people do the repainting as they change this code. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] KVM: arm64: Remove use of ARM64_FEATURE_MASK() @ 2022-12-22 12:23 ` Marc Zyngier 0 siblings, 0 replies; 15+ messages in thread From: Marc Zyngier @ 2022-12-22 12:23 UTC (permalink / raw) To: Mark Brown Cc: James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon, linux-arm-kernel, kvmarm, kvmarm, linux-kernel On Wed, 21 Dec 2022 18:06:10 +0000, Mark Brown <broonie@kernel.org> wrote: > > The KVM code makes extensive use of ARM64_FEATURE_MASK() to generate a > mask for fields in the ID registers. This macro has the assumption that > all feature fields are 4 bits wide but the architecture has evolved to > add fields with other widths, such as the 1 bit fields in ID_AA64SMFR0_EL1, > so we need to adjust the > > We could fix this by making ARM64_FEATURE_MASK() use the generated macros > that we have now but since one of these is a direct _MASK constant the > result is something that's more verbose and less direct than just updating > the users to directly use the generated mask macros, writing > > #define ARM64_FEATURE_MASK(x) (x##_MASK) > > obviously looks redundant and if we look at the users updating them turns > > val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3); > > into the more direct > > val &= ~ID_AA64PFR0_EL1_CSV3_MASK; If the two are strictly equivalent, then let's use the former as it results in a tiny diff. Constantly repainting these files causes no end of conflicts when rebasing large series (pKVM, NV...), and makes backporting of fixes much harder than it should be. Specially considering that there is a single occcurence of an ID register with non-4bit fields. Just put a FIXME in the various files so that people do the repainting as they change this code. Thanks, M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] KVM: arm64: Remove use of ARM64_FEATURE_MASK() @ 2022-12-22 12:34 ` Mark Brown 0 siblings, 0 replies; 15+ messages in thread From: Mark Brown @ 2022-12-22 12:34 UTC (permalink / raw) To: Marc Zyngier Cc: Will Deacon, linux-kernel, Catalin Marinas, kvmarm, kvmarm, linux-arm-kernel [-- Attachment #1.1: Type: text/plain, Size: 1105 bytes --] On Thu, Dec 22, 2022 at 12:23:49PM +0000, Marc Zyngier wrote: > Mark Brown <broonie@kernel.org> wrote: > > the users to directly use the generated mask macros, writing > > > > #define ARM64_FEATURE_MASK(x) (x##_MASK) > > > > obviously looks redundant and if we look at the users updating them turns > If the two are strictly equivalent, then let's use the former as it > results in a tiny diff. They are. I'm tempted to move the define to a KVM header to discourage new use. > Constantly repainting these files causes no end of conflicts when > rebasing large series (pKVM, NV...), and makes backporting of fixes > much harder than it should be. Specially considering that there is a > single occcurence of an ID register with non-4bit fields. > Just put a FIXME in the various files so that people do the repainting > as they change this code. OK. It does result in the half transitioned files looking really messy which for the main arm64 code I'd expect to generate complaints but like you say the conversions have their disadvantages too so if you're OK with it. [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] [-- Attachment #2: Type: text/plain, Size: 151 bytes --] _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] KVM: arm64: Remove use of ARM64_FEATURE_MASK() @ 2022-12-22 12:34 ` Mark Brown 0 siblings, 0 replies; 15+ messages in thread From: Mark Brown @ 2022-12-22 12:34 UTC (permalink / raw) To: Marc Zyngier Cc: James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon, linux-arm-kernel, kvmarm, kvmarm, linux-kernel [-- Attachment #1.1: Type: text/plain, Size: 1105 bytes --] On Thu, Dec 22, 2022 at 12:23:49PM +0000, Marc Zyngier wrote: > Mark Brown <broonie@kernel.org> wrote: > > the users to directly use the generated mask macros, writing > > > > #define ARM64_FEATURE_MASK(x) (x##_MASK) > > > > obviously looks redundant and if we look at the users updating them turns > If the two are strictly equivalent, then let's use the former as it > results in a tiny diff. They are. I'm tempted to move the define to a KVM header to discourage new use. > Constantly repainting these files causes no end of conflicts when > rebasing large series (pKVM, NV...), and makes backporting of fixes > much harder than it should be. Specially considering that there is a > single occcurence of an ID register with non-4bit fields. > Just put a FIXME in the various files so that people do the repainting > as they change this code. OK. It does result in the half transitioned files looking really messy which for the main arm64 code I'd expect to generate complaints but like you say the conversions have their disadvantages too so if you're OK with it. [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] [-- Attachment #2: Type: text/plain, Size: 176 bytes --] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] KVM: arm64: Remove use of ARM64_FEATURE_MASK() @ 2022-12-22 12:34 ` Mark Brown 0 siblings, 0 replies; 15+ messages in thread From: Mark Brown @ 2022-12-22 12:34 UTC (permalink / raw) To: Marc Zyngier Cc: James Morse, Alexandru Elisei, Suzuki K Poulose, Oliver Upton, Catalin Marinas, Will Deacon, linux-arm-kernel, kvmarm, kvmarm, linux-kernel [-- Attachment #1: Type: text/plain, Size: 1105 bytes --] On Thu, Dec 22, 2022 at 12:23:49PM +0000, Marc Zyngier wrote: > Mark Brown <broonie@kernel.org> wrote: > > the users to directly use the generated mask macros, writing > > > > #define ARM64_FEATURE_MASK(x) (x##_MASK) > > > > obviously looks redundant and if we look at the users updating them turns > If the two are strictly equivalent, then let's use the former as it > results in a tiny diff. They are. I'm tempted to move the define to a KVM header to discourage new use. > Constantly repainting these files causes no end of conflicts when > rebasing large series (pKVM, NV...), and makes backporting of fixes > much harder than it should be. Specially considering that there is a > single occcurence of an ID register with non-4bit fields. > Just put a FIXME in the various files so that people do the repainting > as they change this code. OK. It does result in the half transitioned files looking really messy which for the main arm64 code I'd expect to generate complaints but like you say the conversions have their disadvantages too so if you're OK with it. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
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2022-12-21 18:06 [PATCH 0/2] KVM: arm64: syreg cleanups/fixes Mark Brown
2022-12-21 18:06 ` Mark Brown
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2022-12-21 18:06 ` [PATCH 1/2] KVM: arm64: Convert non-GIC code to SYS_FIELD_{GET,PREP} Mark Brown
2022-12-21 18:06 ` Mark Brown
2022-12-21 18:06 ` Mark Brown
2022-12-21 18:06 ` [PATCH 2/2] KVM: arm64: Remove use of ARM64_FEATURE_MASK() Mark Brown
2022-12-21 18:06 ` Mark Brown
2022-12-21 18:06 ` Mark Brown
2022-12-22 12:23 ` Marc Zyngier
2022-12-22 12:23 ` Marc Zyngier
2022-12-22 12:23 ` Marc Zyngier
2022-12-22 12:34 ` Mark Brown
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