From: Marc Zyngier <maz@kernel.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2] arm64: Disable EL2 traps for BRBE instructions executed in EL1
Date: Mon, 15 May 2023 14:42:08 +0100 [thread overview]
Message-ID: <86ilctn233.wl-maz@kernel.org> (raw)
In-Reply-To: <20230515105328.239204-1-anshuman.khandual@arm.com>
On Mon, 15 May 2023 11:53:28 +0100,
Anshuman Khandual <anshuman.khandual@arm.com> wrote:
>
> This disables EL2 traps for BRBE instructions executed in EL1. This would
> enable BRBE to be configured and used successfully in the guest kernel.
> While here, this updates Documentation/arm64/booting.rst as well.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> This patch applies on v6.4-rc2
>
> Changes in V2:
>
> - Updated Documentation/arm64/booting.rst
>
> Changes in V1:
>
> https://lore.kernel.org/all/20230324055127.2228330-1-anshuman.khandual@arm.com/
>
> Documentation/arm64/booting.rst | 8 ++++++++
> arch/arm64/include/asm/el2_setup.h | 10 ++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
> index ffeccdd6bdac..cb9e151f6928 100644
> --- a/Documentation/arm64/booting.rst
> +++ b/Documentation/arm64/booting.rst
> @@ -379,6 +379,14 @@ Before jumping into the kernel, the following conditions must be met:
>
> - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
>
> + For CPUs with the Branch Record Buffer Extension (FEAT_BRBE):
> +
> + - If the kernel is entered at EL1 and EL2 is present:
> +
> + - HFGITR_EL2.nBRBINJ (bit 55) must be initialised to 0b1.
> +
> + - HFGITR_EL2.nBRBIALL (bit 56) must be initialised to 0b1.
> +
> The requirements described above for CPU mode, caches, MMUs, architected
> timers, coherency and system registers apply to all CPUs. All CPUs must
> enter the kernel in the same exception level. Where the values documented
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index 037724b19c5c..06bf321a17be 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -161,6 +161,16 @@
> msr_s SYS_HFGWTR_EL2, x0
> msr_s SYS_HFGITR_EL2, xzr
>
> + mrs x1, id_aa64dfr0_el1
> + ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4
> + cbz x1, .Lskip_brbe_\@
> +
> + mov x0, xzr
> + orr x0, x0, #HFGITR_EL2_nBRBIALL
> + orr x0, x0, #HFGITR_EL2_nBRBINJ
> + msr_s SYS_HFGITR_EL2, x0
This will break badly if someone inserts something between this hunk
and the initial setting of HFGITR_EL2. I'd really prefer a RMW
approach. It's not that this code has to be optimised anyway.
M.
--
Without deviation from the norm, progress is not possible.
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2] arm64: Disable EL2 traps for BRBE instructions executed in EL1
Date: Mon, 15 May 2023 14:42:08 +0100 [thread overview]
Message-ID: <86ilctn233.wl-maz@kernel.org> (raw)
In-Reply-To: <20230515105328.239204-1-anshuman.khandual@arm.com>
On Mon, 15 May 2023 11:53:28 +0100,
Anshuman Khandual <anshuman.khandual@arm.com> wrote:
>
> This disables EL2 traps for BRBE instructions executed in EL1. This would
> enable BRBE to be configured and used successfully in the guest kernel.
> While here, this updates Documentation/arm64/booting.rst as well.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> This patch applies on v6.4-rc2
>
> Changes in V2:
>
> - Updated Documentation/arm64/booting.rst
>
> Changes in V1:
>
> https://lore.kernel.org/all/20230324055127.2228330-1-anshuman.khandual@arm.com/
>
> Documentation/arm64/booting.rst | 8 ++++++++
> arch/arm64/include/asm/el2_setup.h | 10 ++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
> index ffeccdd6bdac..cb9e151f6928 100644
> --- a/Documentation/arm64/booting.rst
> +++ b/Documentation/arm64/booting.rst
> @@ -379,6 +379,14 @@ Before jumping into the kernel, the following conditions must be met:
>
> - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
>
> + For CPUs with the Branch Record Buffer Extension (FEAT_BRBE):
> +
> + - If the kernel is entered at EL1 and EL2 is present:
> +
> + - HFGITR_EL2.nBRBINJ (bit 55) must be initialised to 0b1.
> +
> + - HFGITR_EL2.nBRBIALL (bit 56) must be initialised to 0b1.
> +
> The requirements described above for CPU mode, caches, MMUs, architected
> timers, coherency and system registers apply to all CPUs. All CPUs must
> enter the kernel in the same exception level. Where the values documented
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index 037724b19c5c..06bf321a17be 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -161,6 +161,16 @@
> msr_s SYS_HFGWTR_EL2, x0
> msr_s SYS_HFGITR_EL2, xzr
>
> + mrs x1, id_aa64dfr0_el1
> + ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4
> + cbz x1, .Lskip_brbe_\@
> +
> + mov x0, xzr
> + orr x0, x0, #HFGITR_EL2_nBRBIALL
> + orr x0, x0, #HFGITR_EL2_nBRBINJ
> + msr_s SYS_HFGITR_EL2, x0
This will break badly if someone inserts something between this hunk
and the initial setting of HFGITR_EL2. I'd really prefer a RMW
approach. It's not that this code has to be optimised anyway.
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2023-05-15 13:42 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-15 10:53 [PATCH V2] arm64: Disable EL2 traps for BRBE instructions executed in EL1 Anshuman Khandual
2023-05-15 10:53 ` Anshuman Khandual
2023-05-15 13:42 ` Marc Zyngier [this message]
2023-05-15 13:42 ` Marc Zyngier
2023-05-16 2:43 ` Anshuman Khandual
2023-05-16 2:43 ` Anshuman Khandual
2023-05-16 7:18 ` Marc Zyngier
2023-05-16 7:18 ` Marc Zyngier
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