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From: Marc Zyngier <maz@kernel.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2] arm64: Disable EL2 traps for BRBE instructions executed in EL1
Date: Tue, 16 May 2023 08:18:54 +0100	[thread overview]
Message-ID: <87bkikwxpd.wl-maz@kernel.org> (raw)
In-Reply-To: <b9a15953-ad88-7ca6-f485-116ac0217aae@arm.com>

On Tue, 16 May 2023 03:43:27 +0100,
Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> 
> 
> 
> On 5/15/23 19:12, Marc Zyngier wrote:
> > On Mon, 15 May 2023 11:53:28 +0100,
> > Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> >>

[...]

> >> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> >> index 037724b19c5c..06bf321a17be 100644
> >> --- a/arch/arm64/include/asm/el2_setup.h
> >> +++ b/arch/arm64/include/asm/el2_setup.h
> >> @@ -161,6 +161,16 @@
> >>  	msr_s	SYS_HFGWTR_EL2, x0
> >>  	msr_s	SYS_HFGITR_EL2, xzr
> >>  
> >> +	mrs	x1, id_aa64dfr0_el1
> >> +	ubfx	x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4
> >> +	cbz	x1, .Lskip_brbe_\@
> >> +
> >> +	mov	x0, xzr
> >> +	orr	x0, x0, #HFGITR_EL2_nBRBIALL
> >> +	orr	x0, x0, #HFGITR_EL2_nBRBINJ
> >> +	msr_s	SYS_HFGITR_EL2, x0
> > 
> > This will break badly if someone inserts something between this hunk
> > and the initial setting of HFGITR_EL2. I'd really prefer a RMW
> > approach.  It's not that this code has to be optimised anyway.
> 
> Something like this instead ? So that even if there are more changes
> before this hunk, it will be fetched correctly with first mrs_s and
> only additional bits related to BRBE will be set there after.
> 
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index 037724b19c5c..bfaf41ad9c4e 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -161,6 +161,16 @@
>         msr_s   SYS_HFGWTR_EL2, x0
>         msr_s   SYS_HFGITR_EL2, xzr
>  
> +       mrs     x1, id_aa64dfr0_el1
> +       ubfx    x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4
> +       cbz     x1, .Lskip_brbe_\@
> +
> +       mrs_s   x0, SYS_HFGITR_EL2
> +       orr     x0, x0, #HFGITR_EL2_nBRBIALL
> +       orr     x0, x0, #HFGITR_EL2_nBRBINJ
> +       msr_s   SYS_HFGITR_EL2, x0
> +
> +.Lskip_brbe_\@:
>         mrs     x1, id_aa64pfr0_el1             // AMU traps UNDEF without AMU
>         ubfx    x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
>         cbz     x1, .Lskip_fgt_\@

Yes, this is much better.

	M.

-- 
Without deviation from the norm, progress is not possible.

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WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2] arm64: Disable EL2 traps for BRBE instructions executed in EL1
Date: Tue, 16 May 2023 08:18:54 +0100	[thread overview]
Message-ID: <87bkikwxpd.wl-maz@kernel.org> (raw)
In-Reply-To: <b9a15953-ad88-7ca6-f485-116ac0217aae@arm.com>

On Tue, 16 May 2023 03:43:27 +0100,
Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> 
> 
> 
> On 5/15/23 19:12, Marc Zyngier wrote:
> > On Mon, 15 May 2023 11:53:28 +0100,
> > Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> >>

[...]

> >> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> >> index 037724b19c5c..06bf321a17be 100644
> >> --- a/arch/arm64/include/asm/el2_setup.h
> >> +++ b/arch/arm64/include/asm/el2_setup.h
> >> @@ -161,6 +161,16 @@
> >>  	msr_s	SYS_HFGWTR_EL2, x0
> >>  	msr_s	SYS_HFGITR_EL2, xzr
> >>  
> >> +	mrs	x1, id_aa64dfr0_el1
> >> +	ubfx	x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4
> >> +	cbz	x1, .Lskip_brbe_\@
> >> +
> >> +	mov	x0, xzr
> >> +	orr	x0, x0, #HFGITR_EL2_nBRBIALL
> >> +	orr	x0, x0, #HFGITR_EL2_nBRBINJ
> >> +	msr_s	SYS_HFGITR_EL2, x0
> > 
> > This will break badly if someone inserts something between this hunk
> > and the initial setting of HFGITR_EL2. I'd really prefer a RMW
> > approach.  It's not that this code has to be optimised anyway.
> 
> Something like this instead ? So that even if there are more changes
> before this hunk, it will be fetched correctly with first mrs_s and
> only additional bits related to BRBE will be set there after.
> 
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index 037724b19c5c..bfaf41ad9c4e 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -161,6 +161,16 @@
>         msr_s   SYS_HFGWTR_EL2, x0
>         msr_s   SYS_HFGITR_EL2, xzr
>  
> +       mrs     x1, id_aa64dfr0_el1
> +       ubfx    x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4
> +       cbz     x1, .Lskip_brbe_\@
> +
> +       mrs_s   x0, SYS_HFGITR_EL2
> +       orr     x0, x0, #HFGITR_EL2_nBRBIALL
> +       orr     x0, x0, #HFGITR_EL2_nBRBINJ
> +       msr_s   SYS_HFGITR_EL2, x0
> +
> +.Lskip_brbe_\@:
>         mrs     x1, id_aa64pfr0_el1             // AMU traps UNDEF without AMU
>         ubfx    x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
>         cbz     x1, .Lskip_fgt_\@

Yes, this is much better.

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2023-05-16  7:20 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-15 10:53 [PATCH V2] arm64: Disable EL2 traps for BRBE instructions executed in EL1 Anshuman Khandual
2023-05-15 10:53 ` Anshuman Khandual
2023-05-15 13:42 ` Marc Zyngier
2023-05-15 13:42   ` Marc Zyngier
2023-05-16  2:43   ` Anshuman Khandual
2023-05-16  2:43     ` Anshuman Khandual
2023-05-16  7:18     ` Marc Zyngier [this message]
2023-05-16  7:18       ` Marc Zyngier

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