Re: [PATCH 3/3] arm64: dts: rockchip: Add Radxa E52C

From: Marc Zyngier <maz@kernel.org>
To: FUKAUMI Naoki <naoki@radxa.com>
Cc: heiko@sntech.de, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, tglx@linutronix.de, jonas@kwiboo.se,
	macromorgan@hotmail.com, andyshrk@163.com,
	liujianfeng1994@gmail.com, dmt.yashin@gmail.com,
	dsimic@manjaro.org, tim@feathertop.org,
	marcin.juszkiewicz@linaro.org, michael.riesch@wolfvision.net,
	alchark@gmail.com, sebastian.reichel@collabora.com,
	jbx6244@gmail.com, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org
Subject: Re: [PATCH 3/3] arm64: dts: rockchip: Add Radxa E52C
Date: Fri, 27 Dec 2024 10:27:07 +0000	[thread overview]
Message-ID: <86ldw1pgjo.wl-maz@kernel.org> (raw)
In-Reply-To: <5EDFB980DF778743+9f26c8cc-d86d-46ed-9642-cdca10fe7e91@radxa.com>

On Mon, 23 Dec 2024 10:16:04 +0000,
FUKAUMI Naoki <naoki@radxa.com> wrote:
> 
> Hi Marc,
> 
> On 12/23/24 18:39, Marc Zyngier wrote:
> > On Sun, 22 Dec 2024 03:03:55 +0000,
> > FUKAUMI Naoki <naoki@radxa.com> wrote:
> >> 
> >> Radxa E52C is a compact network computer[1] based on the Rockchip
> >> RK3582 SoC:
> >> 
> >> - Dual Cortex-A76 and quad Cortex-A55 CPU
> > 
> > So you have *two* big cores.
> > 
> >> - 5TOPS NPU
> >> - 2GB/4GB/8GB LPDDR4 RAM
> >> - 16GB/32GB/64GB on-board eMMC
> >> - microSD card slot
> >> - USB 3.0 Type-A HOST port
> >> - USB Type-C debug port
> >> - USB Type-C power port (5V only)
> >> - 2x 2.5GbE ports
> >> 
> >> [1] https://radxa.com/products/network-computer/e52c
> >> 
> >> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
> >> ---
> >>   arch/arm64/boot/dts/rockchip/Makefile         |   1 +
> >>   .../boot/dts/rockchip/rk3582-radxa-e52c.dts   | 729 ++++++++++++++++++
> >>   2 files changed, 730 insertions(+)
> >>   create mode 100644 arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts
> > 
> > [...]
> > 
> >> +&cpu_b0 {
> >> +	cpu-supply = <&vdd_cpu_big0_s0>;
> >> +};
> >> +
> >> +&cpu_b1 {
> >> +	cpu-supply = <&vdd_cpu_big0_s0>;
> >> +};
> >> +
> >> +&cpu_b2 {
> >> +	cpu-supply = <&vdd_cpu_big1_s0>;
> >> +};
> >> +
> >> +&cpu_b3 {
> >> +	cpu-supply = <&vdd_cpu_big1_s0>;
> >> +};
> > 
> > And yet you configure 4. If your HW only has 2 A76s, surely something
> > should remove these cores for this platform rather than keep them
> > around.
> 
> One of the four cores may be defective. This information is stored in
> the OTP, so we need to run our software to detect which core is
> defective. Then we disable the cluster that contains the defective
> core.

Is it one? Is it two? If anything, this sort of binning information
should be clearly explained in the cover letter, and a comment placed
in the DTS file to explain that the DT needs to be further processed
by the bootloader to be valid.

	M.

-- 
Without deviation from the norm, progress is not possible.