* [PATCH 01/11] drm/i915/icl: WaDisableImprovedTdlClkGating
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
@ 2018-05-25 22:05 ` Oscar Mateo
2018-05-29 8:51 ` Mika Kuoppala
2018-05-25 22:05 ` [PATCH 02/11] drm/i915/icl: WaEnableStateCacheRedirectToCS Oscar Mateo
` (12 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Oscar Mateo @ 2018-05-25 22:05 UTC (permalink / raw)
To: intel-gfx
Revert to the legacy implementation.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Rebased
- Renamed to Wa_2006611047
- A0 and B0 only
v4:
- Add spaces around '<<' (and fix the surrounding code as well)
- Mark the WA as pre-prod
v5: Rebased on top of the WA refactoring
v6: Added References (Mika)
v7: Fixed in B0
References: HSDES#2006611047
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6953419..4eb159f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8328,8 +8328,9 @@ enum {
#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
-#define DOP_CLOCK_GATING_DISABLE (1<<0)
-#define PUSH_CONSTANT_DEREF_DISABLE (1<<8)
+#define DOP_CLOCK_GATING_DISABLE (1 << 0)
+#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
+#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index cea5710..04aa885 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -463,6 +463,13 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
*/
WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
+ /* Wa_2006611047:icl (pre-prod)
+ * Formerly known as WaDisableImprovedTdlClkGating
+ */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
+ WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 01/11] drm/i915/icl: WaDisableImprovedTdlClkGating
2018-05-25 22:05 ` [PATCH 01/11] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
@ 2018-05-29 8:51 ` Mika Kuoppala
0 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2018-05-29 8:51 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Oscar Mateo <oscar.mateo@intel.com> writes:
> Revert to the legacy implementation.
>
> v2: GEN7_ROW_CHICKEN2 is masked
> v3:
> - Rebased
> - Renamed to Wa_2006611047
> - A0 and B0 only
> v4:
> - Add spaces around '<<' (and fix the surrounding code as well)
> - Mark the WA as pre-prod
> v5: Rebased on top of the WA refactoring
> v6: Added References (Mika)
> v7: Fixed in B0
>
> References: HSDES#2006611047
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6953419..4eb159f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8328,8 +8328,9 @@ enum {
>
> #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
> #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
> -#define DOP_CLOCK_GATING_DISABLE (1<<0)
> -#define PUSH_CONSTANT_DEREF_DISABLE (1<<8)
> +#define DOP_CLOCK_GATING_DISABLE (1 << 0)
> +#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> +#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
>
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index cea5710..04aa885 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -463,6 +463,13 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> */
> WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
>
> + /* Wa_2006611047:icl (pre-prod)
> + * Formerly known as WaDisableImprovedTdlClkGating
> + */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
> + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> + GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
> +
> return 0;
> }
>
> --
> 1.9.1
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 02/11] drm/i915/icl: WaEnableStateCacheRedirectToCS
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
2018-05-25 22:05 ` [PATCH 01/11] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
@ 2018-05-25 22:05 ` Oscar Mateo
2018-05-29 9:15 ` Mika Kuoppala
2018-05-25 22:05 ` [PATCH 03/11] drm/i915/icl: Wa_2006665173 Oscar Mateo
` (11 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Oscar Mateo @ 2018-05-25 22:05 UTC (permalink / raw)
To: intel-gfx
Redirects the state cache to the CS Command buffer section for
performance reasons.
v2: Rebased
v3: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1604325460
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4eb159f..924b9a6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7227,6 +7227,7 @@ enum {
#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
#define GEN7_L3SQCREG1 _MMIO(0xB010)
#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 04aa885..1d29803 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -470,6 +470,10 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+ /* WaEnableStateCacheRedirectToCS:icl */
+ WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+ GEN11_STATE_CACHE_REDIRECT_TO_CS);
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 02/11] drm/i915/icl: WaEnableStateCacheRedirectToCS
2018-05-25 22:05 ` [PATCH 02/11] drm/i915/icl: WaEnableStateCacheRedirectToCS Oscar Mateo
@ 2018-05-29 9:15 ` Mika Kuoppala
0 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2018-05-29 9:15 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Oscar Mateo <oscar.mateo@intel.com> writes:
> Redirects the state cache to the CS Command buffer section for
> performance reasons.
>
> v2: Rebased
> v3: Rebased on top of the WA refactoring
> v3: Added References (Mika)
>
> References: HSDES#1604325460
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4eb159f..924b9a6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7227,6 +7227,7 @@ enum {
> #define DISABLE_PIXEL_MASK_CAMMING (1<<14)
>
> #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> +#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
>
> #define GEN7_L3SQCREG1 _MMIO(0xB010)
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 04aa885..1d29803 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -470,6 +470,10 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
>
> + /* WaEnableStateCacheRedirectToCS:icl */
> + WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
> + GEN11_STATE_CACHE_REDIRECT_TO_CS);
> +
> return 0;
> }
>
> --
> 1.9.1
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 03/11] drm/i915/icl: Wa_2006665173
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
2018-05-25 22:05 ` [PATCH 01/11] drm/i915/icl: WaDisableImprovedTdlClkGating Oscar Mateo
2018-05-25 22:05 ` [PATCH 02/11] drm/i915/icl: WaEnableStateCacheRedirectToCS Oscar Mateo
@ 2018-05-25 22:05 ` Oscar Mateo
2018-05-29 10:37 ` Mika Kuoppala
2018-05-25 22:05 ` [PATCH 04/11] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
` (10 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Oscar Mateo @ 2018-05-25 22:05 UTC (permalink / raw)
To: intel-gfx
Disable blend embellishment in RCC.
Also, some other registers style fixed in passing.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
v4:
- Fixed in B0
- Mentioned style fixes in commit message
References: HSDES#2006665173
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++++-------
drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 924b9a6..6e88c6b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7211,13 +7211,17 @@ enum {
/* GEN7 chicken */
#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
-# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
-# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
-#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
-# define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13)
-# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
-# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
-# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
+ #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
+ #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
+
+#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
+ #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
+ #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
+ #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
+ #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
+
+#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+ #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
#define HIZ_CHICKEN _MMIO(0x7018)
# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 1d29803..33a1a0c 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -474,6 +474,11 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
GEN11_STATE_CACHE_REDIRECT_TO_CS);
+ /* Wa_2006665173:icl (pre-prod) */
+ if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
+ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+ GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 03/11] drm/i915/icl: Wa_2006665173
2018-05-25 22:05 ` [PATCH 03/11] drm/i915/icl: Wa_2006665173 Oscar Mateo
@ 2018-05-29 10:37 ` Mika Kuoppala
0 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2018-05-29 10:37 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Oscar Mateo <oscar.mateo@intel.com> writes:
> Disable blend embellishment in RCC.
>
> Also, some other registers style fixed in passing.
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
> v4:
> - Fixed in B0
> - Mentioned style fixes in commit message
>
> References: HSDES#2006665173
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++++-------
> drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
> 2 files changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 924b9a6..6e88c6b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7211,13 +7211,17 @@ enum {
>
> /* GEN7 chicken */
> #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
> -# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
> -# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
> -#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
> -# define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13)
> -# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
> -# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
> -# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
> + #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26))
> + #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
> +
> +#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
> + #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
> + #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12)
> + #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8)
> + #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0)
> +
> +#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> + #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11)
>
> #define HIZ_CHICKEN _MMIO(0x7018)
> # define CHV_HZ_8X8_MODE_IN_1X (1<<15)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 1d29803..33a1a0c 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -474,6 +474,11 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
> GEN11_STATE_CACHE_REDIRECT_TO_CS);
>
> + /* Wa_2006665173:icl (pre-prod) */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_A0))
> + WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> + GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
> +
> return 0;
> }
>
> --
> 1.9.1
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 04/11] drm/i915/icl: WaEnableFloatBlendOptimization
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
` (2 preceding siblings ...)
2018-05-25 22:05 ` [PATCH 03/11] drm/i915/icl: Wa_2006665173 Oscar Mateo
@ 2018-05-25 22:05 ` Oscar Mateo
2018-05-29 12:07 ` Mika Kuoppala
2018-07-23 12:03 ` Chris Wilson
2018-05-25 22:05 ` [PATCH 05/11] drm/i915/icl: WaSendPushConstantsFromMMIO Oscar Mateo
` (9 subsequent siblings)
13 siblings, 2 replies; 23+ messages in thread
From: Oscar Mateo @ 2018-05-25 22:05 UTC (permalink / raw)
To: intel-gfx
Enables blend optimization for floating point RTs
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1406393558
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6e88c6b..f123c3e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2663,6 +2663,9 @@ enum i915_power_well_id {
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
+#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
+#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
+
#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
#define GEN6_BLITTER_LOCK_SHIFT 16
#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 33a1a0c..e9c00b0 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -479,6 +479,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+ /* WaEnableFloatBlendOptimization:icl */
+ WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
return 0;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 04/11] drm/i915/icl: WaEnableFloatBlendOptimization
2018-05-25 22:05 ` [PATCH 04/11] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
@ 2018-05-29 12:07 ` Mika Kuoppala
2018-05-29 12:47 ` Lionel Landwerlin
2018-07-23 12:03 ` Chris Wilson
1 sibling, 1 reply; 23+ messages in thread
From: Mika Kuoppala @ 2018-05-29 12:07 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Oscar Mateo <oscar.mateo@intel.com> writes:
> Enables blend optimization for floating point RTs
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
>
> References: HSDES#1406393558
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Let's see if we can get away without whitelisting this,
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6e88c6b..f123c3e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2663,6 +2663,9 @@ enum i915_power_well_id {
> #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
> #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
>
> +#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
> +#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
> +
> #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
> #define GEN6_BLITTER_LOCK_SHIFT 16
> #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 33a1a0c..e9c00b0 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -479,6 +479,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
>
> + /* WaEnableFloatBlendOptimization:icl */
> + WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
> +
> return 0;
> }
>
> --
> 1.9.1
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^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 04/11] drm/i915/icl: WaEnableFloatBlendOptimization
2018-05-29 12:07 ` Mika Kuoppala
@ 2018-05-29 12:47 ` Lionel Landwerlin
2018-05-29 19:13 ` Anuj Phogat
0 siblings, 1 reply; 23+ messages in thread
From: Lionel Landwerlin @ 2018-05-29 12:47 UTC (permalink / raw)
To: Mika Kuoppala, Oscar Mateo, intel-gfx; +Cc: Chery, Nanley G
FYI, we're setting this in Mesa :
https://cgit.freedesktop.org/mesa/mesa/tree/src/intel/vulkan/genX_state.c#n130
https://cgit.freedesktop.org/mesa/mesa/tree/src/mesa/drivers/dri/i965/brw_state_upload.c#n67
I don't think we realized this was a privileged register.
Anuj: Maybe we can drop it?
-
Lionel
On 29/05/18 13:07, Mika Kuoppala wrote:
> Oscar Mateo <oscar.mateo@intel.com> writes:
>
>> Enables blend optimization for floating point RTs
>>
>> v2: Rebased on top of the WA refactoring
>> v3: Added References (Mika)
>>
>> References: HSDES#1406393558
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Let's see if we can get away without whitelisting this,
> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
>> 2 files changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 6e88c6b..f123c3e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2663,6 +2663,9 @@ enum i915_power_well_id {
>> #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
>> #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
>>
>> +#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
>> +#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
>> +
>> #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
>> #define GEN6_BLITTER_LOCK_SHIFT 16
>> #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
>> index 33a1a0c..e9c00b0 100644
>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>> @@ -479,6 +479,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>> WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>> GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
>>
>> + /* WaEnableFloatBlendOptimization:icl */
>> + WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
>> +
>> return 0;
>> }
>>
>> --
>> 1.9.1
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH 04/11] drm/i915/icl: WaEnableFloatBlendOptimization
2018-05-29 12:47 ` Lionel Landwerlin
@ 2018-05-29 19:13 ` Anuj Phogat
0 siblings, 0 replies; 23+ messages in thread
From: Anuj Phogat @ 2018-05-29 19:13 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: Intel GFX, Chery, Nanley G
On Tue, May 29, 2018 at 5:47 AM, Lionel Landwerlin
<lionel.g.landwerlin@intel.com> wrote:
> FYI, we're setting this in Mesa :
> https://cgit.freedesktop.org/mesa/mesa/tree/src/intel/vulkan/genX_state.c#n130
> https://cgit.freedesktop.org/mesa/mesa/tree/src/mesa/drivers/dri/i965/brw_state_upload.c#n67
> I don't think we realized this was a privileged register.
>
No, I didn't.
> Anuj: Maybe we can drop it?
>
Yes, I'll send out patches to remove it from Mesa.
> -
> Lionel
>
>
> On 29/05/18 13:07, Mika Kuoppala wrote:
>>
>> Oscar Mateo <oscar.mateo@intel.com> writes:
>>
>>> Enables blend optimization for floating point RTs
>>>
>>> v2: Rebased on top of the WA refactoring
>>> v3: Added References (Mika)
>>>
>>> References: HSDES#1406393558
>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>>
>> Let's see if we can get away without whitelisting this,
>> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>
>>> ---
>>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>>> drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
>>> 2 files changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> b/drivers/gpu/drm/i915/i915_reg.h
>>> index 6e88c6b..f123c3e 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -2663,6 +2663,9 @@ enum i915_power_well_id {
>>> #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
>>> #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
>>> +#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
>>> +#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
>>> +
>>> #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
>>> #define GEN6_BLITTER_LOCK_SHIFT 16
>>> #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
>>> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
>>> b/drivers/gpu/drm/i915/intel_workarounds.c
>>> index 33a1a0c..e9c00b0 100644
>>> --- a/drivers/gpu/drm/i915/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
>>> @@ -479,6 +479,9 @@ static int icl_ctx_workarounds_init(struct
>>> drm_i915_private *dev_priv)
>>> WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>>> GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
>>> + /* WaEnableFloatBlendOptimization:icl */
>>> + WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS,
>>> FLOAT_BLEND_OPTIMIZATION_ENABLE);
>>> +
>>> return 0;
>>> }
>>>
>>> --
>>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 04/11] drm/i915/icl: WaEnableFloatBlendOptimization
2018-05-25 22:05 ` [PATCH 04/11] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
2018-05-29 12:07 ` Mika Kuoppala
@ 2018-07-23 12:03 ` Chris Wilson
1 sibling, 0 replies; 23+ messages in thread
From: Chris Wilson @ 2018-07-23 12:03 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Quoting Oscar Mateo (2018-05-25 23:05:32)
> Enables blend optimization for floating point RTs
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
>
> References: HSDES#1406393558
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6e88c6b..f123c3e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2663,6 +2663,9 @@ enum i915_power_well_id {
> #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
> #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
>
> +#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
> +#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
> +
> #define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
> #define GEN6_BLITTER_LOCK_SHIFT 16
> #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 33a1a0c..e9c00b0 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -479,6 +479,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
>
> + /* WaEnableFloatBlendOptimization:icl */
> + WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
This is not sticking according to
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4527/fi-icl-u/igt@gem_workarounds@basic-read.html
(gem_workarounds:3598) DEBUG: Address val mask read result
(gem_workarounds:3598) WARNING: 0x0E420 0x00100010 0x00000010 0x00000000 FAIL
-Chris
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 05/11] drm/i915/icl: WaSendPushConstantsFromMMIO
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
` (3 preceding siblings ...)
2018-05-25 22:05 ` [PATCH 04/11] drm/i915/icl: WaEnableFloatBlendOptimization Oscar Mateo
@ 2018-05-25 22:05 ` Oscar Mateo
2018-05-25 22:05 ` [PATCH 06/11] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Oscar Mateo
` (8 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Oscar Mateo @ 2018-05-25 22:05 UTC (permalink / raw)
To: intel-gfx
Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...
v2: Rebased
v3: Rebased on top of the WA refactoring
v4: Rebased on top of the WA whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1405764967
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index e9c00b0..804de04 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -963,6 +963,8 @@ static void cnl_whitelist_build(struct whitelist *w)
static void icl_whitelist_build(struct whitelist *w)
{
+ /* WaSendPushConstantsFromMMIO:icl */
+ whitelist_reg(w, COMMON_SLICE_CHICKEN2);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 06/11] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
` (4 preceding siblings ...)
2018-05-25 22:05 ` [PATCH 05/11] drm/i915/icl: WaSendPushConstantsFromMMIO Oscar Mateo
@ 2018-05-25 22:05 ` Oscar Mateo
2018-05-25 22:05 ` [PATCH 07/11] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Oscar Mateo
` (7 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Oscar Mateo @ 2018-05-25 22:05 UTC (permalink / raw)
To: intel-gfx
Required to dinamically set 'Small PL Lossless Fix Enable'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1804860039
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 804de04..e173e17 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -965,6 +965,9 @@ static void icl_whitelist_build(struct whitelist *w)
{
/* WaSendPushConstantsFromMMIO:icl */
whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+ /* WaAllowUMDToModifyHalfSliceChicken2:icl */
+ whitelist_reg(w, HALF_SLICE_CHICKEN2);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 07/11] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
` (5 preceding siblings ...)
2018-05-25 22:05 ` [PATCH 06/11] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2 Oscar Mateo
@ 2018-05-25 22:05 ` Oscar Mateo
2018-05-25 22:05 ` [PATCH 08/11] drm/i915/icl: WaAllowUmdWriteTRTTRootTable Oscar Mateo
` (6 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Oscar Mateo @ 2018-05-25 22:05 UTC (permalink / raw)
To: intel-gfx
Required to dinamically set 'Trilinear Filter Quality Mode'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of the whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1804860157
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index e173e17..cce3e3f 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -968,6 +968,9 @@ static void icl_whitelist_build(struct whitelist *w)
/* WaAllowUMDToModifyHalfSliceChicken2:icl */
whitelist_reg(w, HALF_SLICE_CHICKEN2);
+
+ /* WaAllowUMDToModifyHalfSliceChicken7:icl */
+ whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 08/11] drm/i915/icl: WaAllowUmdWriteTRTTRootTable
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
` (6 preceding siblings ...)
2018-05-25 22:05 ` [PATCH 07/11] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 Oscar Mateo
@ 2018-05-25 22:05 ` Oscar Mateo
2018-05-25 22:05 ` [PATCH 09/11] drm/i915/icl: WaAllowUMDToModifySamplerMode Oscar Mateo
` (5 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Oscar Mateo @ 2018-05-25 22:05 UTC (permalink / raw)
To: intel-gfx
Required for TR-TT (Tiled Resource Translation Table) support.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f123c3e..1fb86bd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8299,6 +8299,9 @@ enum {
#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
+#define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
+#define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index cce3e3f..9d6b550 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -971,6 +971,10 @@ static void icl_whitelist_build(struct whitelist *w)
/* WaAllowUMDToModifyHalfSliceChicken7:icl */
whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+
+ /* WaAllowUmdWriteTRTTRootTable:icl */
+ whitelist_reg(w, TR_VA_TTL3_PTR_DW0);
+ whitelist_reg(w, TR_VA_TTL3_PTR_DW1);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 09/11] drm/i915/icl: WaAllowUMDToModifySamplerMode
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
` (7 preceding siblings ...)
2018-05-25 22:05 ` [PATCH 08/11] drm/i915/icl: WaAllowUmdWriteTRTTRootTable Oscar Mateo
@ 2018-05-25 22:05 ` Oscar Mateo
2018-05-25 22:05 ` [PATCH 10/11] drm/i915/icl: WaEnablePreemptionGranularityControlByUMD Oscar Mateo
` (4 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Oscar Mateo @ 2018-05-25 22:05 UTC (permalink / raw)
To: intel-gfx
Required for Bindless samplers.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: Rebased on top of the WA refactoring (Michel)
v3: Added References (Mika)
References: HSDES#1404695891
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1fb86bd..42835d79 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8302,6 +8302,8 @@ enum {
#define TR_VA_TTL3_PTR_DW0 _MMIO(0x4DE0)
#define TR_VA_TTL3_PTR_DW1 _MMIO(0x4DE4)
+#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 9d6b550..912f8b5 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -975,6 +975,9 @@ static void icl_whitelist_build(struct whitelist *w)
/* WaAllowUmdWriteTRTTRootTable:icl */
whitelist_reg(w, TR_VA_TTL3_PTR_DW0);
whitelist_reg(w, TR_VA_TTL3_PTR_DW1);
+
+ /* WaAllowUMDToModifySamplerMode:icl */
+ whitelist_reg(w, GEN10_SAMPLER_MODE);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 10/11] drm/i915/icl: WaEnablePreemptionGranularityControlByUMD
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
` (8 preceding siblings ...)
2018-05-25 22:05 ` [PATCH 09/11] drm/i915/icl: WaAllowUMDToModifySamplerMode Oscar Mateo
@ 2018-05-25 22:05 ` Oscar Mateo
2018-05-25 22:05 ` [PATCH 11/11] drm/i915/icl: Wa_1406463099 Oscar Mateo
` (3 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Oscar Mateo @ 2018-05-25 22:05 UTC (permalink / raw)
To: intel-gfx
Apparently HW did not whitelist this register properly.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
References: HSDES#1305642430
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 912f8b5..474e498 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -978,6 +978,9 @@ static void icl_whitelist_build(struct whitelist *w)
/* WaAllowUMDToModifySamplerMode:icl */
whitelist_reg(w, GEN10_SAMPLER_MODE);
+
+ /* WaEnablePreemptionGranularityControlByUMD:icl */
+ whitelist_reg(w, GEN8_CS_CHICKEN1);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 11/11] drm/i915/icl: Wa_1406463099
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
` (9 preceding siblings ...)
2018-05-25 22:05 ` [PATCH 10/11] drm/i915/icl: WaEnablePreemptionGranularityControlByUMD Oscar Mateo
@ 2018-05-25 22:05 ` Oscar Mateo
2018-05-29 12:40 ` Mika Kuoppala
2018-05-25 22:57 ` ✓ Fi.CI.BAT: success for Workarounds for Icelake (rev4) Patchwork
` (2 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Oscar Mateo @ 2018-05-25 22:05 UTC (permalink / raw)
To: intel-gfx
Prevents an error in the GAM unit. Also known as WaGamTlbPendError
References: HSDES#1406463099
References: HSDES#1406465643
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 42835d79..8a18447 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2306,8 +2306,9 @@ enum i915_power_well_id {
#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
-#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
-#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
+#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
+#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
+#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
#if 0
#define PRB0_TAIL _MMIO(0x2030)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 474e498..77929df 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -859,6 +859,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
PMFLUSHDONE_LNICRSDROP |
PMFLUSH_GAPL3UNBLOCK |
PMFLUSHDONE_LNEBLK);
+
+ /* Wa_1406463099:icl
+ * Formerly known as WaGamTlbPendError
+ */
+ I915_WRITE(GAMT_CHKN_BIT_REG,
+ I915_READ(GAMT_CHKN_BIT_REG) |
+ GAMT_CHKN_DISABLE_L3_COH_PIPE);
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 11/11] drm/i915/icl: Wa_1406463099
2018-05-25 22:05 ` [PATCH 11/11] drm/i915/icl: Wa_1406463099 Oscar Mateo
@ 2018-05-29 12:40 ` Mika Kuoppala
0 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2018-05-29 12:40 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Oscar Mateo <oscar.mateo@intel.com> writes:
> Prevents an error in the GAM unit. Also known as WaGamTlbPendError
>
> References: HSDES#1406463099
> References: HSDES#1406465643
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 42835d79..8a18447 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2306,8 +2306,9 @@ enum i915_power_well_id {
> #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
>
> #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
> -#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
> -#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
> +#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31)
> +#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28)
> +#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24)
>
> #if 0
> #define PRB0_TAIL _MMIO(0x2030)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 474e498..77929df 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -859,6 +859,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> PMFLUSHDONE_LNICRSDROP |
> PMFLUSH_GAPL3UNBLOCK |
> PMFLUSHDONE_LNEBLK);
> +
> + /* Wa_1406463099:icl
> + * Formerly known as WaGamTlbPendError
> + */
> + I915_WRITE(GAMT_CHKN_BIT_REG,
> + I915_READ(GAMT_CHKN_BIT_REG) |
> + GAMT_CHKN_DISABLE_L3_COH_PIPE);
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✓ Fi.CI.BAT: success for Workarounds for Icelake (rev4)
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
` (10 preceding siblings ...)
2018-05-25 22:05 ` [PATCH 11/11] drm/i915/icl: Wa_1406463099 Oscar Mateo
@ 2018-05-25 22:57 ` Patchwork
2018-05-26 9:37 ` ✓ Fi.CI.IGT: " Patchwork
2018-05-29 13:03 ` [PATCH v4 00/11] Workarounds for Icelake Mika Kuoppala
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2018-05-25 22:57 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: Workarounds for Icelake (rev4)
URL : https://patchwork.freedesktop.org/series/42055/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4246 -> Patchwork_9131 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42055/revisions/4/mbox/
== Known issues ==
Here are the changes found in Patchwork_9131 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_suspend@basic-s4-devices:
fi-cfl-s3: PASS -> DMESG-WARN (fdo#104056)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951)
fdo#104056 https://bugs.freedesktop.org/show_bug.cgi?id=104056
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
== Participating hosts (44 -> 39) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4246 -> Patchwork_9131
CI_DRM_4246: 5195e857106a3836274e612b26d9d7c6289d8874 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4499: f560ae5a464331f03f0a669ed46b8c9e56526187 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9131: 2eb0165a562e751ffc7ea1005b6b8d0ad5680476 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2eb0165a562e drm/i915/icl: Wa_1406463099
3ef3f3bfbd0c drm/i915/icl: WaEnablePreemptionGranularityControlByUMD
470da3adf07f drm/i915/icl: WaAllowUMDToModifySamplerMode
8145c9ad6df6 drm/i915/icl: WaAllowUmdWriteTRTTRootTable
ee230c83ae4f drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
2c075b6f07a4 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
417bfa1c01d2 drm/i915/icl: WaSendPushConstantsFromMMIO
fab7171add4b drm/i915/icl: WaEnableFloatBlendOptimization
2727cb155b10 drm/i915/icl: Wa_2006665173
8cef56bcdc8c drm/i915/icl: WaEnableStateCacheRedirectToCS
61a5eb6c1851 drm/i915/icl: WaDisableImprovedTdlClkGating
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9131/issues.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* ✓ Fi.CI.IGT: success for Workarounds for Icelake (rev4)
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
` (11 preceding siblings ...)
2018-05-25 22:57 ` ✓ Fi.CI.BAT: success for Workarounds for Icelake (rev4) Patchwork
@ 2018-05-26 9:37 ` Patchwork
2018-05-29 13:03 ` [PATCH v4 00/11] Workarounds for Icelake Mika Kuoppala
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2018-05-26 9:37 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: Workarounds for Icelake (rev4)
URL : https://patchwork.freedesktop.org/series/42055/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4246_full -> Patchwork_9131_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9131_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9131_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42055/revisions/4/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9131_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-blt:
shard-kbl: SKIP -> PASS +1
igt@gem_mocs_settings@mocs-rc6-ctx-dirty-render:
shard-kbl: PASS -> SKIP
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
shard-snb: PASS -> SKIP +1
== Known issues ==
Here are the changes found in Patchwork_9131_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_gtt:
shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#103359)
igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
shard-glk: PASS -> FAIL (fdo#105703)
igt@kms_flip@2x-plain-flip-fb-recreate:
shard-hsw: PASS -> FAIL (fdo#103928)
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#102887, fdo#105363)
igt@kms_flip@plain-flip-fb-recreate-interruptible:
shard-glk: PASS -> FAIL (fdo#100368) +1
igt@kms_flip_tiling@flip-x-tiled:
shard-glk: PASS -> FAIL (fdo#104724)
igt@kms_flip_tiling@flip-y-tiled:
shard-glk: PASS -> FAIL (fdo#103822, fdo#104724)
==== Possible fixes ====
igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
shard-glk: FAIL (fdo#105703) -> PASS
igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
shard-glk: FAIL (fdo#105454, fdo#106509) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4246 -> Patchwork_9131
CI_DRM_4246: 5195e857106a3836274e612b26d9d7c6289d8874 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4499: f560ae5a464331f03f0a669ed46b8c9e56526187 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9131: 2eb0165a562e751ffc7ea1005b6b8d0ad5680476 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9131/shards.html
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^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v4 00/11] Workarounds for Icelake
2018-05-25 22:05 [PATCH v4 00/11] Workarounds for Icelake Oscar Mateo
` (12 preceding siblings ...)
2018-05-26 9:37 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-05-29 13:03 ` Mika Kuoppala
13 siblings, 0 replies; 23+ messages in thread
From: Mika Kuoppala @ 2018-05-29 13:03 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Oscar Mateo <oscar.mateo@intel.com> writes:
> The remaining WA patches that haven't been merged to date, plus
> two new ones (WaEnablePreemptionGranularityControlByUMD &
> Wa_1406463099).
>
> Oscar Mateo (11):
> drm/i915/icl: WaDisableImprovedTdlClkGating
> drm/i915/icl: WaEnableStateCacheRedirectToCS
> drm/i915/icl: Wa_2006665173
> drm/i915/icl: WaEnableFloatBlendOptimization
Reviewed and pushed all the above and the
last one in this series. Thanks for patches!
For the whitelisting stuff, I think we need
to involve mesa/virtualization folks to see
if there is really a need.
-Mika
> drm/i915/icl: WaSendPushConstantsFromMMIO
> drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
> drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
> drm/i915/icl: WaAllowUmdWriteTRTTRootTable
> drm/i915/icl: WaAllowUMDToModifySamplerMode
> drm/i915/icl: WaEnablePreemptionGranularityControlByUMD
> drm/i915/icl: Wa_1406463099
>
> drivers/gpu/drm/i915/i915_reg.h | 37 +++++++++++++++++++--------
> drivers/gpu/drm/i915/intel_workarounds.c | 44 ++++++++++++++++++++++++++++++++
> 2 files changed, 70 insertions(+), 11 deletions(-)
>
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 23+ messages in thread