* Re: why "mov %0, %0" after "rd %%tick, %0"?
@ 2004-01-23 20:58 David S. Miller
2004-01-23 20:59 ` Ed L Cashin
2004-01-23 21:31 ` Ed L Cashin
0 siblings, 2 replies; 3+ messages in thread
From: David S. Miller @ 2004-01-23 20:58 UTC (permalink / raw)
To: sparclinux
On Fri, 23 Jan 2004 15:59:13 -0500
Ed L Cashin <ecashin@uga.edu> wrote:
> One thing I don't get is why there's a mov %0, %0 instruction after
> reading the tick register. Is this because of the delay slot?
No, there is a bug in some of the UltraSPARC processors in that if
you go:
rd %tick, %reg
cmp %reg, XXX
the compare will get an incorrect result. If we force the %tick result
into a simple move instruction this prevents the sequence that leads up
to the bug.
^ permalink raw reply [flat|nested] 3+ messages in thread
* why "mov %0, %0" after "rd %%tick, %0"?
2004-01-23 20:58 why "mov %0, %0" after "rd %%tick, %0"? David S. Miller
@ 2004-01-23 20:59 ` Ed L Cashin
2004-01-23 21:31 ` Ed L Cashin
1 sibling, 0 replies; 3+ messages in thread
From: Ed L Cashin @ 2004-01-23 20:59 UTC (permalink / raw)
To: sparclinux
Hi. In arch/sparc64/kernel/time.c, there are some routines that use
the %tick register. It seems analogous to the Pentium's TSC. I'm
planning to use that register in userland via inline asm. (Thanks for
making sure that non-privileged access is allowed, BTW!)
One thing I don't get is why there's a mov %0, %0 instruction after
reading the tick register. Is this because of the delay slot?
static unsigned long tick_get_tick(void)
{
unsigned long ret;
__asm__ __volatile__("rd %%tick, %0\n\t"
"mov %0, %0"
: "=r" (ret));
return ret & ~TICK_PRIV_BIT;
}
--
--Ed L Cashin | PGP public key:
ecashin@uga.edu | http://noserose.net/e/pgp/
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: why "mov %0, %0" after "rd %%tick, %0"?
2004-01-23 20:58 why "mov %0, %0" after "rd %%tick, %0"? David S. Miller
2004-01-23 20:59 ` Ed L Cashin
@ 2004-01-23 21:31 ` Ed L Cashin
1 sibling, 0 replies; 3+ messages in thread
From: Ed L Cashin @ 2004-01-23 21:31 UTC (permalink / raw)
To: sparclinux
"David S. Miller" <davem@redhat.com> writes:
> On Fri, 23 Jan 2004 15:59:13 -0500
> Ed L Cashin <ecashin@uga.edu> wrote:
>
>> One thing I don't get is why there's a mov %0, %0 instruction after
>> reading the tick register. Is this because of the delay slot?
>
> No, there is a bug in some of the UltraSPARC processors in that if
> you go:
>
> rd %tick, %reg
> cmp %reg, XXX
>
> the compare will get an incorrect result. If we force the %tick result
> into a simple move instruction this prevents the sequence that leads up
> to the bug.
Oh! Thanks. Do you think it's worth a comment?
--- linux-2.6.1/arch/sparc64/kernel/time.c.orig Fri Jan 23 16:21:38 2004
+++ linux-2.6.1/arch/sparc64/kernel/time.c Fri Jan 23 16:24:44 2004
@@ -108,6 +108,14 @@
{
unsigned long ret;
+ /* There is a bug in some of the UltraSPARC processors
+ * where a compare following a read of the %tick
+ * register gets an incorrect result.
+ *
+ * If we force the %tick result into a simple move
+ * instruction this prevents the sequence that leads up
+ * to the bug.
+ */
__asm__ __volatile__("rd %%tick, %0\n\t"
"mov %0, %0"
: "=r" (ret));
--
--Ed L Cashin | PGP public key:
ecashin@uga.edu | http://noserose.net/e/pgp/
^ permalink raw reply [flat|nested] 3+ messages in thread
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2004-01-23 20:58 why "mov %0, %0" after "rd %%tick, %0"? David S. Miller
2004-01-23 20:59 ` Ed L Cashin
2004-01-23 21:31 ` Ed L Cashin
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