* [PATCH 1/3] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m'
2025-01-12 22:56 [PATCH 0/3] hw/arm/v7m: Remove Cortex-M &first_cpu uses Philippe Mathieu-Daudé
@ 2025-01-12 22:56 ` Philippe Mathieu-Daudé
2025-01-12 23:39 ` Alistair Francis
2025-01-12 22:56 ` [PATCH 2/3] hw/arm/stellaris: Add 'armv7m' local variable Philippe Mathieu-Daudé
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-12 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: Samuel Tardieu, qemu-arm, Peter Maydell, Felipe Balbi,
Subbaraya Sundeep, Alistair Francis, Joel Stanley,
Alexandre Iooss, Philippe Mathieu-Daudé
The ARMv7MState object is not simply a CPU, it also
contains the NVIC, SysTick timer, and various MemoryRegions.
Rename the field as 'armv7m', like other Cortex-M boards.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/arm/nrf51_soc.h | 2 +-
hw/arm/nrf51_soc.c | 18 +++++++++---------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
index e52a56e75e0..f88ab1b7d3e 100644
--- a/include/hw/arm/nrf51_soc.h
+++ b/include/hw/arm/nrf51_soc.h
@@ -30,7 +30,7 @@ struct NRF51State {
SysBusDevice parent_obj;
/*< public >*/
- ARMv7MState cpu;
+ ARMv7MState armv7m;
NRF51UARTState uart;
NRF51RNGState rng;
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index 37dd4cf5f40..dee06ab5654 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -76,16 +76,16 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
}
/* This clock doesn't need migration because it is fixed-frequency */
clock_set_hz(s->sysclk, HCLK_FRQ);
- qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk);
+ qdev_connect_clock_in(DEVICE(&s->armv7m), "cpuclk", s->sysclk);
/*
* This SoC has no systick device, so don't connect refclk.
* TODO: model the lack of systick (currently the armv7m object
* will always provide one).
*/
- object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
+ object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(&s->container),
&error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
return;
}
@@ -104,7 +104,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
- qdev_get_gpio_in(DEVICE(&s->cpu),
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
BASE_TO_IRQ(NRF51_UART_BASE)));
/* RNG */
@@ -115,7 +115,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
- qdev_get_gpio_in(DEVICE(&s->cpu),
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
BASE_TO_IRQ(NRF51_RNG_BASE)));
/* UICR, FICR, NVMC, FLASH */
@@ -161,7 +161,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->cpu),
+ qdev_get_gpio_in(DEVICE(&s->armv7m),
BASE_TO_IRQ(base_addr)));
}
@@ -185,10 +185,10 @@ static void nrf51_soc_init(Object *obj)
memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
- object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
- qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
+ object_initialize_child(OBJECT(s), "armv6m", &s->armv7m, TYPE_ARMV7M);
+ qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type",
ARM_CPU_TYPE_NAME("cortex-m0"));
- qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
+ qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", 32);
object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
--
2.47.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 1/3] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m'
2025-01-12 22:56 ` [PATCH 1/3] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m' Philippe Mathieu-Daudé
@ 2025-01-12 23:39 ` Alistair Francis
0 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2025-01-12 23:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Samuel Tardieu, qemu-arm, Peter Maydell, Felipe Balbi,
Subbaraya Sundeep, Alistair Francis, Joel Stanley,
Alexandre Iooss
On Mon, Jan 13, 2025 at 8:57 AM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> The ARMv7MState object is not simply a CPU, it also
> contains the NVIC, SysTick timer, and various MemoryRegions.
>
> Rename the field as 'armv7m', like other Cortex-M boards.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/arm/nrf51_soc.h | 2 +-
> hw/arm/nrf51_soc.c | 18 +++++++++---------
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
> index e52a56e75e0..f88ab1b7d3e 100644
> --- a/include/hw/arm/nrf51_soc.h
> +++ b/include/hw/arm/nrf51_soc.h
> @@ -30,7 +30,7 @@ struct NRF51State {
> SysBusDevice parent_obj;
>
> /*< public >*/
> - ARMv7MState cpu;
> + ARMv7MState armv7m;
>
> NRF51UARTState uart;
> NRF51RNGState rng;
> diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
> index 37dd4cf5f40..dee06ab5654 100644
> --- a/hw/arm/nrf51_soc.c
> +++ b/hw/arm/nrf51_soc.c
> @@ -76,16 +76,16 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
> }
> /* This clock doesn't need migration because it is fixed-frequency */
> clock_set_hz(s->sysclk, HCLK_FRQ);
> - qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk);
> + qdev_connect_clock_in(DEVICE(&s->armv7m), "cpuclk", s->sysclk);
> /*
> * This SoC has no systick device, so don't connect refclk.
> * TODO: model the lack of systick (currently the armv7m object
> * will always provide one).
> */
>
> - object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
> + object_property_set_link(OBJECT(&s->armv7m), "memory", OBJECT(&s->container),
> &error_abort);
> - if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> return;
> }
>
> @@ -104,7 +104,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
> mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
> memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
> - qdev_get_gpio_in(DEVICE(&s->cpu),
> + qdev_get_gpio_in(DEVICE(&s->armv7m),
> BASE_TO_IRQ(NRF51_UART_BASE)));
>
> /* RNG */
> @@ -115,7 +115,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
> mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
> memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
> - qdev_get_gpio_in(DEVICE(&s->cpu),
> + qdev_get_gpio_in(DEVICE(&s->armv7m),
> BASE_TO_IRQ(NRF51_RNG_BASE)));
>
> /* UICR, FICR, NVMC, FLASH */
> @@ -161,7 +161,7 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
>
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
> - qdev_get_gpio_in(DEVICE(&s->cpu),
> + qdev_get_gpio_in(DEVICE(&s->armv7m),
> BASE_TO_IRQ(base_addr)));
> }
>
> @@ -185,10 +185,10 @@ static void nrf51_soc_init(Object *obj)
>
> memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
>
> - object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M);
> - qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
> + object_initialize_child(OBJECT(s), "armv6m", &s->armv7m, TYPE_ARMV7M);
> + qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type",
> ARM_CPU_TYPE_NAME("cortex-m0"));
> - qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
> + qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", 32);
>
> object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART);
> object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev");
> --
> 2.47.1
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] hw/arm/stellaris: Add 'armv7m' local variable
2025-01-12 22:56 [PATCH 0/3] hw/arm/v7m: Remove Cortex-M &first_cpu uses Philippe Mathieu-Daudé
2025-01-12 22:56 ` [PATCH 1/3] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m' Philippe Mathieu-Daudé
@ 2025-01-12 22:56 ` Philippe Mathieu-Daudé
2025-01-12 22:58 ` Philippe Mathieu-Daudé
2025-01-12 23:42 ` Alistair Francis
2025-01-12 22:56 ` [PATCH 3/3] hw/arm/v7m: Remove use of &first_cpu in machine_init() Philippe Mathieu-Daudé
2025-01-27 12:58 ` [PATCH 0/3] hw/arm/v7m: Remove Cortex-M &first_cpu uses Peter Maydell
3 siblings, 2 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-12 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: Samuel Tardieu, qemu-arm, Peter Maydell, Felipe Balbi,
Subbaraya Sundeep, Alistair Francis, Joel Stanley,
Alexandre Iooss, Philippe Mathieu-Daudé
While the TYPE_ARMV7M object forward its NVIC interrupt lines,
it is somehow misleading to name it 'nvic'. Add the 'armv7m'
local variable for clarity, but also keep the 'nvic' variable
behaving like before when used for wiring IRQ lines.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/stellaris.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 1bba96df14e..7303e096ef7 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1031,7 +1031,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
*/
Object *soc_container;
- DeviceState *gpio_dev[7], *nvic;
+ DeviceState *gpio_dev[7], *armv7m, *nvic;
qemu_irq gpio_in[7][8];
qemu_irq gpio_out[7][8];
qemu_irq adc;
@@ -1095,19 +1095,20 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4);
sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
- nvic = qdev_new(TYPE_ARMV7M);
- object_property_add_child(soc_container, "v7m", OBJECT(nvic));
- qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
- qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
- qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
- qdev_prop_set_bit(nvic, "enable-bitband", true);
- qdev_connect_clock_in(nvic, "cpuclk",
+ armv7m = qdev_new(TYPE_ARMV7M);
+ object_property_add_child(soc_container, "v7m", OBJECT(armv7m));
+ qdev_prop_set_uint32(armv7m, "num-irq", NUM_IRQ_LINES);
+ qdev_prop_set_uint8(armv7m, "num-prio-bits", NUM_PRIO_BITS);
+ qdev_prop_set_string(armv7m, "cpu-type", ms->cpu_type);
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
+ qdev_connect_clock_in(armv7m, "cpuclk",
qdev_get_clock_out(ssys_dev, "SYSCLK"));
/* This SoC does not connect the systick reference clock */
- object_property_set_link(OBJECT(nvic), "memory",
+ object_property_set_link(OBJECT(armv7m), "memory",
OBJECT(get_system_memory()), &error_abort);
/* This will exit with an error if the user passed us a bad cpu_type */
- sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(armv7m), &error_fatal);
+ nvic = armv7m;
/* Now we can wire up the IRQ and MMIO of the system registers */
sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
--
2.47.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 2/3] hw/arm/stellaris: Add 'armv7m' local variable
2025-01-12 22:56 ` [PATCH 2/3] hw/arm/stellaris: Add 'armv7m' local variable Philippe Mathieu-Daudé
@ 2025-01-12 22:58 ` Philippe Mathieu-Daudé
2025-01-12 23:42 ` Alistair Francis
1 sibling, 0 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-12 22:58 UTC (permalink / raw)
To: qemu-devel
Cc: Samuel Tardieu, qemu-arm, Peter Maydell, Felipe Balbi,
Subbaraya Sundeep, Alistair Francis, Joel Stanley,
Alexandre Iooss
On 12/1/25 23:56, Philippe Mathieu-Daudé wrote:
> While the TYPE_ARMV7M object forward its NVIC interrupt lines,
> it is somehow misleading to name it 'nvic'. Add the 'armv7m'
> local variable for clarity, but also keep the 'nvic' variable
> behaving like before when used for wiring IRQ lines.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/stellaris.c | 21 +++++++++++----------
> 1 file changed, 11 insertions(+), 10 deletions(-)
Note this patch diverges with my other Stellaris series:
https://lore.kernel.org/qemu-devel/20250110160204.74997-1-philmd@linaro.org/
I'm OK to rebase whichever isn't merged first (this one
being less work).
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] hw/arm/stellaris: Add 'armv7m' local variable
2025-01-12 22:56 ` [PATCH 2/3] hw/arm/stellaris: Add 'armv7m' local variable Philippe Mathieu-Daudé
2025-01-12 22:58 ` Philippe Mathieu-Daudé
@ 2025-01-12 23:42 ` Alistair Francis
1 sibling, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2025-01-12 23:42 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Samuel Tardieu, qemu-arm, Peter Maydell, Felipe Balbi,
Subbaraya Sundeep, Alistair Francis, Joel Stanley,
Alexandre Iooss
On Mon, Jan 13, 2025 at 8:57 AM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> While the TYPE_ARMV7M object forward its NVIC interrupt lines,
> it is somehow misleading to name it 'nvic'. Add the 'armv7m'
> local variable for clarity, but also keep the 'nvic' variable
> behaving like before when used for wiring IRQ lines.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/arm/stellaris.c | 21 +++++++++++----------
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index 1bba96df14e..7303e096ef7 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -1031,7 +1031,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
> */
>
> Object *soc_container;
> - DeviceState *gpio_dev[7], *nvic;
> + DeviceState *gpio_dev[7], *armv7m, *nvic;
> qemu_irq gpio_in[7][8];
> qemu_irq gpio_out[7][8];
> qemu_irq adc;
> @@ -1095,19 +1095,20 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
> qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
>
> - nvic = qdev_new(TYPE_ARMV7M);
> - object_property_add_child(soc_container, "v7m", OBJECT(nvic));
> - qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
> - qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
> - qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
> - qdev_prop_set_bit(nvic, "enable-bitband", true);
> - qdev_connect_clock_in(nvic, "cpuclk",
> + armv7m = qdev_new(TYPE_ARMV7M);
> + object_property_add_child(soc_container, "v7m", OBJECT(armv7m));
> + qdev_prop_set_uint32(armv7m, "num-irq", NUM_IRQ_LINES);
> + qdev_prop_set_uint8(armv7m, "num-prio-bits", NUM_PRIO_BITS);
> + qdev_prop_set_string(armv7m, "cpu-type", ms->cpu_type);
> + qdev_prop_set_bit(armv7m, "enable-bitband", true);
> + qdev_connect_clock_in(armv7m, "cpuclk",
> qdev_get_clock_out(ssys_dev, "SYSCLK"));
> /* This SoC does not connect the systick reference clock */
> - object_property_set_link(OBJECT(nvic), "memory",
> + object_property_set_link(OBJECT(armv7m), "memory",
> OBJECT(get_system_memory()), &error_abort);
> /* This will exit with an error if the user passed us a bad cpu_type */
> - sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
> + sysbus_realize_and_unref(SYS_BUS_DEVICE(armv7m), &error_fatal);
> + nvic = armv7m;
>
> /* Now we can wire up the IRQ and MMIO of the system registers */
> sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
> --
> 2.47.1
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] hw/arm/v7m: Remove use of &first_cpu in machine_init()
2025-01-12 22:56 [PATCH 0/3] hw/arm/v7m: Remove Cortex-M &first_cpu uses Philippe Mathieu-Daudé
2025-01-12 22:56 ` [PATCH 1/3] hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m' Philippe Mathieu-Daudé
2025-01-12 22:56 ` [PATCH 2/3] hw/arm/stellaris: Add 'armv7m' local variable Philippe Mathieu-Daudé
@ 2025-01-12 22:56 ` Philippe Mathieu-Daudé
2025-01-12 23:46 ` Alistair Francis
2025-01-13 8:27 ` Samuel Tardieu
2025-01-27 12:58 ` [PATCH 0/3] hw/arm/v7m: Remove Cortex-M &first_cpu uses Peter Maydell
3 siblings, 2 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-12 22:56 UTC (permalink / raw)
To: qemu-devel
Cc: Samuel Tardieu, qemu-arm, Peter Maydell, Felipe Balbi,
Subbaraya Sundeep, Alistair Francis, Joel Stanley,
Alexandre Iooss, Philippe Mathieu-Daudé
When instanciating the machine model, the machine_init()
implementations usually create the CPUs, so have access
to its first CPU. Use that rather then the &first_cpu
global.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/b-l475e-iot01a.c | 2 +-
hw/arm/microbit.c | 2 +-
hw/arm/mps2-tz.c | 2 +-
hw/arm/mps2.c | 2 +-
hw/arm/msf2-som.c | 2 +-
hw/arm/musca.c | 2 +-
hw/arm/netduino2.c | 2 +-
hw/arm/netduinoplus2.c | 2 +-
hw/arm/olimex-stm32-h405.c | 2 +-
hw/arm/stellaris.c | 2 +-
hw/arm/stm32vldiscovery.c | 2 +-
11 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index 5002a40f06d..c9a5209216c 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -82,7 +82,7 @@ static void bl475e_init(MachineState *machine)
sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
+ armv7m_load_kernel(s->soc.armv7m.cpu, machine->kernel_filename, 0,
sc->flash_size);
if (object_class_by_name(TYPE_DM163)) {
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index 374fbcb3618..3f56fb45ce1 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -56,7 +56,7 @@ static void microbit_init(MachineState *machine)
memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BASE,
mr, -1);
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(s->nrf51.armv7m.cpu, machine->kernel_filename,
0, s->nrf51.flash_size);
}
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 0136e419bfd..d3a9f1b03ac 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -1211,7 +1211,7 @@ static void mps2tz_common_init(MachineState *machine)
mms->remap_irq);
}
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(mms->iotkit.armv7m[0].cpu, machine->kernel_filename,
0, boot_ram_size(mms));
}
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index efb3500742f..56b2af40f1d 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -460,7 +460,7 @@ static void mps2_common_init(MachineState *machine)
qdev_get_gpio_in(armv7m,
mmc->fpga_type == FPGA_AN511 ? 47 : 13));
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(mms->armv7m.cpu, machine->kernel_filename,
0, 0x400000);
}
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 5c415abe852..9b20f1e2c98 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -92,7 +92,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(soc->armv7m.cpu, machine->kernel_filename,
0, soc->envm_size);
}
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index 3c3b534cb72..e9c092abc3d 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -590,7 +590,7 @@ static void musca_init(MachineState *machine)
"cfg_sec_resp", 0));
}
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(mms->sse.armv7m[0].cpu, machine->kernel_filename,
0, 0x2000000);
}
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index 8b1a9a24379..df793c77fe1 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -48,7 +48,7 @@ static void netduino2_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(STM32F205_SOC(dev)->armv7m.cpu, machine->kernel_filename,
0, FLASH_SIZE);
}
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index bccd1003549..81b6334cf72 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -48,7 +48,7 @@ static void netduinoplus2_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu),
+ armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu,
machine->kernel_filename,
0, FLASH_SIZE);
}
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index 4ad7b043be0..1f15620f9fd 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -51,7 +51,7 @@ static void olimex_stm32_h405_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu),
+ armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu,
machine->kernel_filename,
0, FLASH_SIZE);
}
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 7303e096ef7..284980ad4b5 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1366,7 +1366,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
- armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size);
+ armv7m_load_kernel(ARMV7M(armv7m)->cpu, ms->kernel_filename, 0, flash_size);
}
/* FIXME: Figure out how to generate these from stellaris_boards. */
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index cc419351605..e6c1f5b8d7d 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -51,7 +51,7 @@ static void stm32vldiscovery_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu),
+ armv7m_load_kernel(STM32F100_SOC(dev)->armv7m.cpu,
machine->kernel_filename,
0, FLASH_SIZE);
}
--
2.47.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 3/3] hw/arm/v7m: Remove use of &first_cpu in machine_init()
2025-01-12 22:56 ` [PATCH 3/3] hw/arm/v7m: Remove use of &first_cpu in machine_init() Philippe Mathieu-Daudé
@ 2025-01-12 23:46 ` Alistair Francis
2025-01-13 8:27 ` Samuel Tardieu
1 sibling, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2025-01-12 23:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Samuel Tardieu, qemu-arm, Peter Maydell, Felipe Balbi,
Subbaraya Sundeep, Alistair Francis, Joel Stanley,
Alexandre Iooss
On Mon, Jan 13, 2025 at 8:57 AM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> When instanciating the machine model, the machine_init()
> implementations usually create the CPUs, so have access
> to its first CPU. Use that rather then the &first_cpu
> global.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/arm/b-l475e-iot01a.c | 2 +-
> hw/arm/microbit.c | 2 +-
> hw/arm/mps2-tz.c | 2 +-
> hw/arm/mps2.c | 2 +-
> hw/arm/msf2-som.c | 2 +-
> hw/arm/musca.c | 2 +-
> hw/arm/netduino2.c | 2 +-
> hw/arm/netduinoplus2.c | 2 +-
> hw/arm/olimex-stm32-h405.c | 2 +-
> hw/arm/stellaris.c | 2 +-
> hw/arm/stm32vldiscovery.c | 2 +-
> 11 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
> index 5002a40f06d..c9a5209216c 100644
> --- a/hw/arm/b-l475e-iot01a.c
> +++ b/hw/arm/b-l475e-iot01a.c
> @@ -82,7 +82,7 @@ static void bl475e_init(MachineState *machine)
> sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
>
> sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
> + armv7m_load_kernel(s->soc.armv7m.cpu, machine->kernel_filename, 0,
> sc->flash_size);
>
> if (object_class_by_name(TYPE_DM163)) {
> diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
> index 374fbcb3618..3f56fb45ce1 100644
> --- a/hw/arm/microbit.c
> +++ b/hw/arm/microbit.c
> @@ -56,7 +56,7 @@ static void microbit_init(MachineState *machine)
> memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BASE,
> mr, -1);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(s->nrf51.armv7m.cpu, machine->kernel_filename,
> 0, s->nrf51.flash_size);
> }
>
> diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
> index 0136e419bfd..d3a9f1b03ac 100644
> --- a/hw/arm/mps2-tz.c
> +++ b/hw/arm/mps2-tz.c
> @@ -1211,7 +1211,7 @@ static void mps2tz_common_init(MachineState *machine)
> mms->remap_irq);
> }
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(mms->iotkit.armv7m[0].cpu, machine->kernel_filename,
> 0, boot_ram_size(mms));
> }
>
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index efb3500742f..56b2af40f1d 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -460,7 +460,7 @@ static void mps2_common_init(MachineState *machine)
> qdev_get_gpio_in(armv7m,
> mmc->fpga_type == FPGA_AN511 ? 47 : 13));
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(mms->armv7m.cpu, machine->kernel_filename,
> 0, 0x400000);
> }
>
> diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
> index 5c415abe852..9b20f1e2c98 100644
> --- a/hw/arm/msf2-som.c
> +++ b/hw/arm/msf2-som.c
> @@ -92,7 +92,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
> cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
> sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(soc->armv7m.cpu, machine->kernel_filename,
> 0, soc->envm_size);
> }
>
> diff --git a/hw/arm/musca.c b/hw/arm/musca.c
> index 3c3b534cb72..e9c092abc3d 100644
> --- a/hw/arm/musca.c
> +++ b/hw/arm/musca.c
> @@ -590,7 +590,7 @@ static void musca_init(MachineState *machine)
> "cfg_sec_resp", 0));
> }
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(mms->sse.armv7m[0].cpu, machine->kernel_filename,
> 0, 0x2000000);
> }
>
> diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
> index 8b1a9a24379..df793c77fe1 100644
> --- a/hw/arm/netduino2.c
> +++ b/hw/arm/netduino2.c
> @@ -48,7 +48,7 @@ static void netduino2_init(MachineState *machine)
> qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(STM32F205_SOC(dev)->armv7m.cpu, machine->kernel_filename,
> 0, FLASH_SIZE);
> }
>
> diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
> index bccd1003549..81b6334cf72 100644
> --- a/hw/arm/netduinoplus2.c
> +++ b/hw/arm/netduinoplus2.c
> @@ -48,7 +48,7 @@ static void netduinoplus2_init(MachineState *machine)
> qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu),
> + armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu,
> machine->kernel_filename,
> 0, FLASH_SIZE);
> }
> diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
> index 4ad7b043be0..1f15620f9fd 100644
> --- a/hw/arm/olimex-stm32-h405.c
> +++ b/hw/arm/olimex-stm32-h405.c
> @@ -51,7 +51,7 @@ static void olimex_stm32_h405_init(MachineState *machine)
> qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu),
> + armv7m_load_kernel(STM32F405_SOC(dev)->armv7m.cpu,
> machine->kernel_filename,
> 0, FLASH_SIZE);
> }
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index 7303e096ef7..284980ad4b5 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -1366,7 +1366,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
> create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
> create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size);
> + armv7m_load_kernel(ARMV7M(armv7m)->cpu, ms->kernel_filename, 0, flash_size);
> }
>
> /* FIXME: Figure out how to generate these from stellaris_boards. */
> diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
> index cc419351605..e6c1f5b8d7d 100644
> --- a/hw/arm/stm32vldiscovery.c
> +++ b/hw/arm/stm32vldiscovery.c
> @@ -51,7 +51,7 @@ static void stm32vldiscovery_init(MachineState *machine)
> qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu),
> + armv7m_load_kernel(STM32F100_SOC(dev)->armv7m.cpu,
> machine->kernel_filename,
> 0, FLASH_SIZE);
> }
> --
> 2.47.1
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 3/3] hw/arm/v7m: Remove use of &first_cpu in machine_init()
2025-01-12 22:56 ` [PATCH 3/3] hw/arm/v7m: Remove use of &first_cpu in machine_init() Philippe Mathieu-Daudé
2025-01-12 23:46 ` Alistair Francis
@ 2025-01-13 8:27 ` Samuel Tardieu
1 sibling, 0 replies; 10+ messages in thread
From: Samuel Tardieu @ 2025-01-13 8:27 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, qemu-arm, Peter Maydell, Felipe Balbi,
Subbaraya Sundeep, Alistair Francis, Joel Stanley,
Alexandre Iooss
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> When instanciating the machine model, the machine_init()
> implementations usually create the CPUs, so have access
> to its first CPU. Use that rather then the &first_cpu
> global.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Samuel Tardieu <sam@rfc1149.net>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/3] hw/arm/v7m: Remove Cortex-M &first_cpu uses
2025-01-12 22:56 [PATCH 0/3] hw/arm/v7m: Remove Cortex-M &first_cpu uses Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2025-01-12 22:56 ` [PATCH 3/3] hw/arm/v7m: Remove use of &first_cpu in machine_init() Philippe Mathieu-Daudé
@ 2025-01-27 12:58 ` Peter Maydell
3 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2025-01-27 12:58 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Samuel Tardieu, qemu-arm, Felipe Balbi,
Subbaraya Sundeep, Alistair Francis, Joel Stanley,
Alexandre Iooss
On Sun, 12 Jan 2025 at 22:56, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> After renaming a pair of fields in NRF51 & Stellaris boards,
> remove the &first_cpu global uses in Cortex-M boards.
>
> Rational is &first_cpu is going to be restricted to generic
> accelerator code, then be removed. Similarly the global
> 'cpus_queue' containing target-agnostic CPUs is going to be
> restricted to generic accelerator, thus hw/ won't have direct
> access to it anymore.
>
> Note, Cortex-A boards already have been dealt with in
> https://lore.kernel.org/qemu-devel/20231212162935.42910-1-philmd@linaro.org/
> "hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv"
>
> Philippe Mathieu-Daudé (3):
> hw/arm/nrf51: Rename ARMv7MState 'cpu' -> 'armv7m'
> hw/arm/stellaris: Add 'armv7m' local variable
> hw/arm/v7m: Remove use of &first_cpu in machine_init()
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread