[PATCH 00/11] Add Support for RZ/G3E ICU

[PATCH 00/11] Add Support for RZ/G3E ICU

[Biju Das]

The ICU block on the RZ/G3E SoC is almost identical to the one found on
the RZ/V2H SoC, with the following differences:
 - The TINT register offset is 0x830 compared to ox30 on RZ/V2H.
 - The number of supported GPIO interrupts for TINT selection is 141
   instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 15 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Add support for the RZ/G3E ICU driver.

Biju Das (11):
  dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E
    SoC
  clk: renesas: r9a09g047: Add ICU clock/reset
  irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv
  irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()
  irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable
  irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info
  irqchip/renesas-rzv2h: Add tssr_k variable to struct rzv2h_hw_info
  irqchip/renesas-rzv2h: Add tssel_mask and tssel_shift variables to
    struct rzv2h_hw_info
  irqchip/renesas-rzv2h: Add tien variable to struct rzv2h_hw_info
  irqchip/renesas-rzv2h: Add RZ/G3E support
  arm64: dts: renesas: r9a09g047: Add icu node

 .../renesas,rzv2h-icu.yaml                    |   6 +-
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 108 ++++++++++++
 drivers/clk/renesas/r9a09g047-cpg.c           |   3 +
 drivers/irqchip/irq-renesas-rzv2h.c           | 159 +++++++++++++-----
 4 files changed, 229 insertions(+), 47 deletions(-)

-- 
2.43.0

[PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC

[Biju Das]

Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E
SoC is almost identical to the one found on the RZ/V2H SoC, with the
following differences:
 - The TINT register offset is 0x830 compared to ox30 on RZ/V2H.
 - The number of supported GPIO interrupts for TINT selection is 141
   instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 15 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E
SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml    | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
index d7ef4f1323a7..3f99c8645767 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/V2H(P) Interrupt Control Unit
+title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit
 
 maintainers:
   - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
@@ -20,7 +20,9 @@ description:
 
 properties:
   compatible:
-    const: renesas,r9a09g057-icu # RZ/V2H(P)
+    enum:
+      - renesas,r9a09g047-icu # RZ/G3E
+      - renesas,r9a09g057-icu # RZ/V2H(P)
 
   '#interrupt-cells':
     description: The first cell is the SPI number of the NMI or the
-- 
2.43.0

RE: [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC

[Fabrizio Castro]

Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC
> 
> Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E
> SoC is almost identical to the one found on the RZ/V2H SoC, with the
> following differences:
>  - The TINT register offset is 0x830 compared to ox30 on RZ/V2H.
>  - The number of supported GPIO interrupts for TINT selection is 141
>    instead of 86.
>  - The pin index and TINT selection index are not in the 1:1 map
>  - The number of TSSR registers is 15 instead of 8
>  - Each TSSR register can program 2 TINTs instead of 4 TINTs
> 
> Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E
> SoC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Cheers,
Fab

> ---
>  .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml    | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
> b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
> index d7ef4f1323a7..3f99c8645767 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
> @@ -4,7 +4,7 @@
>  $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
> 
> -title: Renesas RZ/V2H(P) Interrupt Control Unit
> +title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit
> 
>  maintainers:
>    - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> @@ -20,7 +20,9 @@ description:
> 
>  properties:
>    compatible:
> -    const: renesas,r9a09g057-icu # RZ/V2H(P)
> +    enum:
> +      - renesas,r9a09g047-icu # RZ/G3E
> +      - renesas,r9a09g057-icu # RZ/V2H(P)
> 
>    '#interrupt-cells':
>      description: The first cell is the SPI number of the NMI or the
> --
> 2.43.0

Re: [PATCH 01/11] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC

[Rob Herring (Arm)]

On Mon, 20 Jan 2025 09:46:57 +0000, Biju Das wrote:
> Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E
> SoC is almost identical to the one found on the RZ/V2H SoC, with the
> following differences:
>  - The TINT register offset is 0x830 compared to ox30 on RZ/V2H.
>  - The number of supported GPIO interrupts for TINT selection is 141
>    instead of 86.
>  - The pin index and TINT selection index are not in the 1:1 map
>  - The number of TSSR registers is 15 instead of 8
>  - Each TSSR register can program 2 TINTs instead of 4 TINTs
> 
> Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E
> SoC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml    | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH 02/11] clk: renesas: r9a09g047: Add ICU clock/reset

[Biju Das]

Add ICU clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g047-cpg.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 1886eab9ef9e..1181e7b605e8 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -90,6 +90,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
 };
 
 static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
+	DEF_MOD_CRITICAL("icu_0_pclk_i",	CLK_PLLCM33_DIV16, 0, 5, 0, 5,
+						BUS_MSTOP_NONE),
 	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
 						BUS_MSTOP(3, BIT(5))),
 	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,
@@ -128,6 +130,7 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
 
 static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
 	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */
+	DEF_RST(3, 6, 1, 7),		/* ICU_0_PRESETN_I */
 	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */
 	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
 	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
-- 
2.43.0

RE: [PATCH 02/11] clk: renesas: r9a09g047: Add ICU clock/reset

[Fabrizio Castro]

Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 02/11] clk: renesas: r9a09g047: Add ICU clock/reset
> 
> Add ICU clock and reset entries.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Cheers,
Fab

> ---
>  drivers/clk/renesas/r9a09g047-cpg.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
> index 1886eab9ef9e..1181e7b605e8 100644
> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -90,6 +90,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
>  };
> 
>  static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> +	DEF_MOD_CRITICAL("icu_0_pclk_i",	CLK_PLLCM33_DIV16, 0, 5, 0, 5,
> +						BUS_MSTOP_NONE),
>  	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
>  						BUS_MSTOP(3, BIT(5))),
>  	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,
> @@ -128,6 +130,7 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> 
>  static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
>  	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */
> +	DEF_RST(3, 6, 1, 7),		/* ICU_0_PRESETN_I */
>  	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */
>  	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
>  	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
> --
> 2.43.0
> 

[PATCH 03/11] irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv

[Biju Das]

Use rzv2h_icu_chip directly on irq_domain_set_hwirq_and_chip() and drop
the global variable irqchip from struct rzv2h_icu_priv.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index fe2d29e91026..fd432b43506b 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -83,13 +83,11 @@
 /**
  * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
  * @base:	Controller's base address
- * @irqchip:	Pointer to struct irq_chip
  * @fwspec:	IRQ firmware specific data
  * @lock:	Lock to serialize access to hardware registers
  */
 struct rzv2h_icu_priv {
 	void __iomem			*base;
-	const struct irq_chip		*irqchip;
 	struct irq_fwspec		fwspec[ICU_NUM_IRQ];
 	raw_spinlock_t			lock;
 };
@@ -390,7 +388,7 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigne
 	if (hwirq > (ICU_NUM_IRQ - 1))
 		return -EINVAL;
 
-	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip,
+	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzv2h_icu_chip,
 					    (void *)(uintptr_t)tint);
 	if (ret)
 		return ret;
@@ -446,8 +444,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 		goto put_dev;
 	}
 
-	rzv2h_icu_data->irqchip = &rzv2h_icu_chip;
-
 	rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
 	if (IS_ERR(rzv2h_icu_data->base)) {
 		ret = PTR_ERR(rzv2h_icu_data->base);
-- 
2.43.0

RE: [PATCH 03/11] irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv

[Fabrizio Castro]

Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 03/11] irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv
> 
> Use rzv2h_icu_chip directly on irq_domain_set_hwirq_and_chip() and drop
> the global variable irqchip from struct rzv2h_icu_priv.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Cheers,
Fab

> ---
>  drivers/irqchip/irq-renesas-rzv2h.c | 6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index fe2d29e91026..fd432b43506b 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -83,13 +83,11 @@
>  /**
>   * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
>   * @base:	Controller's base address
> - * @irqchip:	Pointer to struct irq_chip
>   * @fwspec:	IRQ firmware specific data
>   * @lock:	Lock to serialize access to hardware registers
>   */
>  struct rzv2h_icu_priv {
>  	void __iomem			*base;
> -	const struct irq_chip		*irqchip;
>  	struct irq_fwspec		fwspec[ICU_NUM_IRQ];
>  	raw_spinlock_t			lock;
>  };
> @@ -390,7 +388,7 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigne
>  	if (hwirq > (ICU_NUM_IRQ - 1))
>  		return -EINVAL;
> 
> -	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip,
> +	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzv2h_icu_chip,
>  					    (void *)(uintptr_t)tint);
>  	if (ret)
>  		return ret;
> @@ -446,8 +444,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
>  		goto put_dev;
>  	}
> 
> -	rzv2h_icu_data->irqchip = &rzv2h_icu_chip;
> -
>  	rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
>  	if (IS_ERR(rzv2h_icu_data->base)) {
>  		ret = PTR_ERR(rzv2h_icu_data->base);
> --
> 2.43.0
> 

[PATCH 04/11] irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()

[Biju Das]

Simplify rzv2h_icu_init() by using newly added devm_* helpers.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index fd432b43506b..a02d47529564 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -456,23 +456,23 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 		goto put_dev;
 	}
 
-	resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+	resetn = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, NULL);
 	if (IS_ERR(resetn)) {
 		ret = PTR_ERR(resetn);
+		dev_err(&pdev->dev, "failed to acquire deasserted reset: %d\n", ret);
 		goto put_dev;
 	}
 
-	ret = reset_control_deassert(resetn);
-	if (ret) {
-		dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret);
+	ret = devm_pm_runtime_enable(&pdev->dev);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "devm_pm_runtime_enable failed, %d\n", ret);
 		goto put_dev;
 	}
 
-	pm_runtime_enable(&pdev->dev);
 	ret = pm_runtime_resume_and_get(&pdev->dev);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
-		goto pm_disable;
+		goto put_dev;
 	}
 
 	raw_spin_lock_init(&rzv2h_icu_data->lock);
@@ -493,9 +493,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 
 pm_put:
 	pm_runtime_put(&pdev->dev);
-pm_disable:
-	pm_runtime_disable(&pdev->dev);
-	reset_control_assert(resetn);
 put_dev:
 	put_device(&pdev->dev);
 
-- 
2.43.0

Re: [PATCH 04/11] irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()

[Philipp Zabel]

On Mo, 2025-01-20 at 09:47 +0000, Biju Das wrote:
> Simplify rzv2h_icu_init() by using newly added devm_* helpers.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  drivers/irqchip/irq-renesas-rzv2h.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index fd432b43506b..a02d47529564 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -456,23 +456,23 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
>  		goto put_dev;
>  	}
>  
> -	resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> +	resetn = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, NULL);

This changes the reset control to be optional without mentioning it in
the commit description. Should this change be part of another patch?

regards
Philipp

RE: [PATCH 04/11] irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()

[Biju Das]

Hi Philipp,

Thanks for the review.

> -----Original Message-----
> From: Philipp Zabel <p.zabel@pengutronix.de>
> Sent: 20 January 2025 10:05
> Subject: Re: [PATCH 04/11] irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()
> 
> On Mo, 2025-01-20 at 09:47 +0000, Biju Das wrote:
> > Simplify rzv2h_icu_init() by using newly added devm_* helpers.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  drivers/irqchip/irq-renesas-rzv2h.c | 15 ++++++---------
> >  1 file changed, 6 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c
> > b/drivers/irqchip/irq-renesas-rzv2h.c
> > index fd432b43506b..a02d47529564 100644
> > --- a/drivers/irqchip/irq-renesas-rzv2h.c
> > +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> > @@ -456,23 +456,23 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node
> *parent)
> >  		goto put_dev;
> >  	}
> >
> > -	resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > +	resetn =
> > +devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
> > +NULL);
> 
> This changes the reset control to be optional without mentioning it in the commit description. Should
> this change be part of another patch?

Thanks, It is a typo. It should be devm_reset_control_get_exclusive_deasserted.

I will split simplification patches into two in the next version.

1) Adding devm_reset_control_get_exclusive_deasserted()
2) Adding devm_pm_runtime_enable()

Cheers,
Biju

[PATCH 05/11] irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable

[Biju Das]

The ICU block on the RZ/G3E SoC is almost identical to the one found on
the RZ/V2H SoC, with the following differences:
 - The TINT register offset starts at 0x830 instead of 0x30.
 - The number of GPIO interrupts for TINT selection is 141 instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 15 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Introduce struct rzv2h_hw_info to handle these differences and add t_offs
variable to take care of the TINT register offset difference between
RZ/G3E and RZ/V2H.

Refactor the code by moving rzv2h_icu_init() into rzv2h_icu_init_common()
and pass the varable containing hw difference to support both these SoCs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 46 +++++++++++++++++++++--------
 1 file changed, 34 insertions(+), 12 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index a02d47529564..195ce9c5e5b5 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -80,16 +80,26 @@
 #define ICU_TINT_EXTRACT_GPIOINT(x)		FIELD_GET(GENMASK(31, 16), (x))
 #define ICU_PB5_TINT				0x55
 
+/**
+ * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @t_offs: TINT offset
+ */
+struct rzv2h_hw_info {
+	u16 t_offs;
+};
+
 /**
  * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
  * @base:	Controller's base address
  * @fwspec:	IRQ firmware specific data
  * @lock:	Lock to serialize access to hardware registers
+ * @info:	Pointer to struct rzv2h_hw_info
  */
 struct rzv2h_icu_priv {
 	void __iomem			*base;
 	struct irq_fwspec		fwspec[ICU_NUM_IRQ];
 	raw_spinlock_t			lock;
+	const struct rzv2h_hw_info	*info;
 };
 
 static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *data)
@@ -109,7 +119,7 @@ static void rzv2h_icu_eoi(struct irq_data *d)
 			tintirq_nr = hw_irq - ICU_TINT_START;
 			bit = BIT(tintirq_nr);
 			if (!irqd_is_level_type(d))
-				writel_relaxed(bit, priv->base + ICU_TSCLR);
+				writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
 		} else if (hw_irq >= ICU_IRQ_START) {
 			tintirq_nr = hw_irq - ICU_IRQ_START;
 			bit = BIT(tintirq_nr);
@@ -137,12 +147,12 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
 	tssel_n = ICU_TSSR_TSSEL_N(tint_nr);
 
 	guard(raw_spinlock)(&priv->lock);
-	tssr = readl_relaxed(priv->base + ICU_TSSR(k));
+	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
 	if (enable)
 		tssr |= ICU_TSSR_TIEN(tssel_n);
 	else
 		tssr &= ~ICU_TSSR_TIEN(tssel_n);
-	writel_relaxed(tssr, priv->base + ICU_TSSR(k));
+	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
 }
 
 static void rzv2h_icu_irq_disable(struct irq_data *d)
@@ -245,8 +255,8 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq
 	u32 bit = BIT(tint_nr);
 	int k = tint_nr / 16;
 
-	tsctr = readl_relaxed(priv->base + ICU_TSCTR);
-	titsr = readl_relaxed(priv->base + ICU_TITSR(k));
+	tsctr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSCTR);
+	titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(k));
 	titsel = ICU_TITSR_TITSEL_GET(titsr, titsel_n);
 
 	/*
@@ -255,7 +265,7 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq
 	 */
 	if ((tsctr & bit) && ((titsel == ICU_TINT_EDGE_RISING) ||
 			      (titsel == ICU_TINT_EDGE_FALLING)))
-		writel_relaxed(bit, priv->base + ICU_TSCLR);
+		writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
 }
 
 static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
@@ -306,21 +316,21 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 
 	guard(raw_spinlock)(&priv->lock);
 
-	tssr = readl_relaxed(priv->base + ICU_TSSR(tssr_k));
+	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
 	tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien);
 	tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n);
 
-	writel_relaxed(tssr, priv->base + ICU_TSSR(tssr_k));
+	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
 
-	titsr = readl_relaxed(priv->base + ICU_TITSR(titsr_k));
+	titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));
 	titsr &= ~ICU_TITSR_TITSEL_MASK(titsel_n);
 	titsr |= ICU_TITSR_TITSEL_PREP(sense, titsel_n);
 
-	writel_relaxed(titsr, priv->base + ICU_TITSR(titsr_k));
+	writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));
 
 	rzv2h_clear_tint_int(priv, hwirq);
 
-	writel_relaxed(tssr | tien, priv->base + ICU_TSSR(tssr_k));
+	writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
 
 	return 0;
 }
@@ -419,7 +429,8 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, struct device
 	return 0;
 }
 
-static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
+static int rzv2h_icu_init_common(struct device_node *node, struct device_node *parent,
+				 const struct rzv2h_hw_info *hw_info)
 {
 	struct irq_domain *irq_domain, *parent_domain;
 	struct rzv2h_icu_priv *rzv2h_icu_data;
@@ -485,6 +496,8 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 		goto pm_put;
 	}
 
+	rzv2h_icu_data->info = hw_info;
+
 	/*
 	 * coccicheck complains about a missing put_device call before returning, but it's a false
 	 * positive. We still need &pdev->dev after successfully returning from this function.
@@ -499,6 +512,15 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 	return ret;
 }
 
+static const struct rzv2h_hw_info rzv2h_hw_params = {
+	.t_offs = 0,
+};
+
+static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
+{
+	return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params);
+}
+
 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
 IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
 IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
-- 
2.43.0

RE: [PATCH 05/11] irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable

[Fabrizio Castro]

Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 05/11] irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable
> 
> The ICU block on the RZ/G3E SoC is almost identical to the one found on
> the RZ/V2H SoC, with the following differences:
>  - The TINT register offset starts at 0x830 instead of 0x30.
>  - The number of GPIO interrupts for TINT selection is 141 instead of 86.
>  - The pin index and TINT selection index are not in the 1:1 map
>  - The number of TSSR registers is 15 instead of 8
>  - Each TSSR register can program 2 TINTs instead of 4 TINTs
> 
> Introduce struct rzv2h_hw_info to handle these differences and add t_offs
> variable to take care of the TINT register offset difference between
> RZ/G3E and RZ/V2H.
> 
> Refactor the code by moving rzv2h_icu_init() into rzv2h_icu_init_common()
> and pass the varable containing hw difference to support both these SoCs.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Cheers,
Fab

> ---
>  drivers/irqchip/irq-renesas-rzv2h.c | 46 +++++++++++++++++++++--------
>  1 file changed, 34 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index a02d47529564..195ce9c5e5b5 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -80,16 +80,26 @@
>  #define ICU_TINT_EXTRACT_GPIOINT(x)		FIELD_GET(GENMASK(31, 16), (x))
>  #define ICU_PB5_TINT				0x55
> 
> +/**
> + * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
> + * @t_offs: TINT offset
> + */
> +struct rzv2h_hw_info {
> +	u16 t_offs;
> +};
> +
>  /**
>   * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
>   * @base:	Controller's base address
>   * @fwspec:	IRQ firmware specific data
>   * @lock:	Lock to serialize access to hardware registers
> + * @info:	Pointer to struct rzv2h_hw_info
>   */
>  struct rzv2h_icu_priv {
>  	void __iomem			*base;
>  	struct irq_fwspec		fwspec[ICU_NUM_IRQ];
>  	raw_spinlock_t			lock;
> +	const struct rzv2h_hw_info	*info;
>  };
> 
>  static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *data)
> @@ -109,7 +119,7 @@ static void rzv2h_icu_eoi(struct irq_data *d)
>  			tintirq_nr = hw_irq - ICU_TINT_START;
>  			bit = BIT(tintirq_nr);
>  			if (!irqd_is_level_type(d))
> -				writel_relaxed(bit, priv->base + ICU_TSCLR);
> +				writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
>  		} else if (hw_irq >= ICU_IRQ_START) {
>  			tintirq_nr = hw_irq - ICU_IRQ_START;
>  			bit = BIT(tintirq_nr);
> @@ -137,12 +147,12 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
>  	tssel_n = ICU_TSSR_TSSEL_N(tint_nr);
> 
>  	guard(raw_spinlock)(&priv->lock);
> -	tssr = readl_relaxed(priv->base + ICU_TSSR(k));
> +	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
>  	if (enable)
>  		tssr |= ICU_TSSR_TIEN(tssel_n);
>  	else
>  		tssr &= ~ICU_TSSR_TIEN(tssel_n);
> -	writel_relaxed(tssr, priv->base + ICU_TSSR(k));
> +	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
>  }
> 
>  static void rzv2h_icu_irq_disable(struct irq_data *d)
> @@ -245,8 +255,8 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq
>  	u32 bit = BIT(tint_nr);
>  	int k = tint_nr / 16;
> 
> -	tsctr = readl_relaxed(priv->base + ICU_TSCTR);
> -	titsr = readl_relaxed(priv->base + ICU_TITSR(k));
> +	tsctr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSCTR);
> +	titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(k));
>  	titsel = ICU_TITSR_TITSEL_GET(titsr, titsel_n);
> 
>  	/*
> @@ -255,7 +265,7 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq
>  	 */
>  	if ((tsctr & bit) && ((titsel == ICU_TINT_EDGE_RISING) ||
>  			      (titsel == ICU_TINT_EDGE_FALLING)))
> -		writel_relaxed(bit, priv->base + ICU_TSCLR);
> +		writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
>  }
> 
>  static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
> @@ -306,21 +316,21 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
> 
>  	guard(raw_spinlock)(&priv->lock);
> 
> -	tssr = readl_relaxed(priv->base + ICU_TSSR(tssr_k));
> +	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
>  	tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien);
>  	tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n);
> 
> -	writel_relaxed(tssr, priv->base + ICU_TSSR(tssr_k));
> +	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
> 
> -	titsr = readl_relaxed(priv->base + ICU_TITSR(titsr_k));
> +	titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));
>  	titsr &= ~ICU_TITSR_TITSEL_MASK(titsel_n);
>  	titsr |= ICU_TITSR_TITSEL_PREP(sense, titsel_n);
> 
> -	writel_relaxed(titsr, priv->base + ICU_TITSR(titsr_k));
> +	writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));
> 
>  	rzv2h_clear_tint_int(priv, hwirq);
> 
> -	writel_relaxed(tssr | tien, priv->base + ICU_TSSR(tssr_k));
> +	writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
> 
>  	return 0;
>  }
> @@ -419,7 +429,8 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, struct device
>  	return 0;
>  }
> 
> -static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
> +static int rzv2h_icu_init_common(struct device_node *node, struct device_node *parent,
> +				 const struct rzv2h_hw_info *hw_info)
>  {
>  	struct irq_domain *irq_domain, *parent_domain;
>  	struct rzv2h_icu_priv *rzv2h_icu_data;
> @@ -485,6 +496,8 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
>  		goto pm_put;
>  	}
> 
> +	rzv2h_icu_data->info = hw_info;
> +
>  	/*
>  	 * coccicheck complains about a missing put_device call before returning, but it's a false
>  	 * positive. We still need &pdev->dev after successfully returning from this function.
> @@ -499,6 +512,15 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
>  	return ret;
>  }
> 
> +static const struct rzv2h_hw_info rzv2h_hw_params = {
> +	.t_offs = 0,
> +};
> +
> +static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
> +{
> +	return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params);
> +}
> +
>  IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
>  IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
>  IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
> --
> 2.43.0
> 

[PATCH 06/11] irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info

[Biju Das]

The number of GPIO interrupts on RZ/G3E for TINT selection is 141 compared
to 86 on RZ/V2H.

Add max_tssel variable to struct rzv2h_hw_info to handle this difference.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 195ce9c5e5b5..b244cd61cba4 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -78,14 +78,15 @@
 
 #define ICU_TINT_EXTRACT_HWIRQ(x)		FIELD_GET(GENMASK(15, 0), (x))
 #define ICU_TINT_EXTRACT_GPIOINT(x)		FIELD_GET(GENMASK(31, 16), (x))
-#define ICU_PB5_TINT				0x55
 
 /**
  * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
  * @t_offs: TINT offset
+ * @max_tssel: TSSEL max value
  */
 struct rzv2h_hw_info {
 	u16 t_offs;
+	u8 max_tssel;
 };
 
 /**
@@ -298,13 +299,12 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 		return -EINVAL;
 	}
 
+	priv = irq_data_to_priv(d);
 	tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
-	if (tint > ICU_PB5_TINT)
+	if (tint > priv->info->max_tssel)
 		return -EINVAL;
 
-	priv = irq_data_to_priv(d);
 	hwirq = irqd_to_hwirq(d);
-
 	tint_nr = hwirq - ICU_TINT_START;
 
 	tssr_k = ICU_TSSR_K(tint_nr);
@@ -514,6 +514,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
 
 static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.t_offs = 0,
+	.max_tssel = 0x55,
 };
 
 static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
-- 
2.43.0

RE: [PATCH 06/11] irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info

[Fabrizio Castro]

Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 06/11] irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info
> 
> The number of GPIO interrupts on RZ/G3E for TINT selection is 141 compared
> to 86 on RZ/V2H.
> 
> Add max_tssel variable to struct rzv2h_hw_info to handle this difference.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Cheers,
Fab

> ---
>  drivers/irqchip/irq-renesas-rzv2h.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index 195ce9c5e5b5..b244cd61cba4 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -78,14 +78,15 @@
> 
>  #define ICU_TINT_EXTRACT_HWIRQ(x)		FIELD_GET(GENMASK(15, 0), (x))
>  #define ICU_TINT_EXTRACT_GPIOINT(x)		FIELD_GET(GENMASK(31, 16), (x))
> -#define ICU_PB5_TINT				0x55
> 
>  /**
>   * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
>   * @t_offs: TINT offset
> + * @max_tssel: TSSEL max value
>   */
>  struct rzv2h_hw_info {
>  	u16 t_offs;
> +	u8 max_tssel;
>  };
> 
>  /**
> @@ -298,13 +299,12 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
>  		return -EINVAL;
>  	}
> 
> +	priv = irq_data_to_priv(d);
>  	tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
> -	if (tint > ICU_PB5_TINT)
> +	if (tint > priv->info->max_tssel)
>  		return -EINVAL;
> 
> -	priv = irq_data_to_priv(d);
>  	hwirq = irqd_to_hwirq(d);
> -
>  	tint_nr = hwirq - ICU_TINT_START;
> 
>  	tssr_k = ICU_TSSR_K(tint_nr);
> @@ -514,6 +514,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
> 
>  static const struct rzv2h_hw_info rzv2h_hw_params = {
>  	.t_offs = 0,
> +	.max_tssel = 0x55,
>  };
> 
>  static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
> --
> 2.43.0
> 

Re: [PATCH 06/11] irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info

[Thomas Gleixner]

On Mon, Jan 20 2025 at 09:47, Biju Das wrote:
>  /**
>   * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
>   * @t_offs: TINT offset
> + * @max_tssel: TSSEL max value
>   */
>  struct rzv2h_hw_info {
>  	u16 t_offs;
> +	u8 max_tssel;

Both the kernel doc and the actual struct members want to be done in
tabular fashion.

https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers

>  };
>  
>  /**
> @@ -298,13 +299,12 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
>  		return -EINVAL;
>  	}
>  
> +	priv = irq_data_to_priv(d);
>  	tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
> -	if (tint > ICU_PB5_TINT)
> +	if (tint > priv->info->max_tssel)
>  		return -EINVAL;
>  
> -	priv = irq_data_to_priv(d);
>  	hwirq = irqd_to_hwirq(d);
> -
>  	tint_nr = hwirq - ICU_TINT_START;
>  
>  	tssr_k = ICU_TSSR_K(tint_nr);
> @@ -514,6 +514,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
>  
>  static const struct rzv2h_hw_info rzv2h_hw_params = {
>  	.t_offs = 0,
> +	.max_tssel = 0x55,

See documentation.

Thanks,

        tglx

RE: [PATCH 06/11] irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info

[Biju Das]

Hi Thomas Gleixner,

Thanks for the feedback.

> -----Original Message-----
> From: Thomas Gleixner <tglx@linutronix.de>
> Sent: 23 January 2025 10:54
> Subject: Re: [PATCH 06/11] irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info
> 
> On Mon, Jan 20 2025 at 09:47, Biju Das wrote:
> >  /**
> >   * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
> >   * @t_offs: TINT offset
> > + * @max_tssel: TSSEL max value
> >   */
> >  struct rzv2h_hw_info {
> >  	u16 t_offs;
> > +	u8 max_tssel;
> 
> Both the kernel doc and the actual struct members want to be done in tabular fashion.
> 
> https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-
> initializers

Thanks. I will fix it in next version.

> 
> >  };
> >
> >  /**
> > @@ -298,13 +299,12 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
> >  		return -EINVAL;
> >  	}
> >
> > +	priv = irq_data_to_priv(d);
> >  	tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
> > -	if (tint > ICU_PB5_TINT)
> > +	if (tint > priv->info->max_tssel)
> >  		return -EINVAL;
> >
> > -	priv = irq_data_to_priv(d);
> >  	hwirq = irqd_to_hwirq(d);
> > -
> >  	tint_nr = hwirq - ICU_TINT_START;
> >
> >  	tssr_k = ICU_TSSR_K(tint_nr);
> > @@ -514,6 +514,7 @@ static int rzv2h_icu_init_common(struct
> > device_node *node, struct device_node *p
> >
> >  static const struct rzv2h_hw_info rzv2h_hw_params = {
> >  	.t_offs = 0,
> > +	.max_tssel = 0x55,
> 
> See documentation.

OK, Will fix it.

Cheers,
Biju

[PATCH 07/11] irqchip/renesas-rzv2h: Add tssr_k variable to struct rzv2h_hw_info

[Biju Das]

On RZ/G3E the number of TSSR registers is 15 compared to 8 on RZ/V2H and
each TSSR register can program 2 TINTs compared to 4 on RZ/V2H.

Add tssr_k variable to struct rzv2h_hw_info to handle this difference and
drop the macros ICU_TSSR_K and ICU_TSSR_TSSEL_N.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index b244cd61cba4..a9a9723ff4bb 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -64,8 +64,6 @@
 #define ICU_TINT_LEVEL_HIGH			2
 #define ICU_TINT_LEVEL_LOW			3
 
-#define ICU_TSSR_K(tint_nr)			((tint_nr) / 4)
-#define ICU_TSSR_TSSEL_N(tint_nr)		((tint_nr) % 4)
 #define ICU_TSSR_TSSEL_PREP(tssel, n)		((tssel) << ((n) * 8))
 #define ICU_TSSR_TSSEL_MASK(n)			ICU_TSSR_TSSEL_PREP(0x7F, n)
 #define ICU_TSSR_TIEN(n)			(BIT(7) << ((n) * 8))
@@ -83,10 +81,12 @@
  * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
  * @t_offs: TINT offset
  * @max_tssel: TSSEL max value
+ * @tssr_k: TSSR index k
  */
 struct rzv2h_hw_info {
 	u16 t_offs;
 	u8 max_tssel;
+	u8 tssr_k;
 };
 
 /**
@@ -144,8 +144,8 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
 		return;
 
 	tint_nr = hw_irq - ICU_TINT_START;
-	k = ICU_TSSR_K(tint_nr);
-	tssel_n = ICU_TSSR_TSSEL_N(tint_nr);
+	k = tint_nr / priv->info->tssr_k;
+	tssel_n = tint_nr % priv->info->tssr_k;
 
 	guard(raw_spinlock)(&priv->lock);
 	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
@@ -307,8 +307,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	hwirq = irqd_to_hwirq(d);
 	tint_nr = hwirq - ICU_TINT_START;
 
-	tssr_k = ICU_TSSR_K(tint_nr);
-	tssel_n = ICU_TSSR_TSSEL_N(tint_nr);
+	tssr_k = tint_nr / priv->info->tssr_k;
+	tssel_n = tint_nr % priv->info->tssr_k;
 
 	titsr_k = ICU_TITSR_K(tint_nr);
 	titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
@@ -515,6 +515,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
 static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.t_offs = 0,
 	.max_tssel = 0x55,
+	.tssr_k = 4,
 };
 
 static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
-- 
2.43.0

RE: [PATCH 07/11] irqchip/renesas-rzv2h: Add tssr_k variable to struct rzv2h_hw_info

[Fabrizio Castro]

Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 07/11] irqchip/renesas-rzv2h: Add tssr_k variable to struct rzv2h_hw_info
> 
> On RZ/G3E the number of TSSR registers is 15 compared to 8 on RZ/V2H and
> each TSSR register can program 2 TINTs compared to 4 on RZ/V2H.
> 
> Add tssr_k variable to struct rzv2h_hw_info to handle this difference and
> drop the macros ICU_TSSR_K and ICU_TSSR_TSSEL_N.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Cheers,
Fab

> ---
>  drivers/irqchip/irq-renesas-rzv2h.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index b244cd61cba4..a9a9723ff4bb 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -64,8 +64,6 @@
>  #define ICU_TINT_LEVEL_HIGH			2
>  #define ICU_TINT_LEVEL_LOW			3
> 
> -#define ICU_TSSR_K(tint_nr)			((tint_nr) / 4)
> -#define ICU_TSSR_TSSEL_N(tint_nr)		((tint_nr) % 4)
>  #define ICU_TSSR_TSSEL_PREP(tssel, n)		((tssel) << ((n) * 8))
>  #define ICU_TSSR_TSSEL_MASK(n)			ICU_TSSR_TSSEL_PREP(0x7F, n)
>  #define ICU_TSSR_TIEN(n)			(BIT(7) << ((n) * 8))
> @@ -83,10 +81,12 @@
>   * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
>   * @t_offs: TINT offset
>   * @max_tssel: TSSEL max value
> + * @tssr_k: TSSR index k
>   */
>  struct rzv2h_hw_info {
>  	u16 t_offs;
>  	u8 max_tssel;
> +	u8 tssr_k;
>  };
> 
>  /**
> @@ -144,8 +144,8 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
>  		return;
> 
>  	tint_nr = hw_irq - ICU_TINT_START;
> -	k = ICU_TSSR_K(tint_nr);
> -	tssel_n = ICU_TSSR_TSSEL_N(tint_nr);
> +	k = tint_nr / priv->info->tssr_k;
> +	tssel_n = tint_nr % priv->info->tssr_k;
> 
>  	guard(raw_spinlock)(&priv->lock);
>  	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
> @@ -307,8 +307,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
>  	hwirq = irqd_to_hwirq(d);
>  	tint_nr = hwirq - ICU_TINT_START;
> 
> -	tssr_k = ICU_TSSR_K(tint_nr);
> -	tssel_n = ICU_TSSR_TSSEL_N(tint_nr);
> +	tssr_k = tint_nr / priv->info->tssr_k;
> +	tssel_n = tint_nr % priv->info->tssr_k;
> 
>  	titsr_k = ICU_TITSR_K(tint_nr);
>  	titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
> @@ -515,6 +515,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
>  static const struct rzv2h_hw_info rzv2h_hw_params = {
>  	.t_offs = 0,
>  	.max_tssel = 0x55,
> +	.tssr_k = 4,
>  };
> 
>  static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
> --
> 2.43.0
> 

[PATCH 08/11] irqchip/renesas-rzv2h: Add tssel_mask and tssel_shift variables to struct rzv2h_hw_info

[Biju Das]

On RZ/G3E each TSSR register can program 2 TINTs compared to 4 TINTs on
RZ/V2H. Add tssel_mask and tssel_shift variables to struct rzv2h_hw_info
to simplify the calculations when we add support for RZ/G3E and drop the
macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index a9a9723ff4bb..5990dcf72ef0 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -64,8 +64,6 @@
 #define ICU_TINT_LEVEL_HIGH			2
 #define ICU_TINT_LEVEL_LOW			3
 
-#define ICU_TSSR_TSSEL_PREP(tssel, n)		((tssel) << ((n) * 8))
-#define ICU_TSSR_TSSEL_MASK(n)			ICU_TSSR_TSSEL_PREP(0x7F, n)
 #define ICU_TSSR_TIEN(n)			(BIT(7) << ((n) * 8))
 
 #define ICU_TITSR_K(tint_nr)			((tint_nr) / 16)
@@ -80,11 +78,15 @@
 /**
  * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
  * @t_offs: TINT offset
+ * @tssel_mask: TSSEL mask
+ * @tssel_shift: TSSEL shift
  * @max_tssel: TSSEL max value
  * @tssr_k: TSSR index k
  */
 struct rzv2h_hw_info {
 	u16 t_offs;
+	u16 tssel_mask;
+	u8 tssel_shift;
 	u8 max_tssel;
 	u8 tssr_k;
 };
@@ -317,8 +319,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	guard(raw_spinlock)(&priv->lock);
 
 	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
-	tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien);
-	tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n);
+	tssr &= ~((priv->info->tssel_mask << (tssel_n * priv->info->tssel_shift)) | tien);
+	tssr |= (tint << (tssel_n * priv->info->tssel_shift));
 
 	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
 
@@ -515,6 +517,8 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
 static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.t_offs = 0,
 	.max_tssel = 0x55,
+	.tssel_mask = GENMASK(6, 0),
+	.tssel_shift = 8,
 	.tssr_k = 4,
 };
 
-- 
2.43.0

RE: [PATCH 08/11] irqchip/renesas-rzv2h: Add tssel_mask and tssel_shift variables to struct rzv2h_hw_info

[Fabrizio Castro]

Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 08/11] irqchip/renesas-rzv2h: Add tssel_mask and tssel_shift variables to struct
> rzv2h_hw_info
> 
> On RZ/G3E each TSSR register can program 2 TINTs compared to 4 TINTs on
> RZ/V2H. Add tssel_mask and tssel_shift variables to struct rzv2h_hw_info
> to simplify the calculations when we add support for RZ/G3E and drop the
> macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Cheers,
Fab

> ---
>  drivers/irqchip/irq-renesas-rzv2h.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index a9a9723ff4bb..5990dcf72ef0 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -64,8 +64,6 @@
>  #define ICU_TINT_LEVEL_HIGH			2
>  #define ICU_TINT_LEVEL_LOW			3
> 
> -#define ICU_TSSR_TSSEL_PREP(tssel, n)		((tssel) << ((n) * 8))
> -#define ICU_TSSR_TSSEL_MASK(n)			ICU_TSSR_TSSEL_PREP(0x7F, n)
>  #define ICU_TSSR_TIEN(n)			(BIT(7) << ((n) * 8))
> 
>  #define ICU_TITSR_K(tint_nr)			((tint_nr) / 16)
> @@ -80,11 +78,15 @@
>  /**
>   * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
>   * @t_offs: TINT offset
> + * @tssel_mask: TSSEL mask
> + * @tssel_shift: TSSEL shift
>   * @max_tssel: TSSEL max value
>   * @tssr_k: TSSR index k
>   */
>  struct rzv2h_hw_info {
>  	u16 t_offs;
> +	u16 tssel_mask;
> +	u8 tssel_shift;
>  	u8 max_tssel;
>  	u8 tssr_k;
>  };
> @@ -317,8 +319,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
>  	guard(raw_spinlock)(&priv->lock);
> 
>  	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
> -	tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien);
> -	tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n);
> +	tssr &= ~((priv->info->tssel_mask << (tssel_n * priv->info->tssel_shift)) | tien);
> +	tssr |= (tint << (tssel_n * priv->info->tssel_shift));
> 
>  	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
> 
> @@ -515,6 +517,8 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
>  static const struct rzv2h_hw_info rzv2h_hw_params = {
>  	.t_offs = 0,
>  	.max_tssel = 0x55,
> +	.tssel_mask = GENMASK(6, 0),
> +	.tssel_shift = 8,
>  	.tssr_k = 4,
>  };
> 
> --
> 2.43.0
> 

[PATCH 09/11] irqchip/renesas-rzv2h: Add tien variable to struct rzv2h_hw_info

[Biju Das]

The TINT enable position on RZ/G3E is BIT 15 compared to BIT 8 on RZ/V2H.
Add tien variable to struct rzv2h_hw_info to simplify the calculations
when we add support for RZ/G3E and drop the macro ICU_TSSR_TIEN.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index 5990dcf72ef0..a1ca34d33c93 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -64,8 +64,6 @@
 #define ICU_TINT_LEVEL_HIGH			2
 #define ICU_TINT_LEVEL_LOW			3
 
-#define ICU_TSSR_TIEN(n)			(BIT(7) << ((n) * 8))
-
 #define ICU_TITSR_K(tint_nr)			((tint_nr) / 16)
 #define ICU_TITSR_TITSEL_N(tint_nr)		((tint_nr) % 16)
 #define ICU_TITSR_TITSEL_PREP(titsel, n)	ICU_IITSR_IITSEL_PREP(titsel, n)
@@ -78,6 +76,7 @@
 /**
  * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
  * @t_offs: TINT offset
+ * @tien: TIEN mask
  * @tssel_mask: TSSEL mask
  * @tssel_shift: TSSEL shift
  * @max_tssel: TSSEL max value
@@ -85,6 +84,7 @@
  */
 struct rzv2h_hw_info {
 	u16 t_offs;
+	u16 tien;
 	u16 tssel_mask;
 	u8 tssel_shift;
 	u8 max_tssel;
@@ -152,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
 	guard(raw_spinlock)(&priv->lock);
 	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
 	if (enable)
-		tssr |= ICU_TSSR_TIEN(tssel_n);
+		tssr |= priv->info->tien << (tssel_n * priv->info->tssel_shift);
 	else
-		tssr &= ~ICU_TSSR_TIEN(tssel_n);
+		tssr &= ~(priv->info->tien << (tssel_n * priv->info->tssel_shift));
 	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
 }
 
@@ -314,7 +314,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 
 	titsr_k = ICU_TITSR_K(tint_nr);
 	titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
-	tien = ICU_TSSR_TIEN(titsel_n);
+	tien = priv->info->tien << (titsel_n * priv->info->tssel_shift);
 
 	guard(raw_spinlock)(&priv->lock);
 
@@ -517,6 +517,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
 static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.t_offs = 0,
 	.max_tssel = 0x55,
+	.tien = BIT(7),
 	.tssel_mask = GENMASK(6, 0),
 	.tssel_shift = 8,
 	.tssr_k = 4,
-- 
2.43.0

RE: [PATCH 09/11] irqchip/renesas-rzv2h: Add tien variable to struct rzv2h_hw_info

[Fabrizio Castro]

Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 09/11] irqchip/renesas-rzv2h: Add tien variable to struct rzv2h_hw_info
> 
> The TINT enable position on RZ/G3E is BIT 15 compared to BIT 8 on RZ/V2H.
> Add tien variable to struct rzv2h_hw_info to simplify the calculations
> when we add support for RZ/G3E and drop the macro ICU_TSSR_TIEN.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Cheers,
Fab

> ---
>  drivers/irqchip/irq-renesas-rzv2h.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index 5990dcf72ef0..a1ca34d33c93 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -64,8 +64,6 @@
>  #define ICU_TINT_LEVEL_HIGH			2
>  #define ICU_TINT_LEVEL_LOW			3
> 
> -#define ICU_TSSR_TIEN(n)			(BIT(7) << ((n) * 8))
> -
>  #define ICU_TITSR_K(tint_nr)			((tint_nr) / 16)
>  #define ICU_TITSR_TITSEL_N(tint_nr)		((tint_nr) % 16)
>  #define ICU_TITSR_TITSEL_PREP(titsel, n)	ICU_IITSR_IITSEL_PREP(titsel, n)
> @@ -78,6 +76,7 @@
>  /**
>   * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
>   * @t_offs: TINT offset
> + * @tien: TIEN mask
>   * @tssel_mask: TSSEL mask
>   * @tssel_shift: TSSEL shift
>   * @max_tssel: TSSEL max value
> @@ -85,6 +84,7 @@
>   */
>  struct rzv2h_hw_info {
>  	u16 t_offs;
> +	u16 tien;
>  	u16 tssel_mask;
>  	u8 tssel_shift;
>  	u8 max_tssel;
> @@ -152,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
>  	guard(raw_spinlock)(&priv->lock);
>  	tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
>  	if (enable)
> -		tssr |= ICU_TSSR_TIEN(tssel_n);
> +		tssr |= priv->info->tien << (tssel_n * priv->info->tssel_shift);
>  	else
> -		tssr &= ~ICU_TSSR_TIEN(tssel_n);
> +		tssr &= ~(priv->info->tien << (tssel_n * priv->info->tssel_shift));
>  	writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
>  }
> 
> @@ -314,7 +314,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
> 
>  	titsr_k = ICU_TITSR_K(tint_nr);
>  	titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
> -	tien = ICU_TSSR_TIEN(titsel_n);
> +	tien = priv->info->tien << (titsel_n * priv->info->tssel_shift);
> 
>  	guard(raw_spinlock)(&priv->lock);
> 
> @@ -517,6 +517,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
>  static const struct rzv2h_hw_info rzv2h_hw_params = {
>  	.t_offs = 0,
>  	.max_tssel = 0x55,
> +	.tien = BIT(7),
>  	.tssel_mask = GENMASK(6, 0),
>  	.tssel_shift = 8,
>  	.tssr_k = 4,
> --
> 2.43.0
> 

[PATCH 10/11] irqchip/renesas-rzv2h: Add RZ/G3E support

[Biju Das]

The ICU block on the RZ/G3E SoC is almost identical to the one found on
the RZ/V2H SoC, with the following differences:
 - The TINT register offset starts at 0x830 instead of 0x30.
 - The number of GPIO interrupts for TINT selection is 141 instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 15 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and
adding LUT for mapping between pin index and TINT selection index.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/irqchip/irq-renesas-rzv2h.c | 47 +++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
index a1ca34d33c93..a0d79b357379 100644
--- a/drivers/irqchip/irq-renesas-rzv2h.c
+++ b/drivers/irqchip/irq-renesas-rzv2h.c
@@ -75,6 +75,7 @@
 
 /**
  * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @tssel_lut: TINT lookup table
  * @t_offs: TINT offset
  * @tien: TIEN mask
  * @tssel_mask: TSSEL mask
@@ -83,6 +84,7 @@
  * @tssr_k: TSSR index k
  */
 struct rzv2h_hw_info {
+	const u8 *tssel_lut;
 	u16 t_offs;
 	u16 tien;
 	u16 tssel_mask;
@@ -306,6 +308,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
 	if (tint > priv->info->max_tssel)
 		return -EINVAL;
 
+	if (priv->info->tssel_lut)
+		tint = priv->info->tssel_lut[tint & 0xff];
+
 	hwirq = irqd_to_hwirq(d);
 	tint_nr = hwirq - ICU_TINT_START;
 
@@ -514,6 +519,42 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
 	return ret;
 }
 
+/* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */
+static const u8 rzg3e_tssel_lut[] = {
+	81, 82, 83, 84, 85, 86, 87, 88,		/* P00-P07 */
+	89, 90, 91, 92, 93, 94, 95, 96,		/* P10-P17 */
+	111, 112,				/* P20-P21 */
+	97, 98, 99, 100, 101, 102, 103, 104,	/* P30-P37 */
+	105, 106, 107, 108, 109, 110,		/* P40-P45 */
+	113, 114, 115, 116, 117, 118, 119,	/* P50-P56 */
+	120, 121, 122, 123, 124, 125, 126,	/* P60-P66 */
+	127, 128, 129, 130, 131, 132, 133, 134,	/* P70-P77 */
+	135, 136, 137, 138, 139, 140,		/* P80-P85 */
+	43, 44, 45, 46, 47, 48, 49, 50,		/* PA0-PA7 */
+	51, 52, 53, 54, 55, 56, 57, 58,		/* PB0-PB7 */
+	59, 60,	61,				/* PC0-PC2 */
+	62, 63, 64, 65, 66, 67, 68, 69,		/* PD0-PD7 */
+	70, 71, 72, 73, 74, 75, 76, 77,		/* PE0-PE7 */
+	78, 79, 80,				/* PF0-PF2 */
+	25, 26, 27, 28, 29, 30, 31, 32,		/* PG0-PG7 */
+	33, 34, 35, 36, 37, 38,			/* PH0-PH5 */
+	4, 5, 6, 7, 8,				/* PJ0-PJ4 */
+	39, 40, 41, 42,				/* PK0-PK3 */
+	9, 10, 11, 12, 21, 22, 23, 24,		/* PL0-PL7 */
+	13, 14, 15, 16, 17, 18, 19, 20,		/* PM0-PM7 */
+	0, 1, 2, 3				/* PS0-PS3 */
+};
+
+static const struct rzv2h_hw_info rzg3e_hw_params = {
+	.tssel_lut = rzg3e_tssel_lut,
+	.t_offs = 0x800,
+	.max_tssel = 0x8c,
+	.tien = BIT(15),
+	.tssel_mask = GENMASK(7, 0),
+	.tssel_shift = 16,
+	.tssr_k = 2,
+};
+
 static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.t_offs = 0,
 	.max_tssel = 0x55,
@@ -523,12 +564,18 @@ static const struct rzv2h_hw_info rzv2h_hw_params = {
 	.tssr_k = 4,
 };
 
+static int rzg3e_icu_init(struct device_node *node, struct device_node *parent)
+{
+	return rzv2h_icu_init_common(node, parent, &rzg3e_hw_params);
+}
+
 static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
 {
 	return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params);
 }
 
 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
+IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init)
 IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
 IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
 MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
-- 
2.43.0

RE: [PATCH 10/11] irqchip/renesas-rzv2h: Add RZ/G3E support

[Fabrizio Castro]

Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 10/11] irqchip/renesas-rzv2h: Add RZ/G3E support
> 
> The ICU block on the RZ/G3E SoC is almost identical to the one found on
> the RZ/V2H SoC, with the following differences:
>  - The TINT register offset starts at 0x830 instead of 0x30.
>  - The number of GPIO interrupts for TINT selection is 141 instead of 86.
>  - The pin index and TINT selection index are not in the 1:1 map
>  - The number of TSSR registers is 15 instead of 8
>  - Each TSSR register can program 2 TINTs instead of 4 TINTs
> 
> Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and
> adding LUT for mapping between pin index and TINT selection index.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Cheers,
Fab

> ---
>  drivers/irqchip/irq-renesas-rzv2h.c | 47 +++++++++++++++++++++++++++++
>  1 file changed, 47 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c
> index a1ca34d33c93..a0d79b357379 100644
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -75,6 +75,7 @@
> 
>  /**
>   * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
> + * @tssel_lut: TINT lookup table
>   * @t_offs: TINT offset
>   * @tien: TIEN mask
>   * @tssel_mask: TSSEL mask
> @@ -83,6 +84,7 @@
>   * @tssr_k: TSSR index k
>   */
>  struct rzv2h_hw_info {
> +	const u8 *tssel_lut;
>  	u16 t_offs;
>  	u16 tien;
>  	u16 tssel_mask;
> @@ -306,6 +308,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
>  	if (tint > priv->info->max_tssel)
>  		return -EINVAL;
> 
> +	if (priv->info->tssel_lut)
> +		tint = priv->info->tssel_lut[tint & 0xff];
> +
>  	hwirq = irqd_to_hwirq(d);
>  	tint_nr = hwirq - ICU_TINT_START;
> 
> @@ -514,6 +519,42 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p
>  	return ret;
>  }
> 
> +/* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */
> +static const u8 rzg3e_tssel_lut[] = {
> +	81, 82, 83, 84, 85, 86, 87, 88,		/* P00-P07 */
> +	89, 90, 91, 92, 93, 94, 95, 96,		/* P10-P17 */
> +	111, 112,				/* P20-P21 */
> +	97, 98, 99, 100, 101, 102, 103, 104,	/* P30-P37 */
> +	105, 106, 107, 108, 109, 110,		/* P40-P45 */
> +	113, 114, 115, 116, 117, 118, 119,	/* P50-P56 */
> +	120, 121, 122, 123, 124, 125, 126,	/* P60-P66 */
> +	127, 128, 129, 130, 131, 132, 133, 134,	/* P70-P77 */
> +	135, 136, 137, 138, 139, 140,		/* P80-P85 */
> +	43, 44, 45, 46, 47, 48, 49, 50,		/* PA0-PA7 */
> +	51, 52, 53, 54, 55, 56, 57, 58,		/* PB0-PB7 */
> +	59, 60,	61,				/* PC0-PC2 */
> +	62, 63, 64, 65, 66, 67, 68, 69,		/* PD0-PD7 */
> +	70, 71, 72, 73, 74, 75, 76, 77,		/* PE0-PE7 */
> +	78, 79, 80,				/* PF0-PF2 */
> +	25, 26, 27, 28, 29, 30, 31, 32,		/* PG0-PG7 */
> +	33, 34, 35, 36, 37, 38,			/* PH0-PH5 */
> +	4, 5, 6, 7, 8,				/* PJ0-PJ4 */
> +	39, 40, 41, 42,				/* PK0-PK3 */
> +	9, 10, 11, 12, 21, 22, 23, 24,		/* PL0-PL7 */
> +	13, 14, 15, 16, 17, 18, 19, 20,		/* PM0-PM7 */
> +	0, 1, 2, 3				/* PS0-PS3 */
> +};
> +
> +static const struct rzv2h_hw_info rzg3e_hw_params = {
> +	.tssel_lut = rzg3e_tssel_lut,
> +	.t_offs = 0x800,
> +	.max_tssel = 0x8c,
> +	.tien = BIT(15),
> +	.tssel_mask = GENMASK(7, 0),
> +	.tssel_shift = 16,
> +	.tssr_k = 2,
> +};
> +
>  static const struct rzv2h_hw_info rzv2h_hw_params = {
>  	.t_offs = 0,
>  	.max_tssel = 0x55,
> @@ -523,12 +564,18 @@ static const struct rzv2h_hw_info rzv2h_hw_params = {
>  	.tssr_k = 4,
>  };
> 
> +static int rzg3e_icu_init(struct device_node *node, struct device_node *parent)
> +{
> +	return rzv2h_icu_init_common(node, parent, &rzg3e_hw_params);
> +}
> +
>  static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
>  {
>  	return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params);
>  }
> 
>  IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
> +IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init)
>  IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
>  IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
>  MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
> --
> 2.43.0
> 

[PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node

[Biju Das]

Add interrupt control node to RZ/G3E ("R9A09G047") SoC DTSI
and add icu as interrupt-parent of pincontrol.

Also, define the ICU IRQs for board DT users.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 108 +++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 133aa3272d3a..0beac052f208 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -8,6 +8,24 @@
 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
+#define RZG3E_NMI	0
+#define RZG3E_IRQ0	1
+#define RZG3E_IRQ1	2
+#define RZG3E_IRQ2	3
+#define RZG3E_IRQ3	4
+#define RZG3E_IRQ4	5
+#define RZG3E_IRQ5	6
+#define RZG3E_IRQ6	7
+#define RZG3E_IRQ7	8
+#define RZG3E_IRQ8	9
+#define RZG3E_IRQ9	10
+#define RZG3E_IRQ10	11
+#define RZG3E_IRQ11	12
+#define RZG3E_IRQ12	13
+#define RZG3E_IRQ13	14
+#define RZG3E_IRQ14	15
+#define RZG3E_IRQ15	16
+
 / {
 	compatible = "renesas,r9a09g047";
 	#address-cells = <2>;
@@ -131,6 +149,95 @@ soc: soc {
 		#size-cells = <2>;
 		ranges;
 
+		icu: interrupt-controller@10400000 {
+			compatible = "renesas,r9a09g047-icu";
+			reg = <0 0x10400000 0 0x10000>;
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "nmi",
+					  "port_irq0", "port_irq1", "port_irq2",
+					  "port_irq3", "port_irq4", "port_irq5",
+					  "port_irq6", "port_irq7", "port_irq8",
+					  "port_irq9", "port_irq10", "port_irq11",
+					  "port_irq12", "port_irq13", "port_irq14",
+					  "port_irq15",
+					  "tint0", "tint1", "tint2", "tint3",
+					  "tint4", "tint5", "tint6", "tint7",
+					  "tint8", "tint9", "tint10", "tint11",
+					  "tint12", "tint13", "tint14", "tint15",
+					  "tint16", "tint17", "tint18", "tint19",
+					  "tint20", "tint21", "tint22", "tint23",
+					  "tint24", "tint25", "tint26", "tint27",
+					  "tint28", "tint29", "tint30", "tint31",
+					  "int-ca55-0", "int-ca55-1",
+					  "int-ca55-2", "int-ca55-3",
+					  "icu-error-ca55",
+					  "gpt-u0-gtciada", "gpt-u0-gtciadb",
+					  "gpt-u1-gtciada", "gpt-u1-gtciadb";
+			clocks = <&cpg CPG_MOD 0x5>;
+			power-domains = <&cpg>;
+			resets = <&cpg 0x36>;
+		};
+
 		pinctrl: pinctrl@10410000 {
 			compatible = "renesas,r9a09g047-pinctrl";
 			reg = <0 0x10410000 0 0x10000>;
@@ -140,6 +247,7 @@ pinctrl: pinctrl@10410000 {
 			gpio-ranges = <&pinctrl 0 0 232>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
+			interrupt-parent = <&icu>;
 			power-domains = <&cpg>;
 			resets = <&cpg 0xa5>, <&cpg 0xa6>;
 		};
-- 
2.43.0

RE: [PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node

[Fabrizio Castro]

Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 11/11] arm64: dts: renesas: r9a09g047: Add icu node
> 
> Add interrupt control node to RZ/G3E ("R9A09G047") SoC DTSI
> and add icu as interrupt-parent of pincontrol.
> 
> Also, define the ICU IRQs for board DT users.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Cheers,
Fab

> ---
>  arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 108 +++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> index 133aa3272d3a..0beac052f208 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> @@ -8,6 +8,24 @@
>  #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> 
> +#define RZG3E_NMI	0
> +#define RZG3E_IRQ0	1
> +#define RZG3E_IRQ1	2
> +#define RZG3E_IRQ2	3
> +#define RZG3E_IRQ3	4
> +#define RZG3E_IRQ4	5
> +#define RZG3E_IRQ5	6
> +#define RZG3E_IRQ6	7
> +#define RZG3E_IRQ7	8
> +#define RZG3E_IRQ8	9
> +#define RZG3E_IRQ9	10
> +#define RZG3E_IRQ10	11
> +#define RZG3E_IRQ11	12
> +#define RZG3E_IRQ12	13
> +#define RZG3E_IRQ13	14
> +#define RZG3E_IRQ14	15
> +#define RZG3E_IRQ15	16
> +
>  / {
>  	compatible = "renesas,r9a09g047";
>  	#address-cells = <2>;
> @@ -131,6 +149,95 @@ soc: soc {
>  		#size-cells = <2>;
>  		ranges;
> 
> +		icu: interrupt-controller@10400000 {
> +			compatible = "renesas,r9a09g047-icu";
> +			reg = <0 0x10400000 0 0x10000>;
> +			#interrupt-cells = <2>;
> +			#address-cells = <0>;
> +			interrupt-controller;
> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "nmi",
> +					  "port_irq0", "port_irq1", "port_irq2",
> +					  "port_irq3", "port_irq4", "port_irq5",
> +					  "port_irq6", "port_irq7", "port_irq8",
> +					  "port_irq9", "port_irq10", "port_irq11",
> +					  "port_irq12", "port_irq13", "port_irq14",
> +					  "port_irq15",
> +					  "tint0", "tint1", "tint2", "tint3",
> +					  "tint4", "tint5", "tint6", "tint7",
> +					  "tint8", "tint9", "tint10", "tint11",
> +					  "tint12", "tint13", "tint14", "tint15",
> +					  "tint16", "tint17", "tint18", "tint19",
> +					  "tint20", "tint21", "tint22", "tint23",
> +					  "tint24", "tint25", "tint26", "tint27",
> +					  "tint28", "tint29", "tint30", "tint31",
> +					  "int-ca55-0", "int-ca55-1",
> +					  "int-ca55-2", "int-ca55-3",
> +					  "icu-error-ca55",
> +					  "gpt-u0-gtciada", "gpt-u0-gtciadb",
> +					  "gpt-u1-gtciada", "gpt-u1-gtciadb";
> +			clocks = <&cpg CPG_MOD 0x5>;
> +			power-domains = <&cpg>;
> +			resets = <&cpg 0x36>;
> +		};
> +
>  		pinctrl: pinctrl@10410000 {
>  			compatible = "renesas,r9a09g047-pinctrl";
>  			reg = <0 0x10410000 0 0x10000>;
> @@ -140,6 +247,7 @@ pinctrl: pinctrl@10410000 {
>  			gpio-ranges = <&pinctrl 0 0 232>;
>  			#interrupt-cells = <2>;
>  			interrupt-controller;
> +			interrupt-parent = <&icu>;
>  			power-domains = <&cpg>;
>  			resets = <&cpg 0xa5>, <&cpg 0xa6>;
>  		};
> --
> 2.43.0
> 

Re: [PATCH 00/11] Add Support for RZ/G3E ICU

[Tommaso Merciai]

Hi Biju,

On Mon, Jan 20, 2025 at 09:46:56AM +0000, Biju Das wrote:
> The ICU block on the RZ/G3E SoC is almost identical to the one found on
> the RZ/V2H SoC, with the following differences:
>  - The TINT register offset is 0x830 compared to ox30 on RZ/V2H.
>  - The number of supported GPIO interrupts for TINT selection is 141
>    instead of 86.
>  - The pin index and TINT selection index are not in the 1:1 map
>  - The number of TSSR registers is 15 instead of 8
>  - Each TSSR register can program 2 TINTs instead of 4 TINTs
> 
> Add support for the RZ/G3E ICU driver.
> 
> Biju Das (11):
>   dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E
>     SoC
>   clk: renesas: r9a09g047: Add ICU clock/reset
>   irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv
>   irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()
>   irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable
>   irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info
>   irqchip/renesas-rzv2h: Add tssr_k variable to struct rzv2h_hw_info
>   irqchip/renesas-rzv2h: Add tssel_mask and tssel_shift variables to
>     struct rzv2h_hw_info
>   irqchip/renesas-rzv2h: Add tien variable to struct rzv2h_hw_info
>   irqchip/renesas-rzv2h: Add RZ/G3E support
>   arm64: dts: renesas: r9a09g047: Add icu node
> 
>  .../renesas,rzv2h-icu.yaml                    |   6 +-
>  arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 108 ++++++++++++
>  drivers/clk/renesas/r9a09g047-cpg.c           |   3 +
>  drivers/irqchip/irq-renesas-rzv2h.c           | 159 +++++++++++++-----
>  4 files changed, 229 insertions(+), 47 deletions(-)
> 
> -- 
> 2.43.0

For all the series:
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Thanks & Regards,
Tommaso