* [PATCH v6 01/10] tests/qtest: Enforce zero for the "un-fired" msix message value
2026-08-17 18:55 [PATCH v6 00/10] tests/qtest: pci and MSI-X fixes Jishnu Warrier
@ 2026-08-17 18:55 ` Jishnu Warrier
2026-08-17 18:55 ` [PATCH v6 02/10] tests/qtest: Fix virtio msix message endianness Jishnu Warrier
` (7 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Jishnu Warrier @ 2026-08-17 18:55 UTC (permalink / raw)
To: qemu-devel
Cc: npiggin, philmd, farosas, akihiko.odaki, mst, marcel.apfelbaum,
david, adityag, harshpb, amachhiw
From: Nicholas Piggin <npiggin@gmail.com>
virtio-pci detects an unmasked msix interrupt has fired by looking
for the data payload value at the target address. If a value of zero
is enforced for the memory value when an interrupt has not fired,
then an assertion can be added to catch the case where something
changed the memory to an unexpected value.
This catches an endian conversion bug in the message value when
running these tests on a big endian target. Previously the test
just times out waiting for interrupt, after this it fails nicely.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/libqos/virtio-pci-modern.c | 9 +++++----
tests/qtest/libqos/virtio-pci.c | 20 ++++++++++++--------
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/tests/qtest/libqos/virtio-pci-modern.c b/tests/qtest/libqos/virtio-pci-modern.c
index 4e67fcbd..f31b3be6 100644
--- a/tests/qtest/libqos/virtio-pci-modern.c
+++ b/tests/qtest/libqos/virtio-pci-modern.c
@@ -137,12 +137,13 @@ static bool get_msix_status(QVirtioPCIDevice *dev, uint32_t msix_entry,
}
data = qtest_readl(dev->pdev->bus->qts, msix_addr);
- if (data == msix_data) {
- qtest_writel(dev->pdev->bus->qts, msix_addr, 0);
- return true;
- } else {
+ if (data == 0) {
return false;
}
+ /* got a message, ensure it matches expected value then clear it. */
+ g_assert_cmphex(data, ==, msix_data);
+ qtest_writel(dev->pdev->bus->qts, msix_addr, 0);
+ return true;
}
static bool get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
diff --git a/tests/qtest/libqos/virtio-pci.c b/tests/qtest/libqos/virtio-pci.c
index 002bf8b8..102e45b5 100644
--- a/tests/qtest/libqos/virtio-pci.c
+++ b/tests/qtest/libqos/virtio-pci.c
@@ -132,12 +132,13 @@ static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
} else {
data = qtest_readl(dev->pdev->bus->qts, vqpci->msix_addr);
- if (data == vqpci->msix_data) {
- qtest_writel(dev->pdev->bus->qts, vqpci->msix_addr, 0);
- return true;
- } else {
+ if (data == 0) {
return false;
}
+ /* got a message, ensure it matches expected value then clear it. */
+ g_assert_cmphex(data, ==, vqpci->msix_data);
+ qtest_writel(dev->pdev->bus->qts, vqpci->msix_addr, 0);
+ return true;
}
} else {
return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 1;
@@ -156,12 +157,13 @@ static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
} else {
data = qtest_readl(dev->pdev->bus->qts, dev->config_msix_addr);
- if (data == dev->config_msix_data) {
- qtest_writel(dev->pdev->bus->qts, dev->config_msix_addr, 0);
- return true;
- } else {
+ if (data == 0) {
return false;
}
+ /* got a message, ensure it matches expected value then clear it. */
+ g_assert_cmphex(data, ==, dev->config_msix_data);
+ qtest_writel(dev->pdev->bus->qts, dev->config_msix_addr, 0);
+ return true;
}
} else {
return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 2;
@@ -323,6 +325,7 @@ void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
vqpci->msix_entry = entry;
vqpci->msix_addr = guest_alloc(alloc, 4);
+ qtest_memset(d->pdev->bus->qts, vqpci->msix_addr, 0, 4);
qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_LOWER_ADDR, vqpci->msix_addr & ~0UL);
qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
@@ -355,6 +358,7 @@ void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
d->config_msix_data = 0x12345678;
d->config_msix_addr = guest_alloc(alloc, 4);
+ qtest_memset(d->pdev->bus->qts, d->config_msix_addr, 0, 4);
qpci_io_writel(d->pdev, d->pdev->msix_table_bar,
off + PCI_MSIX_ENTRY_LOWER_ADDR, d->config_msix_addr & ~0UL);
--
2.55.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 02/10] tests/qtest: Fix virtio msix message endianness
2026-08-17 18:55 [PATCH v6 00/10] tests/qtest: pci and MSI-X fixes Jishnu Warrier
2026-08-17 18:55 ` [PATCH v6 01/10] tests/qtest: Enforce zero for the "un-fired" msix message value Jishnu Warrier
@ 2026-08-17 18:55 ` Jishnu Warrier
2026-08-17 18:55 ` [PATCH v6 03/10] tests/qtest: Add libqos function for testing msix interrupt status Jishnu Warrier
` (6 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Jishnu Warrier @ 2026-08-17 18:55 UTC (permalink / raw)
To: qemu-devel
Cc: npiggin, philmd, farosas, akihiko.odaki, mst, marcel.apfelbaum,
david, adityag, harshpb, amachhiw
From: Nicholas Piggin <npiggin@gmail.com>
msix messages are written to memory in little-endian order, so they
should not be byteswapped depending on target endianness, but read
as le and converted to host endian by the qtest.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/libqos/virtio-pci-modern.c | 4 +++-
tests/qtest/libqos/virtio-pci.c | 6 ++++--
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/tests/qtest/libqos/virtio-pci-modern.c b/tests/qtest/libqos/virtio-pci-modern.c
index f31b3be6..5dae41e6 100644
--- a/tests/qtest/libqos/virtio-pci-modern.c
+++ b/tests/qtest/libqos/virtio-pci-modern.c
@@ -8,6 +8,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/bswap.h"
#include "standard-headers/linux/pci_regs.h"
#include "standard-headers/linux/virtio_pci.h"
#include "standard-headers/linux/virtio_config.h"
@@ -136,7 +137,8 @@ static bool get_msix_status(QVirtioPCIDevice *dev, uint32_t msix_entry,
return qpci_msix_pending(dev->pdev, msix_entry);
}
- data = qtest_readl(dev->pdev->bus->qts, msix_addr);
+ qtest_memread(dev->pdev->bus->qts, msix_addr, &data, 4);
+ data = le32_to_cpu(data);
if (data == 0) {
return false;
}
diff --git a/tests/qtest/libqos/virtio-pci.c b/tests/qtest/libqos/virtio-pci.c
index 102e45b5..76ea1f45 100644
--- a/tests/qtest/libqos/virtio-pci.c
+++ b/tests/qtest/libqos/virtio-pci.c
@@ -131,7 +131,8 @@ static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
/* No ISR checking should be done if masked, but read anyway */
return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
} else {
- data = qtest_readl(dev->pdev->bus->qts, vqpci->msix_addr);
+ qtest_memread(dev->pdev->bus->qts, vqpci->msix_addr, &data, 4);
+ data = le32_to_cpu(data);
if (data == 0) {
return false;
}
@@ -156,7 +157,8 @@ static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
/* No ISR checking should be done if masked, but read anyway */
return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
} else {
- data = qtest_readl(dev->pdev->bus->qts, dev->config_msix_addr);
+ qtest_memread(dev->pdev->bus->qts, dev->config_msix_addr, &data, 4);
+ data = le32_to_cpu(data);
if (data == 0) {
return false;
}
--
2.55.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 03/10] tests/qtest: Add libqos function for testing msix interrupt status
2026-08-17 18:55 [PATCH v6 00/10] tests/qtest: pci and MSI-X fixes Jishnu Warrier
2026-08-17 18:55 ` [PATCH v6 01/10] tests/qtest: Enforce zero for the "un-fired" msix message value Jishnu Warrier
2026-08-17 18:55 ` [PATCH v6 02/10] tests/qtest: Fix virtio msix message endianness Jishnu Warrier
@ 2026-08-17 18:55 ` Jishnu Warrier
2026-08-17 18:55 ` [PATCH v6 04/10] tests/qtest: Enable spapr dma with linear iommu map Jishnu Warrier
` (5 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Jishnu Warrier @ 2026-08-17 18:55 UTC (permalink / raw)
To: qemu-devel
Cc: npiggin, philmd, farosas, akihiko.odaki, mst, marcel.apfelbaum,
david, adityag, harshpb, amachhiw
From: Nicholas Piggin <npiggin@gmail.com>
This function is duplicated 3 times, with more potential future users.
Factor it into libqos, using qtest_memset instead of qtest_writel to
clear the message just because that looks nicer with the qtest_memread
used to read it.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/libqos/pci.c | 53 ++++++++++++++++++++++++++
tests/qtest/libqos/pci.h | 2 +
tests/qtest/libqos/virtio-pci-modern.c | 31 +++------------
tests/qtest/libqos/virtio-pci.c | 40 ++++---------------
4 files changed, 67 insertions(+), 59 deletions(-)
diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c
index a59197b9..986ce31d 100644
--- a/tests/qtest/libqos/pci.c
+++ b/tests/qtest/libqos/pci.c
@@ -351,6 +351,59 @@ bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry)
}
}
+/**
+ * qpci_msix_test_interrupt - test whether msix interrupt has been raised
+ * @dev: PCI device
+ * @msix_entry: msix entry to test
+ * @msix_addr: address of msix message
+ * @msix_data: expected msix message payload
+ *
+ * This tests whether the msix source has raised an interrupt. If the msix
+ * entry is masked, it tests the pending bit array for a pending message
+ * and @msix_addr and @msix_data need not be supplied. If the entry is not
+ * masked, it tests the address for corresponding data to see if the interrupt
+ * fired.
+ *
+ * Note that this does not lower the interrupt, however it does clear the
+ * msix message address to 0 if it is found set. This must be called with
+ * the msix address memory containing either 0 or the value of data, otherwise
+ * it will assert on incorrect message.
+ */
+bool qpci_msix_test_interrupt(QPCIDevice *dev, uint32_t msix_entry,
+ uint64_t msix_addr, uint32_t msix_data)
+{
+ uint32_t data;
+
+ g_assert(dev->msix_enabled);
+ g_assert_cmpint(msix_entry, !=, -1);
+
+ if (qpci_msix_masked(dev, msix_entry)) {
+ /* No ISR checking should be done if masked, but read anyway */
+ return qpci_msix_pending(dev, msix_entry);
+ }
+
+ /*
+ * 0 is used as the "not fired" sentinel — callers must program a
+ * non-zero MSI-X data value so the pre-zeroed target memory can be
+ * polled reliably.
+ */
+ g_assert_cmpint(msix_addr, !=, 0);
+ g_assert_cmpint(msix_data, !=, 0);
+
+ /* msix payload is written in little-endian format */
+ qtest_memread(dev->bus->qts, msix_addr, &data, 4);
+ data = le32_to_cpu(data);
+ if (data == 0) {
+ return false;
+ }
+
+ /* got a message, ensure it matches expected value then clear it. */
+ g_assert_cmphex(data, ==, msix_data);
+ qtest_memset(dev->bus->qts, msix_addr, 0, 4);
+
+ return true;
+}
+
uint16_t qpci_msix_table_size(QPCIDevice *dev)
{
uint8_t addr;
diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h
index 83896145..9f8f154c 100644
--- a/tests/qtest/libqos/pci.h
+++ b/tests/qtest/libqos/pci.h
@@ -92,6 +92,8 @@ void qpci_msix_enable(QPCIDevice *dev);
void qpci_msix_disable(QPCIDevice *dev);
bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry);
bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry);
+bool qpci_msix_test_interrupt(QPCIDevice *dev, uint32_t msix_entry,
+ uint64_t msix_addr, uint32_t msix_data);
uint16_t qpci_msix_table_size(QPCIDevice *dev);
uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset);
diff --git a/tests/qtest/libqos/virtio-pci-modern.c b/tests/qtest/libqos/virtio-pci-modern.c
index 5dae41e6..0d7d89bb 100644
--- a/tests/qtest/libqos/virtio-pci-modern.c
+++ b/tests/qtest/libqos/virtio-pci-modern.c
@@ -126,28 +126,6 @@ static void set_status(QVirtioDevice *d, uint8_t status)
status);
}
-static bool get_msix_status(QVirtioPCIDevice *dev, uint32_t msix_entry,
- uint32_t msix_addr, uint32_t msix_data)
-{
- uint32_t data;
-
- g_assert_cmpint(msix_entry, !=, -1);
- if (qpci_msix_masked(dev->pdev, msix_entry)) {
- /* No ISR checking should be done if masked, but read anyway */
- return qpci_msix_pending(dev->pdev, msix_entry);
- }
-
- qtest_memread(dev->pdev->bus->qts, msix_addr, &data, 4);
- data = le32_to_cpu(data);
- if (data == 0) {
- return false;
- }
- /* got a message, ensure it matches expected value then clear it. */
- g_assert_cmphex(data, ==, msix_data);
- qtest_writel(dev->pdev->bus->qts, msix_addr, 0);
- return true;
-}
-
static bool get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
@@ -155,8 +133,8 @@ static bool get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
if (dev->pdev->msix_enabled) {
QVirtQueuePCI *vqpci = container_of(vq, QVirtQueuePCI, vq);
- return get_msix_status(dev, vqpci->msix_entry, vqpci->msix_addr,
- vqpci->msix_data);
+ return qpci_msix_test_interrupt(dev->pdev, vqpci->msix_entry,
+ vqpci->msix_addr, vqpci->msix_data);
}
return qpci_io_readb(dev->pdev, dev->bar, dev->isr_cfg_offset) & 1;
@@ -167,8 +145,9 @@ static bool get_config_isr_status(QVirtioDevice *d)
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
if (dev->pdev->msix_enabled) {
- return get_msix_status(dev, dev->config_msix_entry,
- dev->config_msix_addr, dev->config_msix_data);
+ return qpci_msix_test_interrupt(dev->pdev, dev->config_msix_entry,
+ dev->config_msix_addr,
+ dev->config_msix_data);
}
return qpci_io_readb(dev->pdev, dev->bar, dev->isr_cfg_offset) & 2;
diff --git a/tests/qtest/libqos/virtio-pci.c b/tests/qtest/libqos/virtio-pci.c
index 76ea1f45..ea8114e2 100644
--- a/tests/qtest/libqos/virtio-pci.c
+++ b/tests/qtest/libqos/virtio-pci.c
@@ -122,25 +122,12 @@ static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status)
static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
- QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
- uint32_t data;
if (dev->pdev->msix_enabled) {
- g_assert_cmpint(vqpci->msix_entry, !=, -1);
- if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
- /* No ISR checking should be done if masked, but read anyway */
- return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
- } else {
- qtest_memread(dev->pdev->bus->qts, vqpci->msix_addr, &data, 4);
- data = le32_to_cpu(data);
- if (data == 0) {
- return false;
- }
- /* got a message, ensure it matches expected value then clear it. */
- g_assert_cmphex(data, ==, vqpci->msix_data);
- qtest_writel(dev->pdev->bus->qts, vqpci->msix_addr, 0);
- return true;
- }
+ QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
+
+ return qpci_msix_test_interrupt(dev->pdev, vqpci->msix_entry,
+ vqpci->msix_addr, vqpci->msix_data);
} else {
return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 1;
}
@@ -149,24 +136,11 @@ static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
{
QVirtioPCIDevice *dev = container_of(d, QVirtioPCIDevice, vdev);
- uint32_t data;
if (dev->pdev->msix_enabled) {
- g_assert_cmpint(dev->config_msix_entry, !=, -1);
- if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
- /* No ISR checking should be done if masked, but read anyway */
- return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
- } else {
- qtest_memread(dev->pdev->bus->qts, dev->config_msix_addr, &data, 4);
- data = le32_to_cpu(data);
- if (data == 0) {
- return false;
- }
- /* got a message, ensure it matches expected value then clear it. */
- g_assert_cmphex(data, ==, dev->config_msix_data);
- qtest_writel(dev->pdev->bus->qts, dev->config_msix_addr, 0);
- return true;
- }
+ return qpci_msix_test_interrupt(dev->pdev, dev->config_msix_entry,
+ dev->config_msix_addr,
+ dev->config_msix_data);
} else {
return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 2;
}
--
2.55.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 04/10] tests/qtest: Enable spapr dma with linear iommu map
2026-08-17 18:55 [PATCH v6 00/10] tests/qtest: pci and MSI-X fixes Jishnu Warrier
` (2 preceding siblings ...)
2026-08-17 18:55 ` [PATCH v6 03/10] tests/qtest: Add libqos function for testing msix interrupt status Jishnu Warrier
@ 2026-08-17 18:55 ` Jishnu Warrier
2026-08-18 19:50 ` Fabiano Rosas
2026-08-17 18:55 ` [PATCH v6 05/10] tests/qtest/ahci: unmap pci bar before reusing device Jishnu Warrier
` (4 subsequent siblings)
8 siblings, 1 reply; 11+ messages in thread
From: Jishnu Warrier @ 2026-08-17 18:55 UTC (permalink / raw)
To: qemu-devel
Cc: npiggin, philmd, farosas, akihiko.odaki, mst, marcel.apfelbaum,
david, adityag, harshpb, amachhiw
From: Nicholas Piggin <npiggin@gmail.com>
qtests spapr dma was broken because the iommu was not set up.
spapr requires hypercalls to set up the iommu (TCE tables), but
there is no support for that or a side-channel to the iommu in
qtests at the moment, so add a quick workaround in QEMU to have
the spapr iommu provide a linear map to memory when running
qtests.
The buggy msix checks can all be removed since the tests all work
now.
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_iommu.c | 10 +++++++++-
tests/qtest/e1000e-test.c | 21 ---------------------
tests/qtest/igb-test.c | 21 ---------------------
tests/qtest/libqos/generic-pcihost.c | 1 -
tests/qtest/libqos/pci-pc.c | 3 ---
tests/qtest/libqos/pci-spapr.c | 7 ++++---
tests/qtest/libqos/pci.c | 14 --------------
tests/qtest/libqos/pci.h | 4 ----
tests/qtest/nvme-test.c | 4 ----
tests/qtest/vhost-user-blk-test.c | 6 ------
tests/qtest/virtio-blk-test.c | 12 ------------
11 files changed, 13 insertions(+), 90 deletions(-)
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
index e6264b07..5470602e 100644
--- a/hw/ppc/spapr_iommu.c
+++ b/hw/ppc/spapr_iommu.c
@@ -22,6 +22,8 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "system/kvm.h"
+#include "system/qtest.h"
+#include "exec/target_page.h"
#include "kvm_ppc.h"
#include "migration/vmstate.h"
#include "system/dma.h"
@@ -125,7 +127,13 @@ static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu,
.perm = IOMMU_NONE,
};
- if ((addr >> tcet->page_shift) < tcet->nb_table) {
+ if (qtest_enabled()) {
+ /* spapr qtests does not set up the IOMMU, shortcut a linear map */
+ ret.iova = addr & TARGET_PAGE_MASK;
+ ret.translated_addr = addr & TARGET_PAGE_MASK;
+ ret.addr_mask = ~TARGET_PAGE_MASK;
+ ret.perm = IOMMU_RW;
+ } else if ((addr >> tcet->page_shift) < tcet->nb_table) {
/* Check if we are in bound */
hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c
index de9738fd..8300bf5a 100644
--- a/tests/qtest/e1000e-test.c
+++ b/tests/qtest/e1000e-test.c
@@ -139,13 +139,6 @@ static void test_e1000e_tx(void *obj, void *data, QGuestAllocator * alloc)
{
QE1000E_PCI *e1000e = obj;
QE1000E *d = &e1000e->e1000e;
- QOSGraphObject *e_object = obj;
- QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
-
- /* FIXME: add spapr support */
- if (qpci_check_buggy_msi(dev)) {
- return;
- }
e1000e_send_verify(d, data, alloc);
}
@@ -154,13 +147,6 @@ static void test_e1000e_rx(void *obj, void *data, QGuestAllocator * alloc)
{
QE1000E_PCI *e1000e = obj;
QE1000E *d = &e1000e->e1000e;
- QOSGraphObject *e_object = obj;
- QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
-
- /* FIXME: add spapr support */
- if (qpci_check_buggy_msi(dev)) {
- return;
- }
e1000e_receive_verify(d, data, alloc);
}
@@ -173,13 +159,6 @@ static void test_e1000e_multiple_transfers(void *obj, void *data,
QE1000E_PCI *e1000e = obj;
QE1000E *d = &e1000e->e1000e;
- QOSGraphObject *e_object = obj;
- QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
-
- /* FIXME: add spapr support */
- if (qpci_check_buggy_msi(dev)) {
- return;
- }
for (i = 0; i < iterations; i++) {
e1000e_send_verify(d, data, alloc);
diff --git a/tests/qtest/igb-test.c b/tests/qtest/igb-test.c
index 3d397ea6..1b3b5aa6 100644
--- a/tests/qtest/igb-test.c
+++ b/tests/qtest/igb-test.c
@@ -142,13 +142,6 @@ static void test_igb_tx(void *obj, void *data, QGuestAllocator * alloc)
{
QE1000E_PCI *e1000e = obj;
QE1000E *d = &e1000e->e1000e;
- QOSGraphObject *e_object = obj;
- QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
-
- /* FIXME: add spapr support */
- if (qpci_check_buggy_msi(dev)) {
- return;
- }
igb_send_verify(d, data, alloc);
}
@@ -157,13 +150,6 @@ static void test_igb_rx(void *obj, void *data, QGuestAllocator * alloc)
{
QE1000E_PCI *e1000e = obj;
QE1000E *d = &e1000e->e1000e;
- QOSGraphObject *e_object = obj;
- QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
-
- /* FIXME: add spapr support */
- if (qpci_check_buggy_msi(dev)) {
- return;
- }
igb_receive_verify(d, data, alloc);
}
@@ -176,13 +162,6 @@ static void test_igb_multiple_transfers(void *obj, void *data,
QE1000E_PCI *e1000e = obj;
QE1000E *d = &e1000e->e1000e;
- QOSGraphObject *e_object = obj;
- QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
-
- /* FIXME: add spapr support */
- if (qpci_check_buggy_msi(dev)) {
- return;
- }
for (i = 0; i < iterations; i++) {
igb_send_verify(d, data, alloc);
diff --git a/tests/qtest/libqos/generic-pcihost.c b/tests/qtest/libqos/generic-pcihost.c
index b7761752..93cc3b85 100644
--- a/tests/qtest/libqos/generic-pcihost.c
+++ b/tests/qtest/libqos/generic-pcihost.c
@@ -182,7 +182,6 @@ void qpci_init_generic(QGenericPCIBus *qpci, QTestState *qts,
qpci->gpex_pio_base = 0x3eff0000;
qpci->bus.not_hotpluggable = !hotpluggable;
- qpci->bus.has_buggy_msi = false;
qpci->bus.pio_readb = qpci_generic_pio_readb;
qpci->bus.pio_readw = qpci_generic_pio_readw;
diff --git a/tests/qtest/libqos/pci-pc.c b/tests/qtest/libqos/pci-pc.c
index 147009f4..8b79d858 100644
--- a/tests/qtest/libqos/pci-pc.c
+++ b/tests/qtest/libqos/pci-pc.c
@@ -124,9 +124,6 @@ void qpci_init_pc(QPCIBusPC *qpci, QTestState *qts, QGuestAllocator *alloc)
{
assert(qts);
- /* tests can use pci-bus */
- qpci->bus.has_buggy_msi = false;
-
qpci->bus.pio_readb = qpci_pc_pio_readb;
qpci->bus.pio_readw = qpci_pc_pio_readw;
qpci->bus.pio_readl = qpci_pc_pio_readl;
diff --git a/tests/qtest/libqos/pci-spapr.c b/tests/qtest/libqos/pci-spapr.c
index 3723cbb3..b58cc1b5 100644
--- a/tests/qtest/libqos/pci-spapr.c
+++ b/tests/qtest/libqos/pci-spapr.c
@@ -20,6 +20,10 @@
* PCI devices are always little-endian
* SPAPR by default is big-endian
* so PCI accessors need to swap data endianness
+ *
+ * The spapr iommu model has a qtest_enabled() check that short-cuts
+ * the TCE table and provides a linear map for DMA, since qtests does
+ * not have a way to make hcalls to set up the TCE table.
*/
static uint8_t qpci_spapr_pio_readb(QPCIBus *bus, uint32_t addr)
@@ -155,9 +159,6 @@ void qpci_init_spapr(QPCIBusSPAPR *qpci, QTestState *qts,
{
assert(qts);
- /* tests cannot use spapr, needs to be fixed first */
- qpci->bus.has_buggy_msi = true;
-
qpci->alloc = alloc;
qpci->bus.pio_readb = qpci_spapr_pio_readb;
diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c
index 986ce31d..76b13ade 100644
--- a/tests/qtest/libqos/pci.c
+++ b/tests/qtest/libqos/pci.c
@@ -53,20 +53,6 @@ void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
}
}
-bool qpci_has_buggy_msi(QPCIDevice *dev)
-{
- return dev->bus->has_buggy_msi;
-}
-
-bool qpci_check_buggy_msi(QPCIDevice *dev)
-{
- if (qpci_has_buggy_msi(dev)) {
- g_test_skip("Skipping due to incomplete support for MSI");
- return true;
- }
- return false;
-}
-
static void qpci_device_set(QPCIDevice *dev, QPCIBus *bus, int devfn)
{
g_assert(dev);
diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h
index 9f8f154c..ef40a691 100644
--- a/tests/qtest/libqos/pci.h
+++ b/tests/qtest/libqos/pci.h
@@ -51,7 +51,6 @@ struct QPCIBus {
QTestState *qts;
uint64_t pio_alloc_ptr, pio_limit;
uint64_t mmio_alloc_ptr, mmio_limit;
- bool has_buggy_msi; /* TRUE for spapr, FALSE for pci */
bool not_hotpluggable; /* TRUE if devices cannot be hotplugged */
};
@@ -83,9 +82,6 @@ QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn);
void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr);
int qpci_secondary_buses_init(QPCIBus *bus);
-bool qpci_has_buggy_msi(QPCIDevice *dev);
-bool qpci_check_buggy_msi(QPCIDevice *dev);
-
void qpci_device_enable(QPCIDevice *dev);
uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id, uint8_t start_addr);
void qpci_msix_enable(QPCIDevice *dev);
diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c
index f9395cc2..388011be 100644
--- a/tests/qtest/nvme-test.c
+++ b/tests/qtest/nvme-test.c
@@ -492,10 +492,6 @@ static void test_migrate(void *obj, void *data, QGuestAllocator *alloc)
{ 333, false }
};
- if (qpci_check_buggy_msi(pdev)) {
- return;
- }
-
/* create temporary dir and prepare unix socket path for migration */
tmpfs = g_dir_make_tmp("nvme-test-XXXXXX", &err);
if (!tmpfs) {
diff --git a/tests/qtest/vhost-user-blk-test.c b/tests/qtest/vhost-user-blk-test.c
index ea90d412..3e71fdb9 100644
--- a/tests/qtest/vhost-user-blk-test.c
+++ b/tests/qtest/vhost-user-blk-test.c
@@ -554,14 +554,8 @@ static void idx(void *obj, void *u_data, QGuestAllocator *t_alloc)
uint32_t desc_idx;
uint8_t status;
char *data;
- QOSGraphObject *blk_object = obj;
- QPCIDevice *pci_dev = blk_object->get_driver(blk_object, "pci-device");
QTestState *qts = global_qtest;
- if (qpci_check_buggy_msi(pci_dev)) {
- return;
- }
-
qpci_msix_enable(pdev->pdev);
qvirtio_pci_set_msix_configuration_vector(pdev, t_alloc, 0);
diff --git a/tests/qtest/virtio-blk-test.c b/tests/qtest/virtio-blk-test.c
index 98c906eb..3a005d60 100644
--- a/tests/qtest/virtio-blk-test.c
+++ b/tests/qtest/virtio-blk-test.c
@@ -474,14 +474,8 @@ static void msix(void *obj, void *u_data, QGuestAllocator *t_alloc)
uint32_t free_head;
uint8_t status;
char *data;
- QOSGraphObject *blk_object = obj;
- QPCIDevice *pci_dev = blk_object->get_driver(blk_object, "pci-device");
QTestState *qts = global_qtest;
- if (qpci_check_buggy_msi(pci_dev)) {
- return;
- }
-
qpci_msix_enable(pdev->pdev);
qvirtio_pci_set_msix_configuration_vector(pdev, t_alloc, 0);
@@ -584,14 +578,8 @@ static void idx(void *obj, void *u_data, QGuestAllocator *t_alloc)
uint32_t desc_idx;
uint8_t status;
char *data;
- QOSGraphObject *blk_object = obj;
- QPCIDevice *pci_dev = blk_object->get_driver(blk_object, "pci-device");
QTestState *qts = global_qtest;
- if (qpci_check_buggy_msi(pci_dev)) {
- return;
- }
-
qpci_msix_enable(pdev->pdev);
qvirtio_pci_set_msix_configuration_vector(pdev, t_alloc, 0);
--
2.55.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v6 04/10] tests/qtest: Enable spapr dma with linear iommu map
2026-08-17 18:55 ` [PATCH v6 04/10] tests/qtest: Enable spapr dma with linear iommu map Jishnu Warrier
@ 2026-08-18 19:50 ` Fabiano Rosas
0 siblings, 0 replies; 11+ messages in thread
From: Fabiano Rosas @ 2026-08-18 19:50 UTC (permalink / raw)
To: Jishnu Warrier, qemu-devel
Cc: npiggin, philmd, akihiko.odaki, mst, marcel.apfelbaum, david,
adityag, harshpb, amachhiw
Jishnu Warrier <jishnuvw@linux.ibm.com> writes:
> From: Nicholas Piggin <npiggin@gmail.com>
>
> qtests spapr dma was broken because the iommu was not set up.
>
> spapr requires hypercalls to set up the iommu (TCE tables), but
> there is no support for that or a side-channel to the iommu in
> qtests at the moment, so add a quick workaround in QEMU to have
> the spapr iommu provide a linear map to memory when running
> qtests.
>
> The buggy msix checks can all be removed since the tests all work
> now.
>
> Reviewed-by: Fabiano Rosas <farosas@suse.de>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> hw/ppc/spapr_iommu.c | 10 +++++++++-
> tests/qtest/e1000e-test.c | 21 ---------------------
> tests/qtest/igb-test.c | 21 ---------------------
> tests/qtest/libqos/generic-pcihost.c | 1 -
> tests/qtest/libqos/pci-pc.c | 3 ---
> tests/qtest/libqos/pci-spapr.c | 7 ++++---
> tests/qtest/libqos/pci.c | 14 --------------
> tests/qtest/libqos/pci.h | 4 ----
> tests/qtest/nvme-test.c | 4 ----
> tests/qtest/vhost-user-blk-test.c | 6 ------
> tests/qtest/virtio-blk-test.c | 12 ------------
> 11 files changed, 13 insertions(+), 90 deletions(-)
>
> diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
> index e6264b07..5470602e 100644
> --- a/hw/ppc/spapr_iommu.c
> +++ b/hw/ppc/spapr_iommu.c
> @@ -22,6 +22,8 @@
> #include "qemu/log.h"
> #include "qemu/module.h"
> #include "system/kvm.h"
> +#include "system/qtest.h"
> +#include "exec/target_page.h"
> #include "kvm_ppc.h"
> #include "migration/vmstate.h"
> #include "system/dma.h"
> @@ -125,7 +127,13 @@ static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu,
> .perm = IOMMU_NONE,
> };
>
> - if ((addr >> tcet->page_shift) < tcet->nb_table) {
> + if (qtest_enabled()) {
> + /* spapr qtests does not set up the IOMMU, shortcut a linear map */
> + ret.iova = addr & TARGET_PAGE_MASK;
> + ret.translated_addr = addr & TARGET_PAGE_MASK;
> + ret.addr_mask = ~TARGET_PAGE_MASK;
> + ret.perm = IOMMU_RW;
> + } else if ((addr >> tcet->page_shift) < tcet->nb_table) {
> /* Check if we are in bound */
> hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
>
> diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c
> index de9738fd..8300bf5a 100644
> --- a/tests/qtest/e1000e-test.c
> +++ b/tests/qtest/e1000e-test.c
> @@ -139,13 +139,6 @@ static void test_e1000e_tx(void *obj, void *data, QGuestAllocator * alloc)
> {
> QE1000E_PCI *e1000e = obj;
> QE1000E *d = &e1000e->e1000e;
> - QOSGraphObject *e_object = obj;
> - QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
> -
> - /* FIXME: add spapr support */
> - if (qpci_check_buggy_msi(dev)) {
> - return;
> - }
>
> e1000e_send_verify(d, data, alloc);
> }
> @@ -154,13 +147,6 @@ static void test_e1000e_rx(void *obj, void *data, QGuestAllocator * alloc)
> {
> QE1000E_PCI *e1000e = obj;
> QE1000E *d = &e1000e->e1000e;
> - QOSGraphObject *e_object = obj;
> - QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
> -
> - /* FIXME: add spapr support */
> - if (qpci_check_buggy_msi(dev)) {
> - return;
> - }
>
> e1000e_receive_verify(d, data, alloc);
> }
> @@ -173,13 +159,6 @@ static void test_e1000e_multiple_transfers(void *obj, void *data,
>
> QE1000E_PCI *e1000e = obj;
> QE1000E *d = &e1000e->e1000e;
> - QOSGraphObject *e_object = obj;
> - QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
> -
> - /* FIXME: add spapr support */
> - if (qpci_check_buggy_msi(dev)) {
> - return;
> - }
>
> for (i = 0; i < iterations; i++) {
> e1000e_send_verify(d, data, alloc);
> diff --git a/tests/qtest/igb-test.c b/tests/qtest/igb-test.c
> index 3d397ea6..1b3b5aa6 100644
> --- a/tests/qtest/igb-test.c
> +++ b/tests/qtest/igb-test.c
> @@ -142,13 +142,6 @@ static void test_igb_tx(void *obj, void *data, QGuestAllocator * alloc)
> {
> QE1000E_PCI *e1000e = obj;
> QE1000E *d = &e1000e->e1000e;
> - QOSGraphObject *e_object = obj;
> - QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
> -
> - /* FIXME: add spapr support */
> - if (qpci_check_buggy_msi(dev)) {
> - return;
> - }
>
> igb_send_verify(d, data, alloc);
> }
> @@ -157,13 +150,6 @@ static void test_igb_rx(void *obj, void *data, QGuestAllocator * alloc)
> {
> QE1000E_PCI *e1000e = obj;
> QE1000E *d = &e1000e->e1000e;
> - QOSGraphObject *e_object = obj;
> - QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
> -
> - /* FIXME: add spapr support */
> - if (qpci_check_buggy_msi(dev)) {
> - return;
> - }
>
> igb_receive_verify(d, data, alloc);
> }
> @@ -176,13 +162,6 @@ static void test_igb_multiple_transfers(void *obj, void *data,
>
> QE1000E_PCI *e1000e = obj;
> QE1000E *d = &e1000e->e1000e;
> - QOSGraphObject *e_object = obj;
> - QPCIDevice *dev = e_object->get_driver(e_object, "pci-device");
> -
> - /* FIXME: add spapr support */
> - if (qpci_check_buggy_msi(dev)) {
> - return;
> - }
>
> for (i = 0; i < iterations; i++) {
> igb_send_verify(d, data, alloc);
> diff --git a/tests/qtest/libqos/generic-pcihost.c b/tests/qtest/libqos/generic-pcihost.c
> index b7761752..93cc3b85 100644
> --- a/tests/qtest/libqos/generic-pcihost.c
> +++ b/tests/qtest/libqos/generic-pcihost.c
> @@ -182,7 +182,6 @@ void qpci_init_generic(QGenericPCIBus *qpci, QTestState *qts,
>
> qpci->gpex_pio_base = 0x3eff0000;
> qpci->bus.not_hotpluggable = !hotpluggable;
> - qpci->bus.has_buggy_msi = false;
>
> qpci->bus.pio_readb = qpci_generic_pio_readb;
> qpci->bus.pio_readw = qpci_generic_pio_readw;
> diff --git a/tests/qtest/libqos/pci-pc.c b/tests/qtest/libqos/pci-pc.c
> index 147009f4..8b79d858 100644
> --- a/tests/qtest/libqos/pci-pc.c
> +++ b/tests/qtest/libqos/pci-pc.c
> @@ -124,9 +124,6 @@ void qpci_init_pc(QPCIBusPC *qpci, QTestState *qts, QGuestAllocator *alloc)
> {
> assert(qts);
>
> - /* tests can use pci-bus */
> - qpci->bus.has_buggy_msi = false;
> -
> qpci->bus.pio_readb = qpci_pc_pio_readb;
> qpci->bus.pio_readw = qpci_pc_pio_readw;
> qpci->bus.pio_readl = qpci_pc_pio_readl;
> diff --git a/tests/qtest/libqos/pci-spapr.c b/tests/qtest/libqos/pci-spapr.c
> index 3723cbb3..b58cc1b5 100644
> --- a/tests/qtest/libqos/pci-spapr.c
> +++ b/tests/qtest/libqos/pci-spapr.c
> @@ -20,6 +20,10 @@
> * PCI devices are always little-endian
> * SPAPR by default is big-endian
> * so PCI accessors need to swap data endianness
> + *
> + * The spapr iommu model has a qtest_enabled() check that short-cuts
> + * the TCE table and provides a linear map for DMA, since qtests does
> + * not have a way to make hcalls to set up the TCE table.
> */
>
> static uint8_t qpci_spapr_pio_readb(QPCIBus *bus, uint32_t addr)
> @@ -155,9 +159,6 @@ void qpci_init_spapr(QPCIBusSPAPR *qpci, QTestState *qts,
> {
> assert(qts);
>
> - /* tests cannot use spapr, needs to be fixed first */
> - qpci->bus.has_buggy_msi = true;
> -
> qpci->alloc = alloc;
>
> qpci->bus.pio_readb = qpci_spapr_pio_readb;
> diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c
> index 986ce31d..76b13ade 100644
> --- a/tests/qtest/libqos/pci.c
> +++ b/tests/qtest/libqos/pci.c
> @@ -53,20 +53,6 @@ void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
> }
> }
>
> -bool qpci_has_buggy_msi(QPCIDevice *dev)
> -{
> - return dev->bus->has_buggy_msi;
> -}
> -
> -bool qpci_check_buggy_msi(QPCIDevice *dev)
> -{
> - if (qpci_has_buggy_msi(dev)) {
> - g_test_skip("Skipping due to incomplete support for MSI");
> - return true;
> - }
> - return false;
> -}
> -
> static void qpci_device_set(QPCIDevice *dev, QPCIBus *bus, int devfn)
> {
> g_assert(dev);
> diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h
> index 9f8f154c..ef40a691 100644
> --- a/tests/qtest/libqos/pci.h
> +++ b/tests/qtest/libqos/pci.h
> @@ -51,7 +51,6 @@ struct QPCIBus {
> QTestState *qts;
> uint64_t pio_alloc_ptr, pio_limit;
> uint64_t mmio_alloc_ptr, mmio_limit;
> - bool has_buggy_msi; /* TRUE for spapr, FALSE for pci */
> bool not_hotpluggable; /* TRUE if devices cannot be hotplugged */
>
> };
> @@ -83,9 +82,6 @@ QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn);
> void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr);
> int qpci_secondary_buses_init(QPCIBus *bus);
>
> -bool qpci_has_buggy_msi(QPCIDevice *dev);
> -bool qpci_check_buggy_msi(QPCIDevice *dev);
> -
> void qpci_device_enable(QPCIDevice *dev);
> uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id, uint8_t start_addr);
> void qpci_msix_enable(QPCIDevice *dev);
> diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c
> index f9395cc2..388011be 100644
> --- a/tests/qtest/nvme-test.c
> +++ b/tests/qtest/nvme-test.c
> @@ -492,10 +492,6 @@ static void test_migrate(void *obj, void *data, QGuestAllocator *alloc)
> { 333, false }
> };
>
> - if (qpci_check_buggy_msi(pdev)) {
> - return;
> - }
> -
The nvme-test now fails with:
# starting QEMU: exec ./qemu-system-ppc64 -qtest
unix:/tmp/qtest-1116322.sock -qtest-log /dev/null -chardev
socket,path=/tmp/qtest-1116322.qmp,id=char0 -object
monitor-qmp,id=qmp0,chardev=char0 -display none -audio none -run-with
exit-with-parent=on -M pseries -drive
id=drv0,if=none,file=null-co://,file.read-zeroes=on,format=raw -object
memory-backend-ram,id=pmr0,share=on,size=16 -device
nvme,addr=04.0,drive=drv0,serial=foo -accel qtest
# nvme_wait_ready: csts 0
# q 0x561957dedaa8 db_idx 1 doorbell 0x1004
# cq 0x561957dedaa8 db_idx 1 cqe 0x100000
# q 0x561957deda78 db_idx 0 doorbell 0x1000
# sq 0x561957deda78 db_idx 0 sqe 0x101000
# nvme_wait_ready: csts 1
# sending req cid 123 no_wait 0
# sq 0x561957deda78 next_sqe 0 sqe 0x101000
# sq 0x561957deda78 commit sqe tail 0
**
ERROR:../tests/qtest/nvme-test.c:281:nvme_wait: assertion failed: (ready)
not ok
/ppc64/pseries/spapr-pci-host-bridge/pci-bus-spapr/pci-bus/nvme/nvme-tests/migrate
- ERROR:../tests/qtest/nvme-test.c:281:nvme_wait: assertion failed: (ready)
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v6 05/10] tests/qtest/ahci: unmap pci bar before reusing device
2026-08-17 18:55 [PATCH v6 00/10] tests/qtest: pci and MSI-X fixes Jishnu Warrier
` (3 preceding siblings ...)
2026-08-17 18:55 ` [PATCH v6 04/10] tests/qtest: Enable spapr dma with linear iommu map Jishnu Warrier
@ 2026-08-17 18:55 ` Jishnu Warrier
2026-08-17 18:55 ` [PATCH v6 06/10] tests/qtest/ahci: don't unmap pci bar if it wasn't mapped Jishnu Warrier
` (3 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Jishnu Warrier @ 2026-08-17 18:55 UTC (permalink / raw)
To: qemu-devel
Cc: npiggin, philmd, farosas, akihiko.odaki, mst, marcel.apfelbaum,
david, adityag, harshpb, amachhiw
From: Nicholas Piggin <npiggin@gmail.com>
ahci-test double-maps the hba bar in the pending_callback test.
Unmap it first, to keep iomaps balanced.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/ahci-test.c | 4 ++++
tests/qtest/libqos/ahci.c | 11 +++++++++++
tests/qtest/libqos/ahci.h | 2 ++
3 files changed, 17 insertions(+)
diff --git a/tests/qtest/ahci-test.c b/tests/qtest/ahci-test.c
index 44799eea..64bbdd49 100644
--- a/tests/qtest/ahci-test.c
+++ b/tests/qtest/ahci-test.c
@@ -198,6 +198,7 @@ static void ahci_shutdown(AHCIQState *ahci)
{
QOSState *qs = ahci->parent;
+ ahci_pci_disable(ahci);
ahci_clean_mem(ahci);
free_ahci_device(ahci->dev);
g_free(ahci);
@@ -1418,6 +1419,7 @@ static void test_reset(void)
CMD_READ_DMA_EXT,
CMD_WRITE_DMA_EXT);
ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
+ stop_ahci_device(ahci);
ahci_clean_mem(ahci);
}
@@ -1484,6 +1486,7 @@ static void test_reset_pending_callback(void)
sleep(1);
/* Start again. */
+ stop_ahci_device(ahci);
ahci_clean_mem(ahci);
ahci_pci_enable(ahci);
ahci_hba_enable(ahci);
@@ -1502,6 +1505,7 @@ static void test_reset_pending_callback(void)
ahci_free(ahci, ptr1);
ahci_free(ahci, ptr2);
+ stop_ahci_device(ahci);
ahci_clean_mem(ahci);
ahci_shutdown(ahci);
diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c
index 0621a6c4..f5859c6e 100644
--- a/tests/qtest/libqos/ahci.c
+++ b/tests/qtest/libqos/ahci.c
@@ -205,6 +205,11 @@ void ahci_pci_enable(AHCIQState *ahci)
}
+void ahci_pci_disable(AHCIQState *ahci)
+{
+ stop_ahci_device(ahci);
+}
+
/**
* Map BAR5/ABAR, and engage the PCI device.
*/
@@ -217,6 +222,12 @@ void start_ahci_device(AHCIQState *ahci)
qpci_device_enable(ahci->dev);
}
+void stop_ahci_device(AHCIQState *ahci)
+{
+ /* Unmap AHCI's ABAR */
+ qpci_iounmap(ahci->dev, ahci->hba_bar);
+}
+
/**
* Test and initialize the AHCI's HBA memory areas.
* Initialize and start any ports with devices attached.
diff --git a/tests/qtest/libqos/ahci.h b/tests/qtest/libqos/ahci.h
index a0487a15..f610bd32 100644
--- a/tests/qtest/libqos/ahci.h
+++ b/tests/qtest/libqos/ahci.h
@@ -574,7 +574,9 @@ void ahci_clean_mem(AHCIQState *ahci);
QPCIDevice *get_ahci_device(QTestState *qts, uint32_t *fingerprint);
void free_ahci_device(QPCIDevice *dev);
void ahci_pci_enable(AHCIQState *ahci);
+void ahci_pci_disable(AHCIQState *ahci);
void start_ahci_device(AHCIQState *ahci);
+void stop_ahci_device(AHCIQState *ahci);
void ahci_hba_enable(AHCIQState *ahci);
/* Port Management */
--
2.55.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 06/10] tests/qtest/ahci: don't unmap pci bar if it wasn't mapped
2026-08-17 18:55 [PATCH v6 00/10] tests/qtest: pci and MSI-X fixes Jishnu Warrier
` (4 preceding siblings ...)
2026-08-17 18:55 ` [PATCH v6 05/10] tests/qtest/ahci: unmap pci bar before reusing device Jishnu Warrier
@ 2026-08-17 18:55 ` Jishnu Warrier
2026-08-17 18:55 ` [PATCH v6 07/10] tests/qtest/libquos/pci: Add migration fixup helper for pci devices Jishnu Warrier
` (2 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Jishnu Warrier @ 2026-08-17 18:55 UTC (permalink / raw)
To: qemu-devel
Cc: npiggin, philmd, farosas, akihiko.odaki, mst, marcel.apfelbaum,
david, adityag, harshpb, amachhiw
From: Nicholas Piggin <npiggin@gmail.com>
ahci-test has a bunch of tests where the pci bar was not mapped. Avoid
unmapping it in these cases, to keep iomaps balanced.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/ahci-test.c | 3 +++
tests/qtest/libqos/ahci.c | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/ahci-test.c b/tests/qtest/ahci-test.c
index 64bbdd49..43b5a38b 100644
--- a/tests/qtest/ahci-test.c
+++ b/tests/qtest/ahci-test.c
@@ -85,6 +85,8 @@ static void verify_state(AHCIQState *ahci, uint64_t hba_old)
uint64_t hba_base;
AHCICommandHeader cmd;
+ g_assert_cmphex(ahci->hba_bar.addr, ==, hba_old);
+
ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID);
g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint);
@@ -1421,6 +1423,7 @@ static void test_reset(void)
ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR);
stop_ahci_device(ahci);
ahci_clean_mem(ahci);
+ start_ahci_device(ahci);
}
ahci_shutdown(ahci);
diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c
index f5859c6e..71d19a44 100644
--- a/tests/qtest/libqos/ahci.c
+++ b/tests/qtest/libqos/ahci.c
@@ -224,7 +224,7 @@ void start_ahci_device(AHCIQState *ahci)
void stop_ahci_device(AHCIQState *ahci)
{
- /* Unmap AHCI's ABAR */
+ /* Unmap AHCI's ABAR (no-op if not mapped) */
qpci_iounmap(ahci->dev, ahci->hba_bar);
}
@@ -249,6 +249,7 @@ void ahci_hba_enable(AHCIQState *ahci)
uint8_t num_cmd_slots;
g_assert(ahci != NULL);
+ g_assert(ahci->hba_bar.mapped);
/* Set GHC.AE to 1 */
ahci_set(ahci, AHCI_GHC, AHCI_GHC_AE);
--
2.55.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 07/10] tests/qtest/libquos/pci: Add migration fixup helper for pci devices
2026-08-17 18:55 [PATCH v6 00/10] tests/qtest: pci and MSI-X fixes Jishnu Warrier
` (5 preceding siblings ...)
2026-08-17 18:55 ` [PATCH v6 06/10] tests/qtest/ahci: don't unmap pci bar if it wasn't mapped Jishnu Warrier
@ 2026-08-17 18:55 ` Jishnu Warrier
2026-08-17 18:55 ` [PATCH v6 08/10] qtest/libqos/pci: Enforce balanced iomap/unmap Jishnu Warrier
2026-08-17 18:55 ` [PATCH v6 09/10] qtest/libqos/pci: Fix qpci_msix_enable sharing bar0 Jishnu Warrier
8 siblings, 0 replies; 11+ messages in thread
From: Jishnu Warrier @ 2026-08-17 18:55 UTC (permalink / raw)
To: qemu-devel
Cc: npiggin, philmd, farosas, akihiko.odaki, mst, marcel.apfelbaum,
david, adityag, harshpb, amachhiw
From: Nicholas Piggin <npiggin@gmail.com>
Migration tests can create new QPCI devices for the destination
machine which may need to take on some state of the source machine
after destination is complete.
Add a migration fixup helper and call it from ahci migration tests.
This is currently a noop and will be used subsequently.
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/ahci-test.c | 1 +
tests/qtest/libqos/pci.c | 4 ++++
tests/qtest/libqos/pci.h | 1 +
3 files changed, 6 insertions(+)
diff --git a/tests/qtest/ahci-test.c b/tests/qtest/ahci-test.c
index 43b5a38b..1c45d5f3 100644
--- a/tests/qtest/ahci-test.c
+++ b/tests/qtest/ahci-test.c
@@ -137,6 +137,7 @@ static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri)
memcpy(to, from, sizeof(AHCIQState));
to->parent = tmp;
to->dev = dev;
+ qpci_migrate_fixup(to->dev, from->dev);
tmp = from->parent;
dev = from->dev;
diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c
index 76b13ade..cda3c56c 100644
--- a/tests/qtest/libqos/pci.c
+++ b/tests/qtest/libqos/pci.c
@@ -625,6 +625,10 @@ QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr)
return bar;
}
+void qpci_migrate_fixup(QPCIDevice *to, QPCIDevice *from)
+{
+}
+
void add_qpci_address(QOSGraphEdgeOptions *opts, QPCIAddress *addr)
{
g_assert(addr);
diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h
index ef40a691..19f1dd13 100644
--- a/tests/qtest/libqos/pci.h
+++ b/tests/qtest/libqos/pci.h
@@ -120,6 +120,7 @@ void qpci_memwrite(QPCIDevice *bus, QPCIBar token, uint64_t off,
const void *buf, size_t len);
QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr);
void qpci_iounmap(QPCIDevice *dev, QPCIBar addr);
+void qpci_migrate_fixup(QPCIDevice *to, QPCIDevice *from);
QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr);
void qpci_unplug_acpi_device_test(QTestState *qs, const char *id, uint8_t slot);
--
2.55.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 08/10] qtest/libqos/pci: Enforce balanced iomap/unmap
2026-08-17 18:55 [PATCH v6 00/10] tests/qtest: pci and MSI-X fixes Jishnu Warrier
` (6 preceding siblings ...)
2026-08-17 18:55 ` [PATCH v6 07/10] tests/qtest/libquos/pci: Add migration fixup helper for pci devices Jishnu Warrier
@ 2026-08-17 18:55 ` Jishnu Warrier
2026-08-17 18:55 ` [PATCH v6 09/10] qtest/libqos/pci: Fix qpci_msix_enable sharing bar0 Jishnu Warrier
8 siblings, 0 replies; 11+ messages in thread
From: Jishnu Warrier @ 2026-08-17 18:55 UTC (permalink / raw)
To: qemu-devel
Cc: npiggin, philmd, farosas, akihiko.odaki, mst, marcel.apfelbaum,
david, adityag, harshpb, amachhiw
From: Nicholas Piggin <npiggin@gmail.com>
Add assertions to ensure a BAR is not mapped twice, and that only
previously mapped BARs are unmapped. This can help catch bugs and
fragile coding.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/libqos/pci.c | 75 ++++++++++++++++++++++++++++++++--------
tests/qtest/libqos/pci.h | 10 ++++++
2 files changed, 70 insertions(+), 15 deletions(-)
diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c
index cda3c56c..3d953d23 100644
--- a/tests/qtest/libqos/pci.c
+++ b/tests/qtest/libqos/pci.c
@@ -79,12 +79,17 @@ QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr)
{
uint16_t vendor_id, device_id;
+ int i;
qpci_device_set(dev, bus, addr->devfn);
vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID);
device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
g_assert(!addr->vendor_id || vendor_id == addr->vendor_id);
g_assert(!addr->device_id || device_id == addr->device_id);
+
+ for (i = 0; i < QPCI_NUM_REGIONS; i++) {
+ g_assert(!dev->bars_mapped[i]);
+ }
}
static uint8_t qpci_find_resource_reserve_capability(QPCIDevice *dev)
@@ -338,21 +343,21 @@ bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry)
}
/**
- * qpci_msix_test_interrupt - test whether msix interrupt has been raised
+ * qpci_msix_test_interrupt - test whether MSI-X interrupt has been raised
* @dev: PCI device
- * @msix_entry: msix entry to test
- * @msix_addr: address of msix message
- * @msix_data: expected msix message payload
+ * @msix_entry: MSI-X entry to test
+ * @msix_addr: address of MSI-X message
+ * @msix_data: expected MSI-X message payload
*
- * This tests whether the msix source has raised an interrupt. If the msix
+ * This tests whether the MSI-X source has raised an interrupt. If the MSI-X
* entry is masked, it tests the pending bit array for a pending message
* and @msix_addr and @msix_data need not be supplied. If the entry is not
* masked, it tests the address for corresponding data to see if the interrupt
* fired.
*
* Note that this does not lower the interrupt, however it does clear the
- * msix message address to 0 if it is found set. This must be called with
- * the msix address memory containing either 0 or the value of data, otherwise
+ * MSI-X message address to 0 if it is found set. This must be called with
+ * the MSI-X address memory containing either 0 or the value of data, otherwise
* it will assert on incorrect message.
*/
bool qpci_msix_test_interrupt(QPCIDevice *dev, uint32_t msix_entry,
@@ -376,8 +381,8 @@ bool qpci_msix_test_interrupt(QPCIDevice *dev, uint32_t msix_entry,
g_assert_cmpint(msix_addr, !=, 0);
g_assert_cmpint(msix_data, !=, 0);
- /* msix payload is written in little-endian format */
- qtest_memread(dev->bus->qts, msix_addr, &data, 4);
+ /* MSI-X payload is written in little-endian format */
+ qtest_memread(dev->bus->qts, msix_addr, &data, sizeof(data));
data = le32_to_cpu(data);
if (data == 0) {
return false;
@@ -385,7 +390,7 @@ bool qpci_msix_test_interrupt(QPCIDevice *dev, uint32_t msix_entry,
/* got a message, ensure it matches expected value then clear it. */
g_assert_cmphex(data, ==, msix_data);
- qtest_memset(dev->bus->qts, msix_addr, 0, 4);
+ qtest_memset(dev->bus->qts, msix_addr, 0, sizeof(data));
return true;
}
@@ -554,21 +559,31 @@ void qpci_memwrite(QPCIDevice *dev, QPCIBar token, uint64_t off,
dev->bus->memwrite(dev->bus, token.addr + off, buf, len);
}
-QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
+static uint8_t qpci_bar_reg(int barno)
{
- QPCIBus *bus = dev->bus;
static const int bar_reg_map[] = {
PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
};
+
+ g_assert(barno >= 0 && barno < QPCI_NUM_REGIONS);
+
+ return bar_reg_map[barno];
+}
+
+QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
+{
+ QPCIBus *bus = dev->bus;
QPCIBar bar;
int bar_reg;
uint32_t addr, size;
uint32_t io_type;
uint64_t loc;
- g_assert(barno >= 0 && barno <= 5);
- bar_reg = bar_reg_map[barno];
+ g_assert(barno >= 0 && barno < QPCI_NUM_REGIONS);
+ g_assert(!dev->bars_mapped[barno]);
+
+ bar_reg = qpci_bar_reg(barno);
qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
addr = qpci_config_readl(dev, bar_reg);
@@ -611,12 +626,38 @@ QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
}
bar.addr = loc;
+ bar.mapped = true;
+
+ dev->bars_mapped[barno] = true;
+ dev->bars[barno] = bar;
+
return bar;
}
void qpci_iounmap(QPCIDevice *dev, QPCIBar bar)
{
- /* FIXME */
+ int bar_reg;
+ int i;
+
+ if (!bar.mapped) {
+ return; /* bar was never mapped; no-op */
+ }
+
+ for (i = 0; i < QPCI_NUM_REGIONS; i++) {
+ if (!dev->bars_mapped[i]) {
+ continue;
+ }
+ if (dev->bars[i].addr == bar.addr) {
+ dev->bars_mapped[i] = false;
+ dev->bars[i].mapped = false;
+ bar_reg = qpci_bar_reg(i);
+ qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
+ /* FIXME: the address space is leaked */
+ return;
+ }
+ }
+ /* bar was not iomap()ed; treat as no-op for callers that may
+ * call iounmap unconditionally during cleanup paths. */
}
QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr)
@@ -627,6 +668,10 @@ QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr)
void qpci_migrate_fixup(QPCIDevice *to, QPCIDevice *from)
{
+ memcpy(to->bars_mapped, from->bars_mapped, sizeof(from->bars_mapped));
+ memset(from->bars_mapped, 0, sizeof(from->bars_mapped));
+ memcpy(to->bars, from->bars, sizeof(from->bars));
+ memset(from->bars, 0, sizeof(from->bars));
}
void add_qpci_address(QOSGraphEdgeOptions *opts, QPCIAddress *addr)
diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h
index 19f1dd13..73739afe 100644
--- a/tests/qtest/libqos/pci.h
+++ b/tests/qtest/libqos/pci.h
@@ -58,12 +58,22 @@ struct QPCIBus {
struct QPCIBar {
uint64_t addr;
bool is_io;
+ bool mapped;
};
+/*
+ * hw/pci permits 7 (PCI_NUM_REGIONS) regions, the last for PCI_ROM_SLOT.
+ * libqos does not implement PCI_ROM_SLOT at the moment, and as such it
+ * permits 6.
+ */
+#define QPCI_NUM_REGIONS 6
+
struct QPCIDevice
{
QPCIBus *bus;
int devfn;
+ bool bars_mapped[QPCI_NUM_REGIONS];
+ QPCIBar bars[QPCI_NUM_REGIONS];
bool msix_enabled;
QPCIBar msix_table_bar, msix_pba_bar;
uint64_t msix_table_off, msix_pba_off;
--
2.55.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v6 09/10] qtest/libqos/pci: Fix qpci_msix_enable sharing bar0
2026-08-17 18:55 [PATCH v6 00/10] tests/qtest: pci and MSI-X fixes Jishnu Warrier
` (7 preceding siblings ...)
2026-08-17 18:55 ` [PATCH v6 08/10] qtest/libqos/pci: Enforce balanced iomap/unmap Jishnu Warrier
@ 2026-08-17 18:55 ` Jishnu Warrier
8 siblings, 0 replies; 11+ messages in thread
From: Jishnu Warrier @ 2026-08-17 18:55 UTC (permalink / raw)
To: qemu-devel
Cc: npiggin, philmd, farosas, akihiko.odaki, mst, marcel.apfelbaum,
david, adityag, harshpb, amachhiw
From: Nicholas Piggin <npiggin@gmail.com>
Devices where the MSI-X addresses are shared with other MMIO on BAR0
can not use msi_enable because it unmaps and remaps BAR0, which
interferes with device MMIO mappings. xhci-nec is one such device we
would like to test with msix.
Use the BAR iomap tracking structure introduced in the previous change
to have qpci_misx_enable() use existing iomaps if msix bars are
already mapped.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/libqos/pci.c | 40 ++++++++++++++++++++++++++++++++++------
tests/qtest/libqos/pci.h | 1 +
2 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c
index 3d953d23..19fd991c 100644
--- a/tests/qtest/libqos/pci.c
+++ b/tests/qtest/libqos/pci.c
@@ -274,15 +274,21 @@ void qpci_msix_enable(QPCIDevice *dev)
table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE);
bir_table = table & PCI_MSIX_FLAGS_BIRMASK;
- dev->msix_table_bar = qpci_iomap(dev, bir_table, NULL);
+ if (dev->bars_mapped[bir_table]) {
+ dev->msix_table_bar = dev->bars[bir_table];
+ } else {
+ dev->msix_table_bar_iomap = true;
+ dev->msix_table_bar = qpci_iomap(dev, bir_table, NULL);
+ }
dev->msix_table_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
table = qpci_config_readl(dev, addr + PCI_MSIX_PBA);
bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
- if (bir_pba != bir_table) {
- dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL);
+ if (dev->bars_mapped[bir_pba]) {
+ dev->msix_pba_bar = dev->bars[bir_pba];
} else {
- dev->msix_pba_bar = dev->msix_table_bar;
+ dev->msix_pba_bar_iomap = true;
+ dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL);
}
dev->msix_pba_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
@@ -293,6 +299,7 @@ void qpci_msix_disable(QPCIDevice *dev)
{
uint8_t addr;
uint16_t val;
+ uint32_t table;
g_assert(dev->msix_enabled);
addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0);
@@ -301,10 +308,31 @@ void qpci_msix_disable(QPCIDevice *dev)
qpci_config_writew(dev, addr + PCI_MSIX_FLAGS,
val & ~PCI_MSIX_FLAGS_ENABLE);
- if (dev->msix_pba_bar.addr != dev->msix_table_bar.addr) {
+ if (dev->msix_pba_bar_iomap) {
+ dev->msix_pba_bar_iomap = false;
qpci_iounmap(dev, dev->msix_pba_bar);
+ } else {
+ /*
+ * If we had reused an existing iomap, ensure it is still mapped
+ * otherwise it would be a bug if it were unmapped before msix is
+ * disabled. A refcounting iomap implementation could avoid this
+ * issue entirely, but let's wait until that's needed.
+ */
+ uint8_t bir_pba;
+ table = qpci_config_readl(dev, addr + PCI_MSIX_PBA);
+ bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
+ g_assert(dev->bars_mapped[bir_pba]);
+ }
+
+ if (dev->msix_table_bar_iomap) {
+ dev->msix_table_bar_iomap = false;
+ qpci_iounmap(dev, dev->msix_table_bar);
+ } else {
+ uint8_t bir_table;
+ table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE);
+ bir_table = table & PCI_MSIX_FLAGS_BIRMASK;
+ g_assert(dev->bars_mapped[bir_table]);
}
- qpci_iounmap(dev, dev->msix_table_bar);
dev->msix_enabled = 0;
dev->msix_table_off = 0;
diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h
index 73739afe..3f256241 100644
--- a/tests/qtest/libqos/pci.h
+++ b/tests/qtest/libqos/pci.h
@@ -75,6 +75,7 @@ struct QPCIDevice
bool bars_mapped[QPCI_NUM_REGIONS];
QPCIBar bars[QPCI_NUM_REGIONS];
bool msix_enabled;
+ bool msix_table_bar_iomap, msix_pba_bar_iomap;
QPCIBar msix_table_bar, msix_pba_bar;
uint64_t msix_table_off, msix_pba_off;
};
--
2.55.0
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