* [PATCH 1/2] drm/i915/display: Move port clock calculation
@ 2024-05-15 6:45 Mika Kahola
2024-05-15 6:45 ` [PATCH 2/2] drm/i915/display: Remove .clock from pll state structure Mika Kahola
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Mika Kahola @ 2024-05-15 6:45 UTC (permalink / raw)
To: intel-gfx; +Cc: imre.deak, Mika Kahola
As a preparation to remove .clock member from pll state
structure, let's move the port clock calculation on better
location
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 176 ++++++++++---------
1 file changed, 91 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1b1ebafa49e8..9f860a05e623 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1970,13 +1970,92 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
NULL,
};
-static int intel_c10_phy_check_hdmi_link_rate(int clock)
+static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c10pll_state *pll_state)
+{
+ unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
+ unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
+ int tmpclk = 0;
+
+ if (pll_state->pll[0] & C10_PLL0_FRACEN) {
+ frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
+ frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
+ frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
+ }
+
+ multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
+ pll_state->pll[2]) / 2 + 16;
+
+ tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
+ hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
+
+ tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
+ DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
+ 10 << (tx_clk_div + 16));
+ tmpclk *= (hdmi_div ? 2 : 1);
+
+ return tmpclk;
+}
+
+static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
+{
+ return state->tx[0] & C20_PHY_USE_MPLLB;
+}
+
+static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c20pll_state *pll_state)
+{
+ unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
+ unsigned int multiplier, refclk = 38400;
+ unsigned int tx_clk_div;
+ unsigned int ref_clk_mpllb_div;
+ unsigned int fb_clk_div4_en;
+ unsigned int ref, vco;
+ unsigned int tx_rate_mult;
+ unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
+
+ if (intel_c20phy_use_mpllb(pll_state)) {
+ tx_rate_mult = 1;
+ frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
+ frac_quot = pll_state->mpllb[8];
+ frac_rem = pll_state->mpllb[9];
+ frac_den = pll_state->mpllb[7];
+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
+ tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
+ fb_clk_div4_en = 0;
+ } else {
+ tx_rate_mult = 2;
+ frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
+ frac_quot = pll_state->mplla[8];
+ frac_rem = pll_state->mplla[9];
+ frac_den = pll_state->mplla[7];
+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
+ tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
+ fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
+ }
+
+ if (frac_en)
+ frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
+ else
+ frac = 0;
+
+ ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
+ vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
+
+ return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
+}
+
+static int intel_c10_phy_check_hdmi_link_rate(struct intel_encoder *encoder,
+ int clock)
{
const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
int i;
for (i = 0; tables[i]; i++) {
- if (clock == tables[i]->clock)
+ int port_clock = intel_c10pll_calc_port_clock(encoder, tables[i]);
+ if (clock == port_clock)
return MODE_OK;
}
@@ -2035,7 +2114,8 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
return -EINVAL;
for (i = 0; tables[i]; i++) {
- if (crtc_state->port_clock == tables[i]->clock) {
+ int port_clock = intel_c10pll_calc_port_clock(encoder, tables[i]);
+ if (crtc_state->port_clock == port_clock) {
crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i];
intel_c10pll_update_pll(crtc_state, encoder);
@@ -2209,13 +2289,15 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
return 0;
}
-static int intel_c20_phy_check_hdmi_link_rate(int clock)
+static int intel_c20_phy_check_hdmi_link_rate(struct intel_encoder *encoder,
+ int clock)
{
const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
int i;
for (i = 0; tables[i]; i++) {
- if (clock == tables[i]->clock)
+ int port_clock = intel_c20pll_calc_port_clock(encoder, tables[i]);
+ if (clock == port_clock)
return MODE_OK;
}
@@ -2230,8 +2312,8 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
if (intel_encoder_is_c10phy(&dig_port->base))
- return intel_c10_phy_check_hdmi_link_rate(clock);
- return intel_c20_phy_check_hdmi_link_rate(clock);
+ return intel_c10_phy_check_hdmi_link_rate(hdmi->attached_connector->encoder, clock);
+ return intel_c20_phy_check_hdmi_link_rate(hdmi->attached_connector->encoder, clock);
}
static const struct intel_c20pll_state * const *
@@ -2275,7 +2357,8 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
return -EINVAL;
for (i = 0; tables[i]; i++) {
- if (crtc_state->port_clock == tables[i]->clock) {
+ int port_clock = intel_c20pll_calc_port_clock(encoder, tables[i]);
+ if (crtc_state->port_clock == port_clock) {
crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
return 0;
}
@@ -2292,56 +2375,6 @@ int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
return intel_c20pll_calc_state(crtc_state, encoder);
}
-static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
-{
- return state->tx[0] & C20_PHY_USE_MPLLB;
-}
-
-static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
- const struct intel_c20pll_state *pll_state)
-{
- unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
- unsigned int multiplier, refclk = 38400;
- unsigned int tx_clk_div;
- unsigned int ref_clk_mpllb_div;
- unsigned int fb_clk_div4_en;
- unsigned int ref, vco;
- unsigned int tx_rate_mult;
- unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
-
- if (intel_c20phy_use_mpllb(pll_state)) {
- tx_rate_mult = 1;
- frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
- frac_quot = pll_state->mpllb[8];
- frac_rem = pll_state->mpllb[9];
- frac_den = pll_state->mpllb[7];
- multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
- tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
- ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
- fb_clk_div4_en = 0;
- } else {
- tx_rate_mult = 2;
- frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
- frac_quot = pll_state->mplla[8];
- frac_rem = pll_state->mplla[9];
- frac_den = pll_state->mplla[7];
- multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
- tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
- ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
- fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
- }
-
- if (frac_en)
- frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
- else
- frac = 0;
-
- ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
- vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
-
- return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
-}
-
static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_c20pll_state *pll_state)
{
@@ -2636,33 +2669,6 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
}
-static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
- const struct intel_c10pll_state *pll_state)
-{
- unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
- unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
- int tmpclk = 0;
-
- if (pll_state->pll[0] & C10_PLL0_FRACEN) {
- frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
- frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
- frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
- }
-
- multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
- pll_state->pll[2]) / 2 + 16;
-
- tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
- hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
-
- tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
- DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
- 10 << (tx_clk_div + 16));
- tmpclk *= (hdmi_div ? 2 : 1);
-
- return tmpclk;
-}
-
static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
bool lane_reversal)
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/2] drm/i915/display: Remove .clock from pll state structure
2024-05-15 6:45 [PATCH 1/2] drm/i915/display: Move port clock calculation Mika Kahola
@ 2024-05-15 6:45 ` Mika Kahola
2024-05-15 13:28 ` Gustavo Sousa
2024-05-15 7:36 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display: Move port clock calculation Patchwork
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Mika Kahola @ 2024-05-15 6:45 UTC (permalink / raw)
To: intel-gfx; +Cc: imre.deak, Mika Kahola
.clock is not necessarily required to have in pll state
structure as it can always recalculated with the *_calc_port_clock()
function. Hence, let's remove this struct member complitely.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 86 -------------------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 -
2 files changed, 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 9f860a05e623..abb937368284 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -505,7 +505,6 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
*/
static const struct intel_c10pll_state mtl_c10_dp_rbr = {
- .clock = 162000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0xB4,
@@ -531,7 +530,6 @@ static const struct intel_c10pll_state mtl_c10_dp_rbr = {
};
static const struct intel_c10pll_state mtl_c10_edp_r216 = {
- .clock = 216000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0x4,
@@ -557,7 +555,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r216 = {
};
static const struct intel_c10pll_state mtl_c10_edp_r243 = {
- .clock = 243000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0x34,
@@ -583,7 +580,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r243 = {
};
static const struct intel_c10pll_state mtl_c10_dp_hbr1 = {
- .clock = 270000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0xF4,
@@ -609,7 +605,6 @@ static const struct intel_c10pll_state mtl_c10_dp_hbr1 = {
};
static const struct intel_c10pll_state mtl_c10_edp_r324 = {
- .clock = 324000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0xB4,
@@ -635,7 +630,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r324 = {
};
static const struct intel_c10pll_state mtl_c10_edp_r432 = {
- .clock = 432000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0x4,
@@ -661,7 +655,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r432 = {
};
static const struct intel_c10pll_state mtl_c10_dp_hbr2 = {
- .clock = 540000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0xF4,
@@ -687,7 +680,6 @@ static const struct intel_c10pll_state mtl_c10_dp_hbr2 = {
};
static const struct intel_c10pll_state mtl_c10_edp_r675 = {
- .clock = 675000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0xB4,
@@ -713,7 +705,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r675 = {
};
static const struct intel_c10pll_state mtl_c10_dp_hbr3 = {
- .clock = 810000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0x34,
@@ -761,7 +752,6 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
/* C20 basic DP 1.4 tables */
static const struct intel_c20pll_state mtl_c20_dp_rbr = {
- .clock = 162000,
.tx = { 0xbe88, /* tx cfg0 */
0x5800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -786,7 +776,6 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr = {
};
static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
- .clock = 270000,
.tx = { 0xbe88, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -811,7 +800,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
};
static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
- .clock = 540000,
.tx = { 0xbe88, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -836,7 +824,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
};
static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
- .clock = 810000,
.tx = { 0xbe88, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -862,7 +849,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
/* C20 basic DP 2.0 tables */
static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
- .clock = 1000000, /* 10 Gbps */
.tx = { 0xbe21, /* tx cfg0 */
0xe800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -886,7 +872,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
};
static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
- .clock = 1350000, /* 13.5 Gbps */
.tx = { 0xbea0, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -911,7 +896,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
};
static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
- .clock = 2000000, /* 20 Gbps */
.tx = { 0xbe20, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -950,7 +934,6 @@ static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
*/
static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
- .clock = 216000,
.tx = { 0xbe88,
0x4800,
0x0000,
@@ -975,7 +958,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
};
static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
- .clock = 243000,
.tx = { 0xbe88,
0x4800,
0x0000,
@@ -1000,7 +982,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
};
static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
- .clock = 324000,
.tx = { 0xbe88,
0x4800,
0x0000,
@@ -1025,7 +1006,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
};
static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
- .clock = 432000,
.tx = { 0xbe88,
0x4800,
0x0000,
@@ -1050,7 +1030,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
};
static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = {
- .clock = 675000,
.tx = { 0xbe88,
0x4800,
0x0000,
@@ -1088,7 +1067,6 @@ static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = {
};
static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
- .clock = 1350000, /* 13.5 Gbps */
.tx = { 0xbea0, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1127,7 +1105,6 @@ static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = {
*/
static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
- .clock = 25200,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x4,
@@ -1153,7 +1130,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
- .clock = 27000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34,
@@ -1179,7 +1155,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
- .clock = 74250,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4,
@@ -1205,7 +1180,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
- .clock = 148500,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4,
@@ -1231,7 +1205,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
- .clock = 594000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4,
@@ -1258,7 +1231,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
/* Precomputed C10 HDMI PLL tables */
static const struct intel_c10pll_state mtl_c10_hdmi_27027 = {
- .clock = 27027,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1268,7 +1240,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_27027 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_28320 = {
- .clock = 28320,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1278,7 +1249,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_28320 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_30240 = {
- .clock = 30240,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1288,7 +1258,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_30240 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_31500 = {
- .clock = 31500,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1298,7 +1267,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_31500 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_36000 = {
- .clock = 36000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1308,7 +1276,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_36000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_40000 = {
- .clock = 40000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1318,7 +1285,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_40000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_49500 = {
- .clock = 49500,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1328,7 +1294,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_49500 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_50000 = {
- .clock = 50000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1338,7 +1303,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_50000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_57284 = {
- .clock = 57284,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1348,7 +1312,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_57284 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_58000 = {
- .clock = 58000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1358,7 +1321,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_58000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_65000 = {
- .clock = 65000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1368,7 +1330,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_65000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_71000 = {
- .clock = 71000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1378,7 +1339,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_71000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_74176 = {
- .clock = 74176,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1388,7 +1348,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_74176 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_75000 = {
- .clock = 75000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1398,7 +1357,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_75000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_78750 = {
- .clock = 78750,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1408,7 +1366,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_78750 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_85500 = {
- .clock = 85500,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1418,7 +1375,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_85500 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_88750 = {
- .clock = 88750,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1428,7 +1384,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_88750 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_106500 = {
- .clock = 106500,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1438,7 +1393,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_106500 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_108000 = {
- .clock = 108000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1448,7 +1402,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_108000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_115500 = {
- .clock = 115500,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1458,7 +1411,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_115500 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_119000 = {
- .clock = 119000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1468,7 +1420,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_119000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_135000 = {
- .clock = 135000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1478,7 +1429,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_135000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_138500 = {
- .clock = 138500,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1488,7 +1438,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_138500 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_147160 = {
- .clock = 147160,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1498,7 +1447,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_147160 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_148352 = {
- .clock = 148352,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1508,7 +1456,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_148352 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_154000 = {
- .clock = 154000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1518,7 +1465,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_154000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_162000 = {
- .clock = 162000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1528,7 +1474,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_162000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_167000 = {
- .clock = 167000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1538,7 +1483,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_167000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_197802 = {
- .clock = 197802,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1548,7 +1492,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_197802 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_198000 = {
- .clock = 198000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1558,7 +1501,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_198000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_209800 = {
- .clock = 209800,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1568,7 +1510,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_209800 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_241500 = {
- .clock = 241500,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1578,7 +1519,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_241500 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_262750 = {
- .clock = 262750,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1588,7 +1528,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_262750 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_268500 = {
- .clock = 268500,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1598,7 +1537,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_268500 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_296703 = {
- .clock = 296703,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1608,7 +1546,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_296703 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_297000 = {
- .clock = 297000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1618,7 +1555,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_297000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_319750 = {
- .clock = 319750,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1628,7 +1564,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_319750 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_497750 = {
- .clock = 497750,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1638,7 +1573,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_497750 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_592000 = {
- .clock = 592000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1648,7 +1582,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_592000 = {
};
static const struct intel_c10pll_state mtl_c10_hdmi_593407 = {
- .clock = 593407,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
@@ -1707,7 +1640,6 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
};
static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
- .clock = 25175,
.tx = { 0xbe88, /* tx cfg0 */
0x9800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1732,7 +1664,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
};
static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
- .clock = 27000,
.tx = { 0xbe88, /* tx cfg0 */
0x9800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1757,7 +1688,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
};
static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
- .clock = 74250,
.tx = { 0xbe88, /* tx cfg0 */
0x9800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1782,7 +1712,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
};
static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
- .clock = 148500,
.tx = { 0xbe88, /* tx cfg0 */
0x9800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1807,7 +1736,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
};
static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
- .clock = 594000,
.tx = { 0xbe88, /* tx cfg0 */
0x9800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1832,7 +1760,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
};
static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
- .clock = 3000000,
.tx = { 0xbe98, /* tx cfg0 */
0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1857,7 +1784,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
};
static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
- .clock = 6000000,
.tx = { 0xbe98, /* tx cfg0 */
0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1882,7 +1808,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
};
static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
- .clock = 8000000,
.tx = { 0xbe98, /* tx cfg0 */
0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1907,7 +1832,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
};
static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
- .clock = 10000000,
.tx = { 0xbe98, /* tx cfg0 */
0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1932,7 +1856,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
};
static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
- .clock = 12000000,
.tx = { 0xbe98, /* tx cfg0 */
0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -2259,7 +2182,6 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
else
mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
- pll_state->clock = pixel_clock;
pll_state->tx[0] = 0xbe88;
pll_state->tx[1] = 0x9800;
pll_state->tx[2] = 0x0000;
@@ -2438,8 +2360,6 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
}
}
- pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);
-
intel_cx0_phy_transaction_end(encoder, wakeref);
}
@@ -3299,14 +3219,8 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20;
bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);
bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);
- int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);
int i;
- I915_STATE_WARN(i915, mpll_hw_state->clock != clock,
- "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)",
- crtc->base.base.id, crtc->base.name,
- mpll_sw_state->clock, mpll_hw_state->clock);
-
I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb,
"[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",
crtc->base.base.id, crtc->base.name,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index f09e513ce05b..fedc5e41460c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -242,14 +242,12 @@ struct intel_mpllb_state {
};
struct intel_c10pll_state {
- u32 clock; /* in KHz */
u8 tx;
u8 cmn;
u8 pll[20];
};
struct intel_c20pll_state {
- u32 clock; /* in kHz */
u16 tx[3];
u16 cmn[4];
union {
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display: Move port clock calculation
2024-05-15 6:45 [PATCH 1/2] drm/i915/display: Move port clock calculation Mika Kahola
2024-05-15 6:45 ` [PATCH 2/2] drm/i915/display: Remove .clock from pll state structure Mika Kahola
@ 2024-05-15 7:36 ` Patchwork
2024-05-15 7:36 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2024-05-15 7:36 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Move port clock calculation
URL : https://patchwork.freedesktop.org/series/133640/
State : warning
== Summary ==
Error: dim checkpatch failed
a7f08368e5a3 drm/i915/display: Move port clock calculation
-:107: WARNING:LINE_SPACING: Missing a blank line after declarations
#107: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2058:
+ int port_clock = intel_c10pll_calc_port_clock(encoder, tables[i]);
+ if (clock == port_clock)
-:117: WARNING:LINE_SPACING: Missing a blank line after declarations
#117: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2118:
+ int port_clock = intel_c10pll_calc_port_clock(encoder, tables[i]);
+ if (crtc_state->port_clock == port_clock) {
-:135: WARNING:LINE_SPACING: Missing a blank line after declarations
#135: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2300:
+ int port_clock = intel_c20pll_calc_port_clock(encoder, tables[i]);
+ if (clock == port_clock)
-:156: WARNING:LINE_SPACING: Missing a blank line after declarations
#156: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2361:
+ int port_clock = intel_c20pll_calc_port_clock(encoder, tables[i]);
+ if (crtc_state->port_clock == port_clock) {
total: 0 errors, 4 warnings, 0 checks, 228 lines checked
015f0e910af8 drm/i915/display: Remove .clock from pll state structure
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/display: Move port clock calculation
2024-05-15 6:45 [PATCH 1/2] drm/i915/display: Move port clock calculation Mika Kahola
2024-05-15 6:45 ` [PATCH 2/2] drm/i915/display: Remove .clock from pll state structure Mika Kahola
2024-05-15 7:36 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display: Move port clock calculation Patchwork
@ 2024-05-15 7:36 ` Patchwork
2024-05-15 7:41 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2024-05-15 7:36 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Move port clock calculation
URL : https://patchwork.freedesktop.org/series/133640/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: Move port clock calculation
2024-05-15 6:45 [PATCH 1/2] drm/i915/display: Move port clock calculation Mika Kahola
` (2 preceding siblings ...)
2024-05-15 7:36 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-05-15 7:41 ` Patchwork
2024-05-15 13:23 ` [PATCH 1/2] " Gustavo Sousa
2024-05-15 15:29 ` ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2024-05-15 7:41 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5196 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Move port clock calculation
URL : https://patchwork.freedesktop.org/series/133640/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14764 -> Patchwork_133640v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/index.html
Participating hosts (42 -> 37)
------------------------------
Additional (2): bat-jsl-1 bat-arls-3
Missing (7): fi-bsw-n3050 fi-snb-2520m bat-adlp-6 fi-glk-j4005 fi-cfl-8109u fi-kbl-8809g bat-dg2-11
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_133640v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip@basic-plain-flip@d-dp6:
- {bat-mtlp-9}: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/bat-mtlp-9/igt@kms_flip@basic-plain-flip@d-dp6.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/bat-mtlp-9/igt@kms_flip@basic-plain-flip@d-dp6.html
Known issues
------------
Here are the changes found in Patchwork_133640v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-jsl-1: NOTRUN -> [SKIP][3] ([i915#9318])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-1: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/bat-jsl-1/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- bat-jsl-1: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/bat-jsl-1/igt@gem_lmem_swapping@verify-random.html
* igt@i915_module_load@load:
- bat-arls-3: NOTRUN -> [ABORT][6] ([i915#11041])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/bat-arls-3/igt@i915_module_load@load.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-1: NOTRUN -> [SKIP][7] ([i915#4103]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-jsl-1: NOTRUN -> [SKIP][8] ([i915#3555] / [i915#9886])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/bat-jsl-1/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-1: NOTRUN -> [SKIP][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-jsl-1: NOTRUN -> [SKIP][10] ([i915#3555])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/bat-jsl-1/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- {bat-mtlp-9}: [DMESG-WARN][11] ([i915#11009]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/bat-mtlp-9/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/bat-mtlp-9/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
[i915#10979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10979
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#11041]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11041
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-------------
* Linux: CI_DRM_14764 -> Patchwork_133640v1
CI-20190529: 20190529
CI_DRM_14764: cd3ae03d1d2d6a680b4637e99623166340b4dc9f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7854: 8abb25ffe588020cf0b797d60ad1f3f9e7c0764a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133640v1: cd3ae03d1d2d6a680b4637e99623166340b4dc9f @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/index.html
[-- Attachment #2: Type: text/html, Size: 5895 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] drm/i915/display: Move port clock calculation
2024-05-15 6:45 [PATCH 1/2] drm/i915/display: Move port clock calculation Mika Kahola
` (3 preceding siblings ...)
2024-05-15 7:41 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-05-15 13:23 ` Gustavo Sousa
2024-05-15 13:32 ` Gustavo Sousa
2024-05-16 10:55 ` Kahola, Mika
2024-05-15 15:29 ` ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
5 siblings, 2 replies; 13+ messages in thread
From: Gustavo Sousa @ 2024-05-15 13:23 UTC (permalink / raw)
To: Mika Kahola, intel-gfx; +Cc: imre.deak, Mika Kahola
Quoting Mika Kahola (2024-05-15 03:45:23-03:00)
>As a preparation to remove .clock member from pll state
>structure, let's move the port clock calculation on better
>location
>
>Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 176 ++++++++++---------
> 1 file changed, 91 insertions(+), 85 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index 1b1ebafa49e8..9f860a05e623 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -1970,13 +1970,92 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
> NULL,
> };
>
>-static int intel_c10_phy_check_hdmi_link_rate(int clock)
>+static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
>+ const struct intel_c10pll_state *pll_state)
>+{
>+ unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
>+ unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
>+ int tmpclk = 0;
>+
>+ if (pll_state->pll[0] & C10_PLL0_FRACEN) {
>+ frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
>+ frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
>+ frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
>+ }
>+
>+ multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
>+ pll_state->pll[2]) / 2 + 16;
>+
>+ tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
>+ hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
>+
>+ tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
>+ DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
>+ 10 << (tx_clk_div + 16));
>+ tmpclk *= (hdmi_div ? 2 : 1);
>+
>+ return tmpclk;
>+}
>+
>+static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
>+{
>+ return state->tx[0] & C20_PHY_USE_MPLLB;
>+}
>+
>+static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
While at it, also remove the unused "encoder" parameter?
Also, note that there are legitimate checkpatch issues reported for
this patch, with those addressed:
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>+ const struct intel_c20pll_state *pll_state)
>+{
>+ unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
>+ unsigned int multiplier, refclk = 38400;
>+ unsigned int tx_clk_div;
>+ unsigned int ref_clk_mpllb_div;
>+ unsigned int fb_clk_div4_en;
>+ unsigned int ref, vco;
>+ unsigned int tx_rate_mult;
>+ unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
>+
>+ if (intel_c20phy_use_mpllb(pll_state)) {
>+ tx_rate_mult = 1;
>+ frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
>+ frac_quot = pll_state->mpllb[8];
>+ frac_rem = pll_state->mpllb[9];
>+ frac_den = pll_state->mpllb[7];
>+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
>+ tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
>+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
>+ fb_clk_div4_en = 0;
>+ } else {
>+ tx_rate_mult = 2;
>+ frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
>+ frac_quot = pll_state->mplla[8];
>+ frac_rem = pll_state->mplla[9];
>+ frac_den = pll_state->mplla[7];
>+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
>+ tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
>+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
>+ fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
>+ }
>+
>+ if (frac_en)
>+ frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
>+ else
>+ frac = 0;
>+
>+ ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
>+ vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
>+
>+ return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
>+}
>+
>+static int intel_c10_phy_check_hdmi_link_rate(struct intel_encoder *encoder,
>+ int clock)
> {
> const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
> int i;
>
> for (i = 0; tables[i]; i++) {
>- if (clock == tables[i]->clock)
>+ int port_clock = intel_c10pll_calc_port_clock(encoder, tables[i]);
>+ if (clock == port_clock)
> return MODE_OK;
> }
>
>@@ -2035,7 +2114,8 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
> return -EINVAL;
>
> for (i = 0; tables[i]; i++) {
>- if (crtc_state->port_clock == tables[i]->clock) {
>+ int port_clock = intel_c10pll_calc_port_clock(encoder, tables[i]);
>+ if (crtc_state->port_clock == port_clock) {
> crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i];
> intel_c10pll_update_pll(crtc_state, encoder);
>
>@@ -2209,13 +2289,15 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
> return 0;
> }
>
>-static int intel_c20_phy_check_hdmi_link_rate(int clock)
>+static int intel_c20_phy_check_hdmi_link_rate(struct intel_encoder *encoder,
>+ int clock)
> {
> const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
> int i;
>
> for (i = 0; tables[i]; i++) {
>- if (clock == tables[i]->clock)
>+ int port_clock = intel_c20pll_calc_port_clock(encoder, tables[i]);
>+ if (clock == port_clock)
> return MODE_OK;
> }
>
>@@ -2230,8 +2312,8 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
> struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
>
> if (intel_encoder_is_c10phy(&dig_port->base))
>- return intel_c10_phy_check_hdmi_link_rate(clock);
>- return intel_c20_phy_check_hdmi_link_rate(clock);
>+ return intel_c10_phy_check_hdmi_link_rate(hdmi->attached_connector->encoder, clock);
>+ return intel_c20_phy_check_hdmi_link_rate(hdmi->attached_connector->encoder, clock);
> }
>
> static const struct intel_c20pll_state * const *
>@@ -2275,7 +2357,8 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> return -EINVAL;
>
> for (i = 0; tables[i]; i++) {
>- if (crtc_state->port_clock == tables[i]->clock) {
>+ int port_clock = intel_c20pll_calc_port_clock(encoder, tables[i]);
>+ if (crtc_state->port_clock == port_clock) {
> crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
> return 0;
> }
>@@ -2292,56 +2375,6 @@ int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> return intel_c20pll_calc_state(crtc_state, encoder);
> }
>
>-static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
>-{
>- return state->tx[0] & C20_PHY_USE_MPLLB;
>-}
>-
>-static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
>- const struct intel_c20pll_state *pll_state)
>-{
>- unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
>- unsigned int multiplier, refclk = 38400;
>- unsigned int tx_clk_div;
>- unsigned int ref_clk_mpllb_div;
>- unsigned int fb_clk_div4_en;
>- unsigned int ref, vco;
>- unsigned int tx_rate_mult;
>- unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
>-
>- if (intel_c20phy_use_mpllb(pll_state)) {
>- tx_rate_mult = 1;
>- frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
>- frac_quot = pll_state->mpllb[8];
>- frac_rem = pll_state->mpllb[9];
>- frac_den = pll_state->mpllb[7];
>- multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
>- tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
>- ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
>- fb_clk_div4_en = 0;
>- } else {
>- tx_rate_mult = 2;
>- frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
>- frac_quot = pll_state->mplla[8];
>- frac_rem = pll_state->mplla[9];
>- frac_den = pll_state->mplla[7];
>- multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
>- tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
>- ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
>- fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
>- }
>-
>- if (frac_en)
>- frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
>- else
>- frac = 0;
>-
>- ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
>- vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
>-
>- return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
>-}
>-
> static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> struct intel_c20pll_state *pll_state)
> {
>@@ -2636,33 +2669,6 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
> BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
> }
>
>-static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
>- const struct intel_c10pll_state *pll_state)
>-{
>- unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
>- unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
>- int tmpclk = 0;
>-
>- if (pll_state->pll[0] & C10_PLL0_FRACEN) {
>- frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
>- frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
>- frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
>- }
>-
>- multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
>- pll_state->pll[2]) / 2 + 16;
>-
>- tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
>- hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
>-
>- tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
>- DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
>- 10 << (tx_clk_div + 16));
>- tmpclk *= (hdmi_div ? 2 : 1);
>-
>- return tmpclk;
>-}
>-
> static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> bool lane_reversal)
>--
>2.34.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] drm/i915/display: Remove .clock from pll state structure
2024-05-15 6:45 ` [PATCH 2/2] drm/i915/display: Remove .clock from pll state structure Mika Kahola
@ 2024-05-15 13:28 ` Gustavo Sousa
2024-05-16 8:16 ` Kahola, Mika
0 siblings, 1 reply; 13+ messages in thread
From: Gustavo Sousa @ 2024-05-15 13:28 UTC (permalink / raw)
To: Mika Kahola, intel-gfx; +Cc: imre.deak, Mika Kahola
Quoting Mika Kahola (2024-05-15 03:45:24-03:00)
>.clock is not necessarily required to have in pll state
>structure as it can always recalculated with the *_calc_port_clock()
>function. Hence, let's remove this struct member complitely.
>
>Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 86 -------------------
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 -
> 2 files changed, 88 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index 9f860a05e623..abb937368284 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -505,7 +505,6 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> */
>
> static const struct intel_c10pll_state mtl_c10_dp_rbr = {
>- .clock = 162000,
> .tx = 0x10,
> .cmn = 0x21,
> .pll[0] = 0xB4,
>@@ -531,7 +530,6 @@ static const struct intel_c10pll_state mtl_c10_dp_rbr = {
> };
>
> static const struct intel_c10pll_state mtl_c10_edp_r216 = {
>- .clock = 216000,
> .tx = 0x10,
> .cmn = 0x21,
> .pll[0] = 0x4,
>@@ -557,7 +555,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r216 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_edp_r243 = {
>- .clock = 243000,
> .tx = 0x10,
> .cmn = 0x21,
> .pll[0] = 0x34,
>@@ -583,7 +580,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r243 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_dp_hbr1 = {
>- .clock = 270000,
> .tx = 0x10,
> .cmn = 0x21,
> .pll[0] = 0xF4,
>@@ -609,7 +605,6 @@ static const struct intel_c10pll_state mtl_c10_dp_hbr1 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_edp_r324 = {
>- .clock = 324000,
> .tx = 0x10,
> .cmn = 0x21,
> .pll[0] = 0xB4,
>@@ -635,7 +630,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r324 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_edp_r432 = {
>- .clock = 432000,
> .tx = 0x10,
> .cmn = 0x21,
> .pll[0] = 0x4,
>@@ -661,7 +655,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r432 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_dp_hbr2 = {
>- .clock = 540000,
> .tx = 0x10,
> .cmn = 0x21,
> .pll[0] = 0xF4,
>@@ -687,7 +680,6 @@ static const struct intel_c10pll_state mtl_c10_dp_hbr2 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_edp_r675 = {
>- .clock = 675000,
> .tx = 0x10,
> .cmn = 0x21,
> .pll[0] = 0xB4,
>@@ -713,7 +705,6 @@ static const struct intel_c10pll_state mtl_c10_edp_r675 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_dp_hbr3 = {
>- .clock = 810000,
> .tx = 0x10,
> .cmn = 0x21,
> .pll[0] = 0x34,
>@@ -761,7 +752,6 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
>
> /* C20 basic DP 1.4 tables */
> static const struct intel_c20pll_state mtl_c20_dp_rbr = {
>- .clock = 162000,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x5800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -786,7 +776,6 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> };
>
> static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
>- .clock = 270000,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -811,7 +800,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
>- .clock = 540000,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -836,7 +824,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
>- .clock = 810000,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -862,7 +849,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
>
> /* C20 basic DP 2.0 tables */
> static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
>- .clock = 1000000, /* 10 Gbps */
> .tx = { 0xbe21, /* tx cfg0 */
> 0xe800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -886,7 +872,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
>- .clock = 1350000, /* 13.5 Gbps */
> .tx = { 0xbea0, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -911,7 +896,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
>- .clock = 2000000, /* 20 Gbps */
> .tx = { 0xbe20, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -950,7 +934,6 @@ static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
> */
>
> static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
>- .clock = 216000,
> .tx = { 0xbe88,
> 0x4800,
> 0x0000,
>@@ -975,7 +958,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
> };
>
> static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
>- .clock = 243000,
> .tx = { 0xbe88,
> 0x4800,
> 0x0000,
>@@ -1000,7 +982,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
> };
>
> static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
>- .clock = 324000,
> .tx = { 0xbe88,
> 0x4800,
> 0x0000,
>@@ -1025,7 +1006,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
> };
>
> static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
>- .clock = 432000,
> .tx = { 0xbe88,
> 0x4800,
> 0x0000,
>@@ -1050,7 +1030,6 @@ static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
> };
>
> static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = {
>- .clock = 675000,
> .tx = { 0xbe88,
> 0x4800,
> 0x0000,
>@@ -1088,7 +1067,6 @@ static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = {
> };
>
> static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
>- .clock = 1350000, /* 13.5 Gbps */
> .tx = { 0xbea0, /* tx cfg0 */
> 0x4800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -1127,7 +1105,6 @@ static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = {
> */
>
> static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
>- .clock = 25200,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x4,
>@@ -1153,7 +1130,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
>- .clock = 27000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x34,
>@@ -1179,7 +1155,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
>- .clock = 74250,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4,
>@@ -1205,7 +1180,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
>- .clock = 148500,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4,
>@@ -1231,7 +1205,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
>- .clock = 594000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4,
>@@ -1258,7 +1231,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
>
> /* Precomputed C10 HDMI PLL tables */
> static const struct intel_c10pll_state mtl_c10_hdmi_27027 = {
>- .clock = 27027,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1268,7 +1240,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_27027 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_28320 = {
>- .clock = 28320,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1278,7 +1249,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_28320 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_30240 = {
>- .clock = 30240,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1288,7 +1258,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_30240 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_31500 = {
>- .clock = 31500,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1298,7 +1267,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_31500 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_36000 = {
>- .clock = 36000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1308,7 +1276,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_36000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_40000 = {
>- .clock = 40000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1318,7 +1285,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_40000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_49500 = {
>- .clock = 49500,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1328,7 +1294,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_49500 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_50000 = {
>- .clock = 50000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1338,7 +1303,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_50000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_57284 = {
>- .clock = 57284,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1348,7 +1312,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_57284 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_58000 = {
>- .clock = 58000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1358,7 +1321,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_58000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_65000 = {
>- .clock = 65000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1368,7 +1330,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_65000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_71000 = {
>- .clock = 71000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1378,7 +1339,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_71000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_74176 = {
>- .clock = 74176,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1388,7 +1348,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_74176 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_75000 = {
>- .clock = 75000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1398,7 +1357,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_75000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_78750 = {
>- .clock = 78750,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1408,7 +1366,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_78750 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_85500 = {
>- .clock = 85500,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1418,7 +1375,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_85500 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_88750 = {
>- .clock = 88750,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1428,7 +1384,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_88750 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_106500 = {
>- .clock = 106500,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1438,7 +1393,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_106500 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_108000 = {
>- .clock = 108000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1448,7 +1402,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_108000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_115500 = {
>- .clock = 115500,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1458,7 +1411,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_115500 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_119000 = {
>- .clock = 119000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1468,7 +1420,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_119000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_135000 = {
>- .clock = 135000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1478,7 +1429,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_135000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_138500 = {
>- .clock = 138500,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1488,7 +1438,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_138500 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_147160 = {
>- .clock = 147160,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1498,7 +1447,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_147160 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_148352 = {
>- .clock = 148352,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1508,7 +1456,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_148352 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_154000 = {
>- .clock = 154000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1518,7 +1465,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_154000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_162000 = {
>- .clock = 162000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1528,7 +1474,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_162000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_167000 = {
>- .clock = 167000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1538,7 +1483,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_167000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_197802 = {
>- .clock = 197802,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1548,7 +1492,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_197802 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_198000 = {
>- .clock = 198000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1558,7 +1501,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_198000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_209800 = {
>- .clock = 209800,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1568,7 +1510,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_209800 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_241500 = {
>- .clock = 241500,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1578,7 +1519,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_241500 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_262750 = {
>- .clock = 262750,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1588,7 +1528,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_262750 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_268500 = {
>- .clock = 268500,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1598,7 +1537,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_268500 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_296703 = {
>- .clock = 296703,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1608,7 +1546,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_296703 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_297000 = {
>- .clock = 297000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1618,7 +1555,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_297000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_319750 = {
>- .clock = 319750,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1628,7 +1564,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_319750 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_497750 = {
>- .clock = 497750,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1638,7 +1573,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_497750 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_592000 = {
>- .clock = 592000,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1648,7 +1582,6 @@ static const struct intel_c10pll_state mtl_c10_hdmi_592000 = {
> };
>
> static const struct intel_c10pll_state mtl_c10_hdmi_593407 = {
>- .clock = 593407,
> .tx = 0x10,
> .cmn = 0x1,
> .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
>@@ -1707,7 +1640,6 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
> };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
>- .clock = 25175,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -1732,7 +1664,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
>- .clock = 27000,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -1757,7 +1688,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
>- .clock = 74250,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -1782,7 +1712,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
>- .clock = 148500,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -1807,7 +1736,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
>- .clock = 594000,
> .tx = { 0xbe88, /* tx cfg0 */
> 0x9800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -1832,7 +1760,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
>- .clock = 3000000,
> .tx = { 0xbe98, /* tx cfg0 */
> 0x8800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -1857,7 +1784,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
>- .clock = 6000000,
> .tx = { 0xbe98, /* tx cfg0 */
> 0x8800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -1882,7 +1808,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
>- .clock = 8000000,
> .tx = { 0xbe98, /* tx cfg0 */
> 0x8800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -1907,7 +1832,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
>- .clock = 10000000,
> .tx = { 0xbe98, /* tx cfg0 */
> 0x8800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -1932,7 +1856,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> };
>
> static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
>- .clock = 12000000,
> .tx = { 0xbe98, /* tx cfg0 */
> 0x8800, /* tx cfg1 */
> 0x0000, /* tx cfg2 */
>@@ -2259,7 +2182,6 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
> else
> mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
>
>- pll_state->clock = pixel_clock;
> pll_state->tx[0] = 0xbe88;
> pll_state->tx[1] = 0x9800;
> pll_state->tx[2] = 0x0000;
>@@ -2438,8 +2360,6 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> }
> }
>
>- pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);
>-
> intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
>@@ -3299,14 +3219,8 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
> const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20;
> bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);
> bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);
>- int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);
> int i;
>
>- I915_STATE_WARN(i915, mpll_hw_state->clock != clock,
>- "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)",
>- crtc->base.base.id, crtc->base.name,
>- mpll_sw_state->clock, mpll_hw_state->clock);
>-
Maybe it would be better if we did not remove this check? We could
calculate port clock for mpll_hw_state and keep the check, this could be
done in a separate patch.
--
Gustavo Sousa
> I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb,
> "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",
> crtc->base.base.id, crtc->base.name,
>diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>index f09e513ce05b..fedc5e41460c 100644
>--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>@@ -242,14 +242,12 @@ struct intel_mpllb_state {
> };
>
> struct intel_c10pll_state {
>- u32 clock; /* in KHz */
> u8 tx;
> u8 cmn;
> u8 pll[20];
> };
>
> struct intel_c20pll_state {
>- u32 clock; /* in kHz */
> u16 tx[3];
> u16 cmn[4];
> union {
>--
>2.34.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] drm/i915/display: Move port clock calculation
2024-05-15 13:23 ` [PATCH 1/2] " Gustavo Sousa
@ 2024-05-15 13:32 ` Gustavo Sousa
2024-05-15 13:59 ` Jani Nikula
2024-05-16 10:55 ` Kahola, Mika
1 sibling, 1 reply; 13+ messages in thread
From: Gustavo Sousa @ 2024-05-15 13:32 UTC (permalink / raw)
To: Mika Kahola, intel-gfx; +Cc: imre.deak, Mika Kahola
Quoting Gustavo Sousa (2024-05-15 10:23:54-03:00)
>Quoting Mika Kahola (2024-05-15 03:45:23-03:00)
>>As a preparation to remove .clock member from pll state
>>structure, let's move the port clock calculation on better
>>location
Ah... Also, I noticed that we are not simply moving the implementation
of port calculation functions with this patch. We are also replacing
usage of the "clock" members with function calls. I think the message
subject and body should be reworded.
--
Gustavo Sousa
>>
>>Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>>---
>> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 176 ++++++++++---------
>> 1 file changed, 91 insertions(+), 85 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>index 1b1ebafa49e8..9f860a05e623 100644
>>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>@@ -1970,13 +1970,92 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
>> NULL,
>> };
>>
>>-static int intel_c10_phy_check_hdmi_link_rate(int clock)
>>+static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
>>+ const struct intel_c10pll_state *pll_state)
>>+{
>>+ unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
>>+ unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
>>+ int tmpclk = 0;
>>+
>>+ if (pll_state->pll[0] & C10_PLL0_FRACEN) {
>>+ frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
>>+ frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
>>+ frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
>>+ }
>>+
>>+ multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
>>+ pll_state->pll[2]) / 2 + 16;
>>+
>>+ tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
>>+ hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
>>+
>>+ tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
>>+ DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
>>+ 10 << (tx_clk_div + 16));
>>+ tmpclk *= (hdmi_div ? 2 : 1);
>>+
>>+ return tmpclk;
>>+}
>>+
>>+static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
>>+{
>>+ return state->tx[0] & C20_PHY_USE_MPLLB;
>>+}
>>+
>>+static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
>
>While at it, also remove the unused "encoder" parameter?
>
>Also, note that there are legitimate checkpatch issues reported for
>this patch, with those addressed:
>
> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>
>>+ const struct intel_c20pll_state *pll_state)
>>+{
>>+ unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
>>+ unsigned int multiplier, refclk = 38400;
>>+ unsigned int tx_clk_div;
>>+ unsigned int ref_clk_mpllb_div;
>>+ unsigned int fb_clk_div4_en;
>>+ unsigned int ref, vco;
>>+ unsigned int tx_rate_mult;
>>+ unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
>>+
>>+ if (intel_c20phy_use_mpllb(pll_state)) {
>>+ tx_rate_mult = 1;
>>+ frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
>>+ frac_quot = pll_state->mpllb[8];
>>+ frac_rem = pll_state->mpllb[9];
>>+ frac_den = pll_state->mpllb[7];
>>+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
>>+ tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
>>+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
>>+ fb_clk_div4_en = 0;
>>+ } else {
>>+ tx_rate_mult = 2;
>>+ frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
>>+ frac_quot = pll_state->mplla[8];
>>+ frac_rem = pll_state->mplla[9];
>>+ frac_den = pll_state->mplla[7];
>>+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
>>+ tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
>>+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
>>+ fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
>>+ }
>>+
>>+ if (frac_en)
>>+ frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
>>+ else
>>+ frac = 0;
>>+
>>+ ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
>>+ vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
>>+
>>+ return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
>>+}
>>+
>>+static int intel_c10_phy_check_hdmi_link_rate(struct intel_encoder *encoder,
>>+ int clock)
>> {
>> const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
>> int i;
>>
>> for (i = 0; tables[i]; i++) {
>>- if (clock == tables[i]->clock)
>>+ int port_clock = intel_c10pll_calc_port_clock(encoder, tables[i]);
>>+ if (clock == port_clock)
>> return MODE_OK;
>> }
>>
>>@@ -2035,7 +2114,8 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
>> return -EINVAL;
>>
>> for (i = 0; tables[i]; i++) {
>>- if (crtc_state->port_clock == tables[i]->clock) {
>>+ int port_clock = intel_c10pll_calc_port_clock(encoder, tables[i]);
>>+ if (crtc_state->port_clock == port_clock) {
>> crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i];
>> intel_c10pll_update_pll(crtc_state, encoder);
>>
>>@@ -2209,13 +2289,15 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
>> return 0;
>> }
>>
>>-static int intel_c20_phy_check_hdmi_link_rate(int clock)
>>+static int intel_c20_phy_check_hdmi_link_rate(struct intel_encoder *encoder,
>>+ int clock)
>> {
>> const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
>> int i;
>>
>> for (i = 0; tables[i]; i++) {
>>- if (clock == tables[i]->clock)
>>+ int port_clock = intel_c20pll_calc_port_clock(encoder, tables[i]);
>>+ if (clock == port_clock)
>> return MODE_OK;
>> }
>>
>>@@ -2230,8 +2312,8 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
>> struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
>>
>> if (intel_encoder_is_c10phy(&dig_port->base))
>>- return intel_c10_phy_check_hdmi_link_rate(clock);
>>- return intel_c20_phy_check_hdmi_link_rate(clock);
>>+ return intel_c10_phy_check_hdmi_link_rate(hdmi->attached_connector->encoder, clock);
>>+ return intel_c20_phy_check_hdmi_link_rate(hdmi->attached_connector->encoder, clock);
>> }
>>
>> static const struct intel_c20pll_state * const *
>>@@ -2275,7 +2357,8 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
>> return -EINVAL;
>>
>> for (i = 0; tables[i]; i++) {
>>- if (crtc_state->port_clock == tables[i]->clock) {
>>+ int port_clock = intel_c20pll_calc_port_clock(encoder, tables[i]);
>>+ if (crtc_state->port_clock == port_clock) {
>> crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
>> return 0;
>> }
>>@@ -2292,56 +2375,6 @@ int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
>> return intel_c20pll_calc_state(crtc_state, encoder);
>> }
>>
>>-static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
>>-{
>>- return state->tx[0] & C20_PHY_USE_MPLLB;
>>-}
>>-
>>-static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
>>- const struct intel_c20pll_state *pll_state)
>>-{
>>- unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
>>- unsigned int multiplier, refclk = 38400;
>>- unsigned int tx_clk_div;
>>- unsigned int ref_clk_mpllb_div;
>>- unsigned int fb_clk_div4_en;
>>- unsigned int ref, vco;
>>- unsigned int tx_rate_mult;
>>- unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
>>-
>>- if (intel_c20phy_use_mpllb(pll_state)) {
>>- tx_rate_mult = 1;
>>- frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
>>- frac_quot = pll_state->mpllb[8];
>>- frac_rem = pll_state->mpllb[9];
>>- frac_den = pll_state->mpllb[7];
>>- multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
>>- tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
>>- ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]);
>>- fb_clk_div4_en = 0;
>>- } else {
>>- tx_rate_mult = 2;
>>- frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
>>- frac_quot = pll_state->mplla[8];
>>- frac_rem = pll_state->mplla[9];
>>- frac_den = pll_state->mplla[7];
>>- multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
>>- tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
>>- ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]);
>>- fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]);
>>- }
>>-
>>- if (frac_en)
>>- frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
>>- else
>>- frac = 0;
>>-
>>- ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div);
>>- vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10);
>>-
>>- return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
>>-}
>>-
>> static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
>> struct intel_c20pll_state *pll_state)
>> {
>>@@ -2636,33 +2669,6 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
>> BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
>> }
>>
>>-static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
>>- const struct intel_c10pll_state *pll_state)
>>-{
>>- unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
>>- unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
>>- int tmpclk = 0;
>>-
>>- if (pll_state->pll[0] & C10_PLL0_FRACEN) {
>>- frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
>>- frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
>>- frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
>>- }
>>-
>>- multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
>>- pll_state->pll[2]) / 2 + 16;
>>-
>>- tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
>>- hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
>>-
>>- tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
>>- DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
>>- 10 << (tx_clk_div + 16));
>>- tmpclk *= (hdmi_div ? 2 : 1);
>>-
>>- return tmpclk;
>>-}
>>-
>> static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>> const struct intel_crtc_state *crtc_state,
>> bool lane_reversal)
>>--
>>2.34.1
>>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] drm/i915/display: Move port clock calculation
2024-05-15 13:32 ` Gustavo Sousa
@ 2024-05-15 13:59 ` Jani Nikula
2024-05-15 14:39 ` Gustavo Sousa
0 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2024-05-15 13:59 UTC (permalink / raw)
To: Gustavo Sousa, Mika Kahola, intel-gfx; +Cc: imre.deak, Mika Kahola
On Wed, 15 May 2024, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Quoting Gustavo Sousa (2024-05-15 10:23:54-03:00)
>>Quoting Mika Kahola (2024-05-15 03:45:23-03:00)
>>>As a preparation to remove .clock member from pll state
>>>structure, let's move the port clock calculation on better
>>>location
>
> Ah... Also, I noticed that we are not simply moving the implementation
> of port calculation functions with this patch. We are also replacing
> usage of the "clock" members with function calls. I think the message
> subject and body should be reworded.
No, code movement is one patch, replacing .clock usage with function
calls is another patch, and removing .clock is yet another patch.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] drm/i915/display: Move port clock calculation
2024-05-15 13:59 ` Jani Nikula
@ 2024-05-15 14:39 ` Gustavo Sousa
0 siblings, 0 replies; 13+ messages in thread
From: Gustavo Sousa @ 2024-05-15 14:39 UTC (permalink / raw)
To: Jani Nikula, Mika Kahola, intel-gfx; +Cc: imre.deak, Mika Kahola
Quoting Jani Nikula (2024-05-15 10:59:11-03:00)
>On Wed, 15 May 2024, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> Quoting Gustavo Sousa (2024-05-15 10:23:54-03:00)
>>>Quoting Mika Kahola (2024-05-15 03:45:23-03:00)
>>>>As a preparation to remove .clock member from pll state
>>>>structure, let's move the port clock calculation on better
>>>>location
>>
>> Ah... Also, I noticed that we are not simply moving the implementation
>> of port calculation functions with this patch. We are also replacing
>> usage of the "clock" members with function calls. I think the message
>> subject and body should be reworded.
>
>No, code movement is one patch, replacing .clock usage with function
>calls is another patch, and removing .clock is yet another patch.
Cool. Even better!
--
Gustavo Sousa
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/display: Move port clock calculation
2024-05-15 6:45 [PATCH 1/2] drm/i915/display: Move port clock calculation Mika Kahola
` (4 preceding siblings ...)
2024-05-15 13:23 ` [PATCH 1/2] " Gustavo Sousa
@ 2024-05-15 15:29 ` Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2024-05-15 15:29 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 65458 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Move port clock calculation
URL : https://patchwork.freedesktop.org/series/133640/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14764_full -> Patchwork_133640v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_133640v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_133640v1_full, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_133640v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-tglu-3/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-4/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html
Known issues
------------
Here are the changes found in Patchwork_133640v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@unbind-cold-reset-rebind:
- shard-tglu: NOTRUN -> [SKIP][3] ([i915#11078])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][4] ([i915#8414]) +4 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@drm_fdinfo@most-busy-check-all@bcs0.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-mtlp: NOTRUN -> [SKIP][5] ([i915#3555] / [i915#9323])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-rkl: NOTRUN -> [SKIP][6] ([i915#9323])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_close_race@multigpu-basic-process:
- shard-tglu: NOTRUN -> [SKIP][7] ([i915#7697])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-rkl: NOTRUN -> [SKIP][8] ([i915#7697])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#8555])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#280])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@kms:
- shard-dg2: [PASS][11] -> [INCOMPLETE][12] ([i915#10513] / [i915#1982])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-dg2-6/igt@gem_eio@kms.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-2/igt@gem_eio@kms.html
* igt@gem_eio@reset-stress:
- shard-dg1: NOTRUN -> [FAIL][13] ([i915#5784])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@gem_eio@reset-stress.html
* igt@gem_exec_capture@many-4k-incremental:
- shard-glk: NOTRUN -> [FAIL][14] ([i915#9606]) +1 other test fail
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-glk8/igt@gem_exec_capture@many-4k-incremental.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglu: NOTRUN -> [FAIL][15] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: NOTRUN -> [FAIL][16] ([i915#2842]) +3 other tests fail
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [PASS][17] -> [FAIL][18] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fence@submit3:
- shard-dg1: NOTRUN -> [SKIP][19] ([i915#4812])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@gem_exec_fence@submit3.html
* igt@gem_exec_flush@basic-wb-prw-default:
- shard-dg1: NOTRUN -> [SKIP][20] ([i915#3539] / [i915#4852])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@gem_exec_flush@basic-wb-prw-default.html
* igt@gem_exec_reloc@basic-scanout:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#3281]) +8 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-4/igt@gem_exec_reloc@basic-scanout.html
* igt@gem_exec_reloc@basic-wc-read-active:
- shard-mtlp: NOTRUN -> [SKIP][22] ([i915#3281]) +2 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@gem_exec_reloc@basic-wc-read-active.html
* igt@gem_exec_reloc@basic-write-read:
- shard-dg1: NOTRUN -> [SKIP][23] ([i915#3281]) +2 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@gem_exec_reloc@basic-write-read.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-dg1: NOTRUN -> [SKIP][24] ([i915#4860]) +1 other test skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_huc_copy@huc-copy:
- shard-tglu: NOTRUN -> [SKIP][25] ([i915#2190])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-glk: NOTRUN -> [SKIP][26] ([i915#4613]) +3 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-glk1/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-rkl: NOTRUN -> [SKIP][27] ([i915#4613])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-mtlp: NOTRUN -> [SKIP][28] ([i915#4613])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_lmem_swapping@verify-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][29] ([i915#4565])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@gem_lmem_swapping@verify-ccs@lmem0.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-tglu: NOTRUN -> [SKIP][30] ([i915#4613]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-2/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_mmap@basic-small-bo:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#4083])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@gem_mmap@basic-small-bo.html
* igt@gem_mmap_gtt@basic-wc:
- shard-dg1: NOTRUN -> [SKIP][32] ([i915#4077]) +9 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@gem_mmap_gtt@basic-wc.html
* igt@gem_mmap_gtt@hang:
- shard-mtlp: NOTRUN -> [SKIP][33] ([i915#4077]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@gem_mmap_gtt@hang.html
* igt@gem_partial_pwrite_pread@write-uncached:
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#3282]) +3 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@gem_partial_pwrite_pread@write-uncached.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: NOTRUN -> [SKIP][35] ([i915#3282]) +2 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pread@exhaustion:
- shard-glk: NOTRUN -> [WARN][36] ([i915#2658])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-glk1/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-tglu: NOTRUN -> [WARN][37] ([i915#2658])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@create-valid-protected-context:
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#4270])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-rkl: NOTRUN -> [SKIP][39] ([i915#4270]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-tglu: NOTRUN -> [SKIP][40] ([i915#4270]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][41] ([i915#4270]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_readwrite@new-obj:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#3282]) +2 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@gem_readwrite@new-obj.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#8428]) +1 other test skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-rkl: NOTRUN -> [SKIP][44] ([i915#8411]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_tiled_pread_pwrite:
- shard-dg1: NOTRUN -> [SKIP][45] ([i915#4079]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@gem_tiled_pread_pwrite.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-mtlp: NOTRUN -> [SKIP][46] ([i915#3297])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#3297])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@gem_userptr_blits@unsync-overlap.html
* igt@gen9_exec_parse@batch-without-end:
- shard-mtlp: NOTRUN -> [SKIP][48] ([i915#2856]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@gen9_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@bb-chained:
- shard-tglu: NOTRUN -> [SKIP][49] ([i915#2527] / [i915#2856])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@bb-large:
- shard-rkl: NOTRUN -> [SKIP][50] ([i915#2527])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@gen9_exec_parse@bb-large.html
* igt@gen9_exec_parse@shadow-peek:
- shard-dg1: NOTRUN -> [SKIP][51] ([i915#2527]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: [PASS][52] -> [ABORT][53] ([i915#9820])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-rkl-6/igt@i915_module_load@reload-with-fault-injection.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-reset:
- shard-rkl: NOTRUN -> [SKIP][54] ([i915#8399])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-4/igt@i915_pm_freq_api@freq-reset.html
* igt@i915_pm_rps@basic-api:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#6621])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@thresholds-idle-park@gt0:
- shard-dg1: NOTRUN -> [SKIP][56] ([i915#8925])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@i915_pm_rps@thresholds-idle-park@gt0.html
* igt@i915_selftest@mock@memory_region:
- shard-glk: NOTRUN -> [DMESG-WARN][57] ([i915#9311])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-glk8/igt@i915_selftest@mock@memory_region.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-tglu: NOTRUN -> [INCOMPLETE][58] ([i915#7443])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-2/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#4212])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-tglu: NOTRUN -> [SKIP][60] ([i915#3826])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-4/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-dg1: NOTRUN -> [SKIP][61] ([i915#9531])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#1769] / [i915#3555])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg1: NOTRUN -> [SKIP][63] ([i915#1769] / [i915#3555])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-rkl: NOTRUN -> [SKIP][64] ([i915#5286]) +3 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][65] ([i915#5286]) +2 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][66] ([i915#4538] / [i915#5286])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][67] ([i915#3638])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][68] ([i915#3638]) +1 other test skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][69] +4 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][70] +30 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][71] ([i915#4538]) +1 other test skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-mtlp: NOTRUN -> [SKIP][72] ([i915#6187])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][73] ([i915#6095]) +35 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-c-hdmi-a-4.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#10307] / [i915#10434] / [i915#6095]) +5 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-10/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#10307] / [i915#6095]) +181 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-11/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4.html
* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][76] ([i915#6095]) +19 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs:
- shard-mtlp: NOTRUN -> [SKIP][77] ([i915#10278]) +1 other test skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][78] ([i915#6095]) +47 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#7213] / [i915#9010])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@plane-scaling:
- shard-tglu: NOTRUN -> [SKIP][80] ([i915#3742])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-4/igt@kms_cdclk@plane-scaling.html
* igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][81] ([i915#4087]) +3 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-2/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-dg1: NOTRUN -> [SKIP][82] ([i915#7828]) +3 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
- shard-rkl: NOTRUN -> [SKIP][83] ([i915#7828]) +5 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
- shard-mtlp: NOTRUN -> [SKIP][84] ([i915#7828]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
* igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
- shard-tglu: NOTRUN -> [SKIP][85] ([i915#7828]) +2 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg1: NOTRUN -> [SKIP][86] ([i915#7116] / [i915#9424])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@atomic-dpms@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][87] ([i915#7173])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-11/igt@kms_content_protection@atomic-dpms@pipe-a-dp-4.html
* igt@kms_content_protection@content-type-change:
- shard-rkl: NOTRUN -> [SKIP][88] ([i915#9424])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@legacy:
- shard-tglu: NOTRUN -> [SKIP][89] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424]) +1 other test skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-2/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-0:
- shard-mtlp: NOTRUN -> [SKIP][90] ([i915#6944] / [i915#9424])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_content_protection@lic-type-0.html
- shard-dg2: NOTRUN -> [SKIP][91] ([i915#9424])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-7/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@srm:
- shard-rkl: NOTRUN -> [SKIP][92] ([i915#7118])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][93] ([i915#1339] / [i915#7173])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-rkl: NOTRUN -> [SKIP][94] ([i915#3359])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-mtlp: NOTRUN -> [SKIP][95] ([i915#3359])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-dg1: NOTRUN -> [SKIP][96] ([i915#3555]) +3 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-random-256x85:
- shard-mtlp: NOTRUN -> [SKIP][97] ([i915#8814])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_cursor_crc@cursor-random-256x85.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-tglu: NOTRUN -> [SKIP][98] ([i915#3555]) +2 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-tglu: NOTRUN -> [SKIP][99] ([i915#3359]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#4103])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-rkl: NOTRUN -> [SKIP][101] ([i915#9067])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-rkl: NOTRUN -> [SKIP][102] ([i915#9723])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-4/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#9227])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-11/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-dp-4.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-dg1: NOTRUN -> [SKIP][104] ([i915#9723])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-mtlp: NOTRUN -> [SKIP][105] ([i915#8588])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#3804])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dsc@dsc-basic:
- shard-tglu: NOTRUN -> [SKIP][107] ([i915#3555] / [i915#3840])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg1: NOTRUN -> [SKIP][108] ([i915#3840])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-with-bpc:
- shard-rkl: NOTRUN -> [SKIP][109] ([i915#3555] / [i915#3840])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_fbcon_fbt@psr:
- shard-tglu: NOTRUN -> [SKIP][110] ([i915#3469])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-4/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@chamelium:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#4854])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-4/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-3x:
- shard-tglu: NOTRUN -> [SKIP][112] ([i915#1839])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-2/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@psr1:
- shard-rkl: NOTRUN -> [SKIP][113] ([i915#658])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_feature_discovery@psr1.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-tglu: NOTRUN -> [SKIP][114] ([i915#3637]) +3 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-2/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-mtlp: NOTRUN -> [SKIP][115] ([i915#3637]) +1 other test skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][116] ([i915#8381])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-dg1: NOTRUN -> [SKIP][117] ([i915#9934]) +4 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#2587] / [i915#2672]) +2 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][119] ([i915#8810])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][120] ([i915#2587] / [i915#2672]) +1 other test skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][121] ([i915#2672]) +2 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][122] ([i915#2672] / [i915#3555])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-dg2: [PASS][123] -> [FAIL][124] ([i915#6880]) +1 other test fail
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][125] ([i915#1825]) +31 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][126] ([i915#8708]) +8 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-tglu: NOTRUN -> [SKIP][127] ([i915#5439])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-rkl: NOTRUN -> [SKIP][128] ([i915#9766])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][129] ([i915#3023]) +16 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][130] ([i915#8708])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
- shard-dg1: NOTRUN -> [SKIP][131] ([i915#3458]) +4 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt:
- shard-tglu: NOTRUN -> [SKIP][132] +45 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][133] ([i915#1825]) +4 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_hdr@bpc-switch:
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#3555] / [i915#8228])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-4/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#3555] / [i915#8228]) +2 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-tglu: NOTRUN -> [SKIP][136] ([i915#6301])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-2/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_panel_fitting@legacy:
- shard-dg1: NOTRUN -> [SKIP][137] ([i915#6301])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][138] ([i915#10647]) +1 other test fail
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-glk1/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html
* igt@kms_plane_multiple@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][139] ([i915#3555]) +2 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#6953] / [i915#9423])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-10/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][141] ([i915#9423]) +3 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-a-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#9423]) +3 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-8/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][143] ([i915#9423]) +7 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-3/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][144] ([i915#9423]) +3 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#5235]) +1 other test skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][146] ([i915#5235]) +3 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-a-edp-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#5235] / [i915#9423]) +15 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-10/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][148] ([i915#5235]) +7 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-13/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-3.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-dg1: NOTRUN -> [SKIP][149] ([i915#5354])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#3361])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: NOTRUN -> [SKIP][151] ([i915#4281])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-tglu: NOTRUN -> [SKIP][152] ([i915#8430])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-2/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglu: NOTRUN -> [SKIP][153] ([i915#9519])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-rkl: [PASS][154] -> [SKIP][155] ([i915#9519])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-rkl-3/igt@kms_pm_rpm@dpms-non-lpsp.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-mtlp: NOTRUN -> [SKIP][156] ([i915#9519])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_prime@basic-crc-hybrid:
- shard-tglu: NOTRUN -> [SKIP][157] ([i915#6524])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-4/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-rkl: NOTRUN -> [SKIP][158] ([i915#6524])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-dg1: NOTRUN -> [SKIP][159] +20 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-rkl: NOTRUN -> [SKIP][160] ([i915#9683])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-pr-sprite-render:
- shard-dg1: NOTRUN -> [SKIP][161] ([i915#1072] / [i915#9732]) +10 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@kms_psr@fbc-pr-sprite-render.html
* igt@kms_psr@fbc-psr-sprite-plane-onoff@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][162] ([i915#9688]) +3 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_psr@fbc-psr-sprite-plane-onoff@edp-1.html
* igt@kms_psr@fbc-psr2-no-drrs:
- shard-tglu: NOTRUN -> [SKIP][163] ([i915#9732]) +14 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_psr@fbc-psr2-no-drrs.html
* igt@kms_psr@pr-no-drrs:
- shard-glk: NOTRUN -> [SKIP][164] +181 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-glk1/igt@kms_psr@pr-no-drrs.html
* igt@kms_psr@pr-sprite-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][165] ([i915#1072] / [i915#9732]) +14 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_psr@pr-sprite-mmap-gtt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-rkl: NOTRUN -> [SKIP][166] ([i915#9685])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@exhaust-fences:
- shard-mtlp: NOTRUN -> [SKIP][167] ([i915#4235])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-rkl: NOTRUN -> [SKIP][168] ([i915#5289])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#5289])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: [PASS][170] -> [FAIL][171] ([IGT#2])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-dg2-11/igt@kms_sysfs_edid_timing.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-7/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-tglu: NOTRUN -> [SKIP][172] ([i915#8623]) +1 other test skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-4/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
- shard-tglu: [PASS][173] -> [FAIL][174] ([i915#9196]) +1 other test fail
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#8808] / [i915#9906])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-tglu: NOTRUN -> [SKIP][176] ([i915#2437] / [i915#9412])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-9/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-glk: NOTRUN -> [SKIP][177] ([i915#2437]) +2 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-glk7/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@mi-rpc:
- shard-rkl: NOTRUN -> [SKIP][178] ([i915#2434])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-4/igt@perf@mi-rpc.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#2433])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [PASS][180] -> [FAIL][181] ([i915#4349]) +3 other tests fail
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-10/igt@perf_pmu@busy-double-start@vecs1.html
* igt@perf_pmu@cpu-hotplug:
- shard-tglu: NOTRUN -> [SKIP][182] ([i915#8850])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-2/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@rc6-all-gts:
- shard-tglu: NOTRUN -> [SKIP][183] ([i915#8516]) +1 other test skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-4/igt@perf_pmu@rc6-all-gts.html
* igt@prime_vgem@basic-fence-read:
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#3708])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@prime_vgem@basic-fence-read.html
* igt@v3d/v3d_get_bo_offset@create-get-offsets:
- shard-mtlp: NOTRUN -> [SKIP][185] ([i915#2575]) +2 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@v3d/v3d_get_bo_offset@create-get-offsets.html
* igt@v3d/v3d_submit_csd@bad-multisync-extension:
- shard-dg1: NOTRUN -> [SKIP][186] ([i915#2575]) +5 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@v3d/v3d_submit_csd@bad-multisync-extension.html
* igt@vc4/vc4_label_bo@set-label:
- shard-rkl: NOTRUN -> [SKIP][187] ([i915#7711]) +4 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@vc4/vc4_label_bo@set-label.html
* igt@vc4/vc4_perfmon@get-values-invalid-pointer:
- shard-tglu: NOTRUN -> [SKIP][188] ([i915#2575]) +11 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-2/igt@vc4/vc4_perfmon@get-values-invalid-pointer.html
* igt@vc4/vc4_tiling@get-bad-handle:
- shard-dg1: NOTRUN -> [SKIP][189] ([i915#7711]) +2 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@vc4/vc4_tiling@get-bad-handle.html
* igt@vc4/vc4_wait_bo@bad-bo:
- shard-mtlp: NOTRUN -> [SKIP][190] ([i915#7711]) +1 other test skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-3/igt@vc4/vc4_wait_bo@bad-bo.html
#### Possible fixes ####
* igt@drm_fdinfo@idle@rcs0:
- shard-rkl: [FAIL][191] ([i915#7742]) -> [PASS][192]
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-rkl-4/igt@drm_fdinfo@idle@rcs0.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@drm_fdinfo@idle@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglu: [FAIL][193] ([i915#2842]) -> [PASS][194]
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-tglu-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
- shard-dg2: [FAIL][195] ([i915#10378]) -> [PASS][196]
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-dg2-3/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-1/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [FAIL][197] ([i915#3591]) -> [PASS][198]
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [FAIL][199] ([i915#10031]) -> [PASS][200]
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-rkl-6/igt@i915_suspend@basic-s3-without-i915.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-0:
- shard-tglu: [INCOMPLETE][201] -> [PASS][202]
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-tglu-7/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-tglu-4/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
* igt@kms_cursor_legacy@single-move@pipe-a:
- shard-rkl: [DMESG-WARN][203] ([i915#10166]) -> [PASS][204]
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-rkl-4/igt@kms_cursor_legacy@single-move@pipe-a.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-5/igt@kms_cursor_legacy@single-move@pipe-a.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-rkl: [FAIL][205] -> [PASS][206]
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-rkl-6/igt@kms_fbcon_fbt@fbc-suspend.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1:
- shard-snb: [FAIL][207] ([i915#2122]) -> [PASS][208]
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-snb7/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-snb5/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html
* igt@kms_pm_rpm@dpms-mode-unset-lpsp:
- shard-dg2: [SKIP][209] ([i915#9519]) -> [PASS][210] +1 other test pass
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-dg2-11/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-10/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [SKIP][211] ([i915#9519]) -> [PASS][212]
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
- shard-mtlp: [FAIL][213] ([i915#9196]) -> [PASS][214]
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-mtlp-6/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
* igt@perf_pmu@rc6-suspend:
- shard-rkl: [FAIL][215] ([i915#10864]) -> [PASS][216]
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-rkl-6/igt@perf_pmu@rc6-suspend.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-4/igt@perf_pmu@rc6-suspend.html
#### Warnings ####
* igt@gem_eio@kms:
- shard-dg1: [INCOMPLETE][217] ([i915#10513]) -> [INCOMPLETE][218] ([i915#10513] / [i915#1982])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-dg1-15/igt@gem_eio@kms.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg1-18/igt@gem_eio@kms.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [ABORT][219] ([i915#10131] / [i915#9820]) -> [ABORT][220] ([i915#10131] / [i915#10887] / [i915#9820])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][221] ([i915#4281]) -> [SKIP][222] ([i915#3361])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-rkl-1/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_psr@fbc-psr2-sprite-blt:
- shard-dg2: [SKIP][223] ([i915#1072] / [i915#9732]) -> [SKIP][224] ([i915#1072] / [i915#9673] / [i915#9732]) +15 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-dg2-2/igt@kms_psr@fbc-psr2-sprite-blt.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-11/igt@kms_psr@fbc-psr2-sprite-blt.html
* igt@kms_psr@psr2-cursor-blt:
- shard-dg2: [SKIP][225] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][226] ([i915#1072] / [i915#9732]) +19 other tests skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14764/shard-dg2-11/igt@kms_psr@psr2-cursor-blt.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/shard-dg2-7/igt@kms_psr@psr2-cursor-blt.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[i915#10031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10031
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166
[i915#10278]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10278
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10513]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10513
[i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10864]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10864
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6187
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
[i915#7443]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7443
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8808
[i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8850]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8850
[i915#8925]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8925
[i915#9010]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9010
[i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9227
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
[i915#9606]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9606
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_14764 -> Patchwork_133640v1
CI-20190529: 20190529
CI_DRM_14764: cd3ae03d1d2d6a680b4637e99623166340b4dc9f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7854: 8abb25ffe588020cf0b797d60ad1f3f9e7c0764a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133640v1: cd3ae03d1d2d6a680b4637e99623166340b4dc9f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133640v1/index.html
[-- Attachment #2: Type: text/html, Size: 78873 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 2/2] drm/i915/display: Remove .clock from pll state structure
2024-05-15 13:28 ` Gustavo Sousa
@ 2024-05-16 8:16 ` Kahola, Mika
0 siblings, 0 replies; 13+ messages in thread
From: Kahola, Mika @ 2024-05-16 8:16 UTC (permalink / raw)
To: Sousa, Gustavo, intel-gfx@lists.freedesktop.org; +Cc: Deak, Imre
> -----Original Message-----
> From: Sousa, Gustavo <gustavo.sousa@intel.com>
> Sent: Wednesday, May 15, 2024 4:29 PM
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> Subject: Re: [PATCH 2/2] drm/i915/display: Remove .clock from pll state structure
>
> Quoting Mika Kahola (2024-05-15 03:45:24-03:00)
> >.clock is not necessarily required to have in pll state structure as it
> >can always recalculated with the *_calc_port_clock() function. Hence,
> >let's remove this struct member complitely.
> >
> >Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 86 -------------------
> >drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 2 -
> > 2 files changed, 88 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >index 9f860a05e623..abb937368284 100644
> >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >@@ -505,7 +505,6 @@ void intel_cx0_phy_set_signal_levels(struct
> >intel_encoder *encoder,
> > */
> >
> > static const struct intel_c10pll_state mtl_c10_dp_rbr = {
> >- .clock = 162000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0xB4,
> >@@ -531,7 +530,6 @@ static const struct intel_c10pll_state
> >mtl_c10_dp_rbr = { };
> >
> > static const struct intel_c10pll_state mtl_c10_edp_r216 = {
> >- .clock = 216000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0x4,
> >@@ -557,7 +555,6 @@ static const struct intel_c10pll_state
> >mtl_c10_edp_r216 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_edp_r243 = {
> >- .clock = 243000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0x34,
> >@@ -583,7 +580,6 @@ static const struct intel_c10pll_state
> >mtl_c10_edp_r243 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_dp_hbr1 = {
> >- .clock = 270000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0xF4,
> >@@ -609,7 +605,6 @@ static const struct intel_c10pll_state
> >mtl_c10_dp_hbr1 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_edp_r324 = {
> >- .clock = 324000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0xB4,
> >@@ -635,7 +630,6 @@ static const struct intel_c10pll_state
> >mtl_c10_edp_r324 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_edp_r432 = {
> >- .clock = 432000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0x4,
> >@@ -661,7 +655,6 @@ static const struct intel_c10pll_state
> >mtl_c10_edp_r432 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_dp_hbr2 = {
> >- .clock = 540000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0xF4,
> >@@ -687,7 +680,6 @@ static const struct intel_c10pll_state
> >mtl_c10_dp_hbr2 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_edp_r675 = {
> >- .clock = 675000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0xB4,
> >@@ -713,7 +705,6 @@ static const struct intel_c10pll_state
> >mtl_c10_edp_r675 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_dp_hbr3 = {
> >- .clock = 810000,
> > .tx = 0x10,
> > .cmn = 0x21,
> > .pll[0] = 0x34,
> >@@ -761,7 +752,6 @@ static const struct intel_c10pll_state * const
> >mtl_c10_edp_tables[] = {
> >
> > /* C20 basic DP 1.4 tables */
> > static const struct intel_c20pll_state mtl_c20_dp_rbr = {
> >- .clock = 162000,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x5800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */
> >@@ -786,7 +776,6 @@ static const struct intel_c20pll_state
> >mtl_c20_dp_rbr = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
> >- .clock = 270000,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */
> >@@ -811,7 +800,6 @@ static const struct intel_c20pll_state
> >mtl_c20_dp_hbr1 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
> >- .clock = 540000,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */
> >@@ -836,7 +824,6 @@ static const struct intel_c20pll_state
> >mtl_c20_dp_hbr2 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
> >- .clock = 810000,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */
> >@@ -862,7 +849,6 @@ static const struct intel_c20pll_state
> >mtl_c20_dp_hbr3 = {
> >
> > /* C20 basic DP 2.0 tables */
> > static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
> >- .clock = 1000000, /* 10 Gbps */
> > .tx = { 0xbe21, /* tx cfg0 */
> > 0xe800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */
> >@@ -886,7 +872,6 @@ static const struct intel_c20pll_state
> >mtl_c20_dp_uhbr10 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> >- .clock = 1350000, /* 13.5 Gbps */
> > .tx = { 0xbea0, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */
> >@@ -911,7 +896,6 @@ static const struct intel_c20pll_state
> >mtl_c20_dp_uhbr13_5 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> >- .clock = 2000000, /* 20 Gbps */
> > .tx = { 0xbe20, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */
> >@@ -950,7 +934,6 @@ static const struct intel_c20pll_state * const
> >mtl_c20_dp_tables[] = {
> > */
> >
> > static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
> >- .clock = 216000,
> > .tx = { 0xbe88,
> > 0x4800,
> > 0x0000,
> >@@ -975,7 +958,6 @@ static const struct intel_c20pll_state
> >xe2hpd_c20_edp_r216 = { };
> >
> > static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
> >- .clock = 243000,
> > .tx = { 0xbe88,
> > 0x4800,
> > 0x0000,
> >@@ -1000,7 +982,6 @@ static const struct intel_c20pll_state
> >xe2hpd_c20_edp_r243 = { };
> >
> > static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
> >- .clock = 324000,
> > .tx = { 0xbe88,
> > 0x4800,
> > 0x0000,
> >@@ -1025,7 +1006,6 @@ static const struct intel_c20pll_state
> >xe2hpd_c20_edp_r324 = { };
> >
> > static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
> >- .clock = 432000,
> > .tx = { 0xbe88,
> > 0x4800,
> > 0x0000,
> >@@ -1050,7 +1030,6 @@ static const struct intel_c20pll_state
> >xe2hpd_c20_edp_r432 = { };
> >
> > static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = {
> >- .clock = 675000,
> > .tx = { 0xbe88,
> > 0x4800,
> > 0x0000,
> >@@ -1088,7 +1067,6 @@ static const struct intel_c20pll_state * const
> >xe2hpd_c20_edp_tables[] = { };
> >
> > static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
> >- .clock = 1350000, /* 13.5 Gbps */
> > .tx = { 0xbea0, /* tx cfg0 */
> > 0x4800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */
> >@@ -1127,7 +1105,6 @@ static const struct intel_c20pll_state * const
> >xe2hpd_c20_dp_tables[] = {
> > */
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
> >- .clock = 25200,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x4,
> >@@ -1153,7 +1130,6 @@ static const struct intel_c10pll_state
> >mtl_c10_hdmi_25_2 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
> >- .clock = 27000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x34,
> >@@ -1179,7 +1155,6 @@ static const struct intel_c10pll_state
> >mtl_c10_hdmi_27_0 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
> >- .clock = 74250,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4,
> >@@ -1205,7 +1180,6 @@ static const struct intel_c10pll_state
> >mtl_c10_hdmi_74_25 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
> >- .clock = 148500,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4,
> >@@ -1231,7 +1205,6 @@ static const struct intel_c10pll_state
> >mtl_c10_hdmi_148_5 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
> >- .clock = 594000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4,
> >@@ -1258,7 +1231,6 @@ static const struct intel_c10pll_state
> >mtl_c10_hdmi_594 = {
> >
> > /* Precomputed C10 HDMI PLL tables */
> > static const struct intel_c10pll_state mtl_c10_hdmi_27027 = {
> >- .clock = 27027,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1268,7 +1240,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_27027 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_28320 = {
> >- .clock = 28320,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1278,7 +1249,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_28320 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_30240 = {
> >- .clock = 30240,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1288,7 +1258,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_30240 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_31500 = {
> >- .clock = 31500,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1298,7 +1267,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_31500 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_36000 = {
> >- .clock = 36000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1308,7 +1276,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_36000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_40000 = {
> >- .clock = 40000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1318,7 +1285,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_40000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_49500 = {
> >- .clock = 49500,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1328,7 +1294,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_49500 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_50000 = {
> >- .clock = 50000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1338,7 +1303,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_50000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_57284 = {
> >- .clock = 57284,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1348,7 +1312,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_57284 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_58000 = {
> >- .clock = 58000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1358,7 +1321,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_58000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_65000 = {
> >- .clock = 65000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1368,7 +1330,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_65000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_71000 = {
> >- .clock = 71000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1378,7 +1339,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_71000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_74176 = {
> >- .clock = 74176,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1388,7 +1348,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_74176 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_75000 = {
> >- .clock = 75000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1398,7 +1357,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_75000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_78750 = {
> >- .clock = 78750,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1408,7 +1366,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_78750 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_85500 = {
> >- .clock = 85500,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1418,7 +1375,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_85500 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_88750 = {
> >- .clock = 88750,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1428,7 +1384,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_88750 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_106500 = {
> >- .clock = 106500,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1438,7 +1393,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_106500 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_108000 = {
> >- .clock = 108000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1448,7 +1402,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_108000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_115500 = {
> >- .clock = 115500,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1458,7 +1411,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_115500 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_119000 = {
> >- .clock = 119000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1468,7 +1420,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_119000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_135000 = {
> >- .clock = 135000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1478,7 +1429,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_135000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_138500 = {
> >- .clock = 138500,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1488,7 +1438,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_138500 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_147160 = {
> >- .clock = 147160,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1498,7 +1447,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_147160 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_148352 = {
> >- .clock = 148352,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1508,7 +1456,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_148352 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_154000 = {
> >- .clock = 154000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1518,7 +1465,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_154000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_162000 = {
> >- .clock = 162000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1528,7 +1474,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_162000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_167000 = {
> >- .clock = 167000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1538,7 +1483,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_167000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_197802 = {
> >- .clock = 197802,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1548,7 +1492,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_197802 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_198000 = {
> >- .clock = 198000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1558,7 +1501,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_198000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_209800 = {
> >- .clock = 209800,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1568,7 +1510,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_209800 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_241500 = {
> >- .clock = 241500,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1578,7 +1519,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_241500 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_262750 = {
> >- .clock = 262750,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1588,7 +1528,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_262750 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_268500 = {
> >- .clock = 268500,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1598,7 +1537,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_268500 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_296703 = {
> >- .clock = 296703,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1608,7 +1546,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_296703 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_297000 = {
> >- .clock = 297000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1618,7 +1555,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_297000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_319750 = {
> >- .clock = 319750,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1628,7 +1564,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_319750 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_497750 = {
> >- .clock = 497750,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1638,7 +1573,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_497750 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_592000 = {
> >- .clock = 592000,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1648,7 +1582,6 @@ static const struct
> >intel_c10pll_state mtl_c10_hdmi_592000 = { };
> >
> > static const struct intel_c10pll_state mtl_c10_hdmi_593407 = {
> >- .clock = 593407,
> > .tx = 0x10,
> > .cmn = 0x1,
> > .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] =
> >0x00, .pll[4] = 0x00, @@ -1707,7 +1640,6 @@ static const struct
> >intel_c10pll_state * const mtl_c10_hdmi_tables[] = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
> >- .clock = 25175,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x9800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */ @@ -1732,7 +1664,6 @@ static
> >const struct intel_c20pll_state mtl_c20_hdmi_25_175 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
> >- .clock = 27000,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x9800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */ @@ -1757,7 +1688,6 @@ static
> >const struct intel_c20pll_state mtl_c20_hdmi_27_0 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
> >- .clock = 74250,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x9800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */ @@ -1782,7 +1712,6 @@ static
> >const struct intel_c20pll_state mtl_c20_hdmi_74_25 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
> >- .clock = 148500,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x9800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */ @@ -1807,7 +1736,6 @@ static
> >const struct intel_c20pll_state mtl_c20_hdmi_148_5 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
> >- .clock = 594000,
> > .tx = { 0xbe88, /* tx cfg0 */
> > 0x9800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */ @@ -1832,7 +1760,6 @@ static
> >const struct intel_c20pll_state mtl_c20_hdmi_594 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> >- .clock = 3000000,
> > .tx = { 0xbe98, /* tx cfg0 */
> > 0x8800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */ @@ -1857,7 +1784,6 @@ static
> >const struct intel_c20pll_state mtl_c20_hdmi_300 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> >- .clock = 6000000,
> > .tx = { 0xbe98, /* tx cfg0 */
> > 0x8800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */ @@ -1882,7 +1808,6 @@ static
> >const struct intel_c20pll_state mtl_c20_hdmi_600 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> >- .clock = 8000000,
> > .tx = { 0xbe98, /* tx cfg0 */
> > 0x8800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */ @@ -1907,7 +1832,6 @@ static
> >const struct intel_c20pll_state mtl_c20_hdmi_800 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> >- .clock = 10000000,
> > .tx = { 0xbe98, /* tx cfg0 */
> > 0x8800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */ @@ -1932,7 +1856,6 @@ static
> >const struct intel_c20pll_state mtl_c20_hdmi_1000 = { };
> >
> > static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> >- .clock = 12000000,
> > .tx = { 0xbe98, /* tx cfg0 */
> > 0x8800, /* tx cfg1 */
> > 0x0000, /* tx cfg2 */ @@ -2259,7 +2182,6 @@ static
> >int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
> > else
> > mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
> >
> >- pll_state->clock = pixel_clock;
> > pll_state->tx[0] = 0xbe88;
> > pll_state->tx[1] = 0x9800;
> > pll_state->tx[2] = 0x0000;
> >@@ -2438,8 +2360,6 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> > }
> > }
> >
> >- pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);
> >-
> > intel_cx0_phy_transaction_end(encoder, wakeref); }
> >
> >@@ -3299,14 +3219,8 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
> > const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20;
> > bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);
> > bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);
> >- int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);
> > int i;
> >
> >- I915_STATE_WARN(i915, mpll_hw_state->clock != clock,
> >- "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)",
> >- crtc->base.base.id, crtc->base.name,
> >- mpll_sw_state->clock, mpll_hw_state->clock);
> >-
>
> Maybe it would be better if we did not remove this check? We could calculate port clock for mpll_hw_state and keep the check,
> this could be done in a separate patch.
I decided to remove this check. We are already checking the tx, cmn, and pll values and since we calculate the clock based on these values, I thought that we wouldn't need to recalculate the clock here.
Like Jani pointed out, this part would be better to leave out the patch that removes the .clock member.
-Mika-
>
> --
> Gustavo Sousa
>
> > I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb,
> > "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",
> > crtc->base.base.id, crtc->base.name, diff
> >--git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >index f09e513ce05b..fedc5e41460c 100644
> >--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >@@ -242,14 +242,12 @@ struct intel_mpllb_state { };
> >
> > struct intel_c10pll_state {
> >- u32 clock; /* in KHz */
> > u8 tx;
> > u8 cmn;
> > u8 pll[20];
> > };
> >
> > struct intel_c20pll_state {
> >- u32 clock; /* in kHz */
> > u16 tx[3];
> > u16 cmn[4];
> > union {
> >--
> >2.34.1
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/2] drm/i915/display: Move port clock calculation
2024-05-15 13:23 ` [PATCH 1/2] " Gustavo Sousa
2024-05-15 13:32 ` Gustavo Sousa
@ 2024-05-16 10:55 ` Kahola, Mika
1 sibling, 0 replies; 13+ messages in thread
From: Kahola, Mika @ 2024-05-16 10:55 UTC (permalink / raw)
To: Sousa, Gustavo, intel-gfx@lists.freedesktop.org; +Cc: Deak, Imre
> -----Original Message-----
> From: Sousa, Gustavo <gustavo.sousa@intel.com>
> Sent: Wednesday, May 15, 2024 4:24 PM
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> Subject: Re: [PATCH 1/2] drm/i915/display: Move port clock calculation
>
> Quoting Mika Kahola (2024-05-15 03:45:23-03:00)
> >As a preparation to remove .clock member from pll state structure,
> >let's move the port clock calculation on better location
> >
> >Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 176 ++++++++++---------
> > 1 file changed, 91 insertions(+), 85 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >index 1b1ebafa49e8..9f860a05e623 100644
> >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >@@ -1970,13 +1970,92 @@ static const struct intel_c20pll_state * const
> mtl_c20_hdmi_tables[] = {
> > NULL,
> > };
> >
> >-static int intel_c10_phy_check_hdmi_link_rate(int clock)
> >+static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> >+ const struct
> >+intel_c10pll_state *pll_state) {
> >+ unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> >+ unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
> >+ int tmpclk = 0;
> >+
> >+ if (pll_state->pll[0] & C10_PLL0_FRACEN) {
> >+ frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
> >+ frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
> >+ frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
> >+ }
> >+
> >+ multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state-
> >pll[3]) << 8 |
> >+ pll_state->pll[2]) / 2 + 16;
> >+
> >+ tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state-
> >pll[15]);
> >+ hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK,
> >+ pll_state->pll[15]);
> >+
> >+ tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) +
> frac_quot) +
> >+ DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
> >+ 10 << (tx_clk_div + 16));
> >+ tmpclk *= (hdmi_div ? 2 : 1);
> >+
> >+ return tmpclk;
> >+}
> >+
> >+static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state
> >+*state) {
> >+ return state->tx[0] & C20_PHY_USE_MPLLB; }
> >+
> >+static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
>
> While at it, also remove the unused "encoder" parameter?
>
> Also, note that there are legitimate checkpatch issues reported for this patch, with
> those addressed:
That's true. I will fix the checkpatch issues.
Thanks for the review!
-Mika-
>
> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>
> >+ const struct
> >+intel_c20pll_state *pll_state) {
> >+ unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
> >+ unsigned int multiplier, refclk = 38400;
> >+ unsigned int tx_clk_div;
> >+ unsigned int ref_clk_mpllb_div;
> >+ unsigned int fb_clk_div4_en;
> >+ unsigned int ref, vco;
> >+ unsigned int tx_rate_mult;
> >+ unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE,
> >+pll_state->tx[0]);
> >+
> >+ if (intel_c20phy_use_mpllb(pll_state)) {
> >+ tx_rate_mult = 1;
> >+ frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
> >+ frac_quot = pll_state->mpllb[8];
> >+ frac_rem = pll_state->mpllb[9];
> >+ frac_den = pll_state->mpllb[7];
> >+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state-
> >mpllb[0]);
> >+ tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state-
> >mpllb[0]);
> >+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK,
> pll_state->mpllb[6]);
> >+ fb_clk_div4_en = 0;
> >+ } else {
> >+ tx_rate_mult = 2;
> >+ frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
> >+ frac_quot = pll_state->mplla[8];
> >+ frac_rem = pll_state->mplla[9];
> >+ frac_den = pll_state->mplla[7];
> >+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state-
> >mplla[0]);
> >+ tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state-
> >mplla[1]);
> >+ ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK,
> pll_state->mplla[6]);
> >+ fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state-
> >mplla[0]);
> >+ }
> >+
> >+ if (frac_en)
> >+ frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
> >+ else
> >+ frac = 0;
> >+
> >+ ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 <<
> ref_clk_mpllb_div);
> >+ vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier <<
> >+ (17 - 2)) + frac) >> 17, 10);
> >+
> >+ return vco << tx_rate_mult >> tx_clk_div >> tx_rate; }
> >+
> >+static int intel_c10_phy_check_hdmi_link_rate(struct intel_encoder *encoder,
> >+ int clock)
> > {
> > const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
> > int i;
> >
> > for (i = 0; tables[i]; i++) {
> >- if (clock == tables[i]->clock)
> >+ int port_clock = intel_c10pll_calc_port_clock(encoder, tables[i]);
> >+ if (clock == port_clock)
> > return MODE_OK;
> > }
> >
> >@@ -2035,7 +2114,8 @@ static int intel_c10pll_calc_state(struct intel_crtc_state
> *crtc_state,
> > return -EINVAL;
> >
> > for (i = 0; tables[i]; i++) {
> >- if (crtc_state->port_clock == tables[i]->clock) {
> >+ int port_clock = intel_c10pll_calc_port_clock(encoder, tables[i]);
> >+ if (crtc_state->port_clock == port_clock) {
> > crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i];
> > intel_c10pll_update_pll(crtc_state, encoder);
> >
> >@@ -2209,13 +2289,15 @@ static int intel_c20_compute_hdmi_tmds_pll(u64
> pixel_clock, struct intel_c20pll_
> > return 0;
> > }
> >
> >-static int intel_c20_phy_check_hdmi_link_rate(int clock)
> >+static int intel_c20_phy_check_hdmi_link_rate(struct intel_encoder *encoder,
> >+ int clock)
> > {
> > const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
> > int i;
> >
> > for (i = 0; tables[i]; i++) {
> >- if (clock == tables[i]->clock)
> >+ int port_clock = intel_c20pll_calc_port_clock(encoder, tables[i]);
> >+ if (clock == port_clock)
> > return MODE_OK;
> > }
> >
> >@@ -2230,8 +2312,8 @@ int intel_cx0_phy_check_hdmi_link_rate(struct
> intel_hdmi *hdmi, int clock)
> > struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
> >
> > if (intel_encoder_is_c10phy(&dig_port->base))
> >- return intel_c10_phy_check_hdmi_link_rate(clock);
> >- return intel_c20_phy_check_hdmi_link_rate(clock);
> >+ return intel_c10_phy_check_hdmi_link_rate(hdmi->attached_connector-
> >encoder, clock);
> >+ return
> >+ intel_c20_phy_check_hdmi_link_rate(hdmi->attached_connector->encoder,
> >+ clock);
> > }
> >
> > static const struct intel_c20pll_state * const * @@ -2275,7 +2357,8 @@
> >static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> > return -EINVAL;
> >
> > for (i = 0; tables[i]; i++) {
> >- if (crtc_state->port_clock == tables[i]->clock) {
> >+ int port_clock = intel_c20pll_calc_port_clock(encoder, tables[i]);
> >+ if (crtc_state->port_clock == port_clock) {
> > crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
> > return 0;
> > }
> >@@ -2292,56 +2375,6 @@ int intel_cx0pll_calc_state(struct intel_crtc_state
> *crtc_state,
> > return intel_c20pll_calc_state(crtc_state, encoder); }
> >
> >-static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state
> >*state) -{
> >- return state->tx[0] & C20_PHY_USE_MPLLB;
> >-}
> >-
> >-static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
> >- const struct intel_c20pll_state *pll_state)
> >-{
> >- unsigned int frac, frac_en, frac_quot, frac_rem, frac_den;
> >- unsigned int multiplier, refclk = 38400;
> >- unsigned int tx_clk_div;
> >- unsigned int ref_clk_mpllb_div;
> >- unsigned int fb_clk_div4_en;
> >- unsigned int ref, vco;
> >- unsigned int tx_rate_mult;
> >- unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]);
> >-
> >- if (intel_c20phy_use_mpllb(pll_state)) {
> >- tx_rate_mult = 1;
> >- frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]);
> >- frac_quot = pll_state->mpllb[8];
> >- frac_rem = pll_state->mpllb[9];
> >- frac_den = pll_state->mpllb[7];
> >- multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state-
> >mpllb[0]);
> >- tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state-
> >mpllb[0]);
> >- ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK,
> pll_state->mpllb[6]);
> >- fb_clk_div4_en = 0;
> >- } else {
> >- tx_rate_mult = 2;
> >- frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]);
> >- frac_quot = pll_state->mplla[8];
> >- frac_rem = pll_state->mplla[9];
> >- frac_den = pll_state->mplla[7];
> >- multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state-
> >mplla[0]);
> >- tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state-
> >mplla[1]);
> >- ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK,
> pll_state->mplla[6]);
> >- fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state-
> >mplla[0]);
> >- }
> >-
> >- if (frac_en)
> >- frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den);
> >- else
> >- frac = 0;
> >-
> >- ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 <<
> ref_clk_mpllb_div);
> >- vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) +
> frac) >> 17, 10);
> >-
> >- return vco << tx_rate_mult >> tx_clk_div >> tx_rate;
> >-}
> >-
> > static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> > struct intel_c20pll_state
> >*pll_state) { @@ -2636,33 +2669,6 @@ static void
> >intel_c20_pll_program(struct drm_i915_private *i915,
> > BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); }
> >
> >-static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> >- const struct intel_c10pll_state *pll_state)
> >-{
> >- unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> >- unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
> >- int tmpclk = 0;
> >-
> >- if (pll_state->pll[0] & C10_PLL0_FRACEN) {
> >- frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
> >- frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
> >- frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
> >- }
> >-
> >- multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state-
> >pll[3]) << 8 |
> >- pll_state->pll[2]) / 2 + 16;
> >-
> >- tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state-
> >pll[15]);
> >- hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
> >-
> >- tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) +
> frac_quot) +
> >- DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
> >- 10 << (tx_clk_div + 16));
> >- tmpclk *= (hdmi_div ? 2 : 1);
> >-
> >- return tmpclk;
> >-}
> >-
> > static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state,
> > bool lane_reversal)
> >--
> >2.34.1
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2024-05-16 10:56 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-05-15 6:45 [PATCH 1/2] drm/i915/display: Move port clock calculation Mika Kahola
2024-05-15 6:45 ` [PATCH 2/2] drm/i915/display: Remove .clock from pll state structure Mika Kahola
2024-05-15 13:28 ` Gustavo Sousa
2024-05-16 8:16 ` Kahola, Mika
2024-05-15 7:36 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display: Move port clock calculation Patchwork
2024-05-15 7:36 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-15 7:41 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-15 13:23 ` [PATCH 1/2] " Gustavo Sousa
2024-05-15 13:32 ` Gustavo Sousa
2024-05-15 13:59 ` Jani Nikula
2024-05-15 14:39 ` Gustavo Sousa
2024-05-16 10:55 ` Kahola, Mika
2024-05-15 15:29 ` ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
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