From: Thomas Gleixner <tglx@linutronix.de>
To: Anup Patel <apatel@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: "Anup Patel" <apatel@ventanamicro.com>,
devicetree@vger.kernel.org,
"Saravana Kannan" <saravanak@google.com>,
"Marc Zyngier" <maz@kernel.org>,
"Anup Patel" <anup@brainfault.org>,
linux-kernel@vger.kernel.org, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
"Andrew Jones" <ajones@ventanamicro.com>
Subject: Re: [PATCH v13 07/13] irqchip/riscv-imsic: Add device MSI domain support for platform devices
Date: Tue, 20 Feb 2024 14:32:27 +0100 [thread overview]
Message-ID: <875xyji7mc.ffs@tglx> (raw)
In-Reply-To: <20240220060718.823229-8-apatel@ventanamicro.com>
On Tue, Feb 20 2024 at 11:37, Anup Patel wrote:
> +#ifdef CONFIG_SMP
> +static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vector *vec)
> +{
> + struct msi_msg msg[2] = { [1] = { }, };
That's a weird initializer and why do you need an array here?
struct msi_msg msg = { };
Should be sufficient, no?
> +
> + imsic_irq_compose_vector_msg(vec, msg);
> + irq_data_get_irq_chip(d)->irq_write_msi_msg(d, msg);
> +}
> +static int imsic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> + unsigned int nr_irqs, void *args)
> +{
> + struct imsic_vector *vec;
> +
> + /* Legacy-MSI or multi-MSI not supported yet. */
Coming back to my earlier question:
>> What's legacy MSI in that context?
>
> The legacy-MSI is the MSI support in PCI v2.2 where
> number of MSIs allocated by device were either 1, 2, 4,
> 8, 16, or 32 and the data written is <data_word> + <irqnum>.
You talk about PCI/MSI, where more than one vector is named
multi-MSI. Contrary to the modern v3.0 variant which is PCI/MSI-X.
So this should be "Multi-MSI is not supported yet", no?
> + if (nr_irqs > 1)
> + return -ENOTSUPP;
> +
> + vec = imsic_vector_alloc(virq, cpu_online_mask);
> + if (!vec)
> + return -ENOSPC;
> +
> + irq_domain_set_info(domain, virq, virq,
> + &imsic_irq_base_chip, vec,
> + handle_simple_irq, NULL, NULL);
Please utilize the 100 characters.
> + irq_set_noprobe(virq);
> + irq_set_affinity(virq, cpu_online_mask);
> +
> + return 0;
> +}
Thanks,
tglx
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: Anup Patel <apatel@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: "Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Saravana Kannan" <saravanak@google.com>,
"Anup Patel" <anup@brainfault.org>,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
"Anup Patel" <apatel@ventanamicro.com>
Subject: Re: [PATCH v13 07/13] irqchip/riscv-imsic: Add device MSI domain support for platform devices
Date: Tue, 20 Feb 2024 14:32:27 +0100 [thread overview]
Message-ID: <875xyji7mc.ffs@tglx> (raw)
In-Reply-To: <20240220060718.823229-8-apatel@ventanamicro.com>
On Tue, Feb 20 2024 at 11:37, Anup Patel wrote:
> +#ifdef CONFIG_SMP
> +static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vector *vec)
> +{
> + struct msi_msg msg[2] = { [1] = { }, };
That's a weird initializer and why do you need an array here?
struct msi_msg msg = { };
Should be sufficient, no?
> +
> + imsic_irq_compose_vector_msg(vec, msg);
> + irq_data_get_irq_chip(d)->irq_write_msi_msg(d, msg);
> +}
> +static int imsic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> + unsigned int nr_irqs, void *args)
> +{
> + struct imsic_vector *vec;
> +
> + /* Legacy-MSI or multi-MSI not supported yet. */
Coming back to my earlier question:
>> What's legacy MSI in that context?
>
> The legacy-MSI is the MSI support in PCI v2.2 where
> number of MSIs allocated by device were either 1, 2, 4,
> 8, 16, or 32 and the data written is <data_word> + <irqnum>.
You talk about PCI/MSI, where more than one vector is named
multi-MSI. Contrary to the modern v3.0 variant which is PCI/MSI-X.
So this should be "Multi-MSI is not supported yet", no?
> + if (nr_irqs > 1)
> + return -ENOTSUPP;
> +
> + vec = imsic_vector_alloc(virq, cpu_online_mask);
> + if (!vec)
> + return -ENOSPC;
> +
> + irq_domain_set_info(domain, virq, virq,
> + &imsic_irq_base_chip, vec,
> + handle_simple_irq, NULL, NULL);
Please utilize the 100 characters.
> + irq_set_noprobe(virq);
> + irq_set_affinity(virq, cpu_online_mask);
> +
> + return 0;
> +}
Thanks,
tglx
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: Anup Patel <apatel@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: "Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Saravana Kannan" <saravanak@google.com>,
"Anup Patel" <anup@brainfault.org>,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
"Anup Patel" <apatel@ventanamicro.com>
Subject: Re: [PATCH v13 07/13] irqchip/riscv-imsic: Add device MSI domain support for platform devices
Date: Tue, 20 Feb 2024 14:32:27 +0100 [thread overview]
Message-ID: <875xyji7mc.ffs@tglx> (raw)
In-Reply-To: <20240220060718.823229-8-apatel@ventanamicro.com>
On Tue, Feb 20 2024 at 11:37, Anup Patel wrote:
> +#ifdef CONFIG_SMP
> +static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vector *vec)
> +{
> + struct msi_msg msg[2] = { [1] = { }, };
That's a weird initializer and why do you need an array here?
struct msi_msg msg = { };
Should be sufficient, no?
> +
> + imsic_irq_compose_vector_msg(vec, msg);
> + irq_data_get_irq_chip(d)->irq_write_msi_msg(d, msg);
> +}
> +static int imsic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> + unsigned int nr_irqs, void *args)
> +{
> + struct imsic_vector *vec;
> +
> + /* Legacy-MSI or multi-MSI not supported yet. */
Coming back to my earlier question:
>> What's legacy MSI in that context?
>
> The legacy-MSI is the MSI support in PCI v2.2 where
> number of MSIs allocated by device were either 1, 2, 4,
> 8, 16, or 32 and the data written is <data_word> + <irqnum>.
You talk about PCI/MSI, where more than one vector is named
multi-MSI. Contrary to the modern v3.0 variant which is PCI/MSI-X.
So this should be "Multi-MSI is not supported yet", no?
> + if (nr_irqs > 1)
> + return -ENOTSUPP;
> +
> + vec = imsic_vector_alloc(virq, cpu_online_mask);
> + if (!vec)
> + return -ENOSPC;
> +
> + irq_domain_set_info(domain, virq, virq,
> + &imsic_irq_base_chip, vec,
> + handle_simple_irq, NULL, NULL);
Please utilize the 100 characters.
> + irq_set_noprobe(virq);
> + irq_set_affinity(virq, cpu_online_mask);
> +
> + return 0;
> +}
Thanks,
tglx
next prev parent reply other threads:[~2024-02-20 13:32 UTC|newest]
Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-20 6:07 [PATCH v13 00/13] Linux RISC-V AIA Support Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 01/13] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 10:09 ` Thomas Gleixner
2024-02-20 10:09 ` Thomas Gleixner
2024-02-20 10:09 ` Thomas Gleixner
2024-02-22 9:25 ` Anup Patel
2024-02-22 9:25 ` Anup Patel
2024-02-22 9:25 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 02/13] irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 10:11 ` Thomas Gleixner
2024-02-20 10:11 ` Thomas Gleixner
2024-02-20 10:11 ` Thomas Gleixner
2024-02-21 13:35 ` Anup Patel
2024-02-21 13:35 ` Anup Patel
2024-02-21 13:35 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 03/13] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 10:13 ` Thomas Gleixner
2024-02-20 10:13 ` Thomas Gleixner
2024-02-20 10:13 ` Thomas Gleixner
2024-02-21 13:32 ` Anup Patel
2024-02-21 13:32 ` Anup Patel
2024-02-21 13:32 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 04/13] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 05/13] genirq/matrix: Dynamic bitmap allocation Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 06/13] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 11:52 ` Björn Töpel
2024-02-20 11:52 ` Björn Töpel
2024-02-20 11:52 ` Björn Töpel
2024-02-20 13:00 ` Anup Patel
2024-02-20 13:00 ` Anup Patel
2024-02-20 13:00 ` Anup Patel
2024-02-21 11:59 ` Björn Töpel
2024-02-21 11:59 ` Björn Töpel
2024-02-21 11:59 ` Björn Töpel
2024-02-21 12:23 ` Anup Patel
2024-02-21 12:23 ` Anup Patel
2024-02-21 12:23 ` Anup Patel
2024-02-21 17:22 ` Björn Töpel
2024-02-21 17:22 ` Björn Töpel
2024-02-21 17:22 ` Björn Töpel
2024-02-20 11:53 ` Björn Töpel
2024-02-20 11:53 ` Björn Töpel
2024-02-20 11:53 ` Björn Töpel
2024-02-20 13:15 ` Anup Patel
2024-02-20 13:15 ` Anup Patel
2024-02-20 13:15 ` Anup Patel
2024-02-20 13:15 ` Thomas Gleixner
2024-02-20 13:15 ` Thomas Gleixner
2024-02-20 13:15 ` Thomas Gleixner
2024-02-20 16:33 ` Anup Patel
2024-02-20 16:33 ` Anup Patel
2024-02-20 16:33 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 07/13] irqchip/riscv-imsic: Add device MSI domain support for platform devices Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 11:53 ` Björn Töpel
2024-02-20 11:53 ` Björn Töpel
2024-02-20 11:53 ` Björn Töpel
2024-02-20 16:39 ` Anup Patel
2024-02-20 16:39 ` Anup Patel
2024-02-20 16:39 ` Anup Patel
2024-02-20 13:32 ` Thomas Gleixner [this message]
2024-02-20 13:32 ` Thomas Gleixner
2024-02-20 13:32 ` Thomas Gleixner
2024-02-20 16:52 ` Anup Patel
2024-02-20 16:52 ` Anup Patel
2024-02-20 16:52 ` Anup Patel
2024-02-20 17:12 ` Thomas Gleixner
2024-02-20 17:12 ` Thomas Gleixner
2024-02-20 17:12 ` Thomas Gleixner
2024-02-20 6:07 ` [PATCH v13 08/13] irqchip/riscv-imsic: Add device MSI domain support for PCI devices Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 13:35 ` Thomas Gleixner
2024-02-20 13:35 ` Thomas Gleixner
2024-02-20 13:35 ` Thomas Gleixner
2024-02-20 17:21 ` Anup Patel
2024-02-20 17:21 ` Anup Patel
2024-02-20 17:21 ` Anup Patel
2024-02-20 20:03 ` Thomas Gleixner
2024-02-20 20:03 ` Thomas Gleixner
2024-02-20 20:03 ` Thomas Gleixner
2024-02-20 6:07 ` [PATCH v13 09/13] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 10/13] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 13:40 ` Thomas Gleixner
2024-02-20 13:40 ` Thomas Gleixner
2024-02-20 13:40 ` Thomas Gleixner
2024-02-21 5:42 ` Anup Patel
2024-02-21 5:42 ` Anup Patel
2024-02-21 5:42 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 11/13] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 12/13] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` [PATCH v13 13/13] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 6:07 ` Anup Patel
2024-02-20 11:52 ` [PATCH v13 00/13] Linux RISC-V AIA Support Björn Töpel
2024-02-20 11:52 ` Björn Töpel
2024-02-20 11:52 ` Björn Töpel
2024-02-20 13:09 ` Anup Patel
2024-02-20 13:09 ` Anup Patel
2024-02-20 13:09 ` Anup Patel
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