* [v2 1/3] drm/i915: Fix the pipe state timing mismatch warnings
@ 2019-04-30 8:17 Vandita Kulkarni
2019-04-30 8:17 ` [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format Vandita Kulkarni
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Vandita Kulkarni @ 2019-04-30 8:17 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala
Adjust the get transcoder timings for mipi dsi as per the
set timing calculations.
v2: Use the existing intel_get_pipe_timings and do the dsi
specific adjustments in the encoder get_config hook.(Ville, Jani)
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 9d962ea..dbb2712 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1193,6 +1193,34 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
gen11_dsi_disable_io_power(encoder);
}
+static void gen11_dsi_get_timings(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct drm_display_mode *adjusted_mode =
+ &pipe_config->base.adjusted_mode;
+
+ if (intel_dsi->dual_link) {
+ adjusted_mode->crtc_hdisplay *= 2;
+ if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+ adjusted_mode->crtc_hdisplay -=
+ intel_dsi->pixel_overlap;
+ adjusted_mode->crtc_htotal *= 2;
+ }
+ adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
+ adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
+
+ if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+ if (intel_dsi->dual_link) {
+ adjusted_mode->crtc_hsync_start *= 2;
+ adjusted_mode->crtc_hsync_end *= 2;
+ }
+ }
+ adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
+ adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
+
+}
+
static void gen11_dsi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -1203,6 +1231,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
pipe_config->port_clock =
cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+ gen11_dsi_get_timings(encoder, pipe_config);
pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format 2019-04-30 8:17 [v2 1/3] drm/i915: Fix the pipe state timing mismatch warnings Vandita Kulkarni @ 2019-04-30 8:17 ` Vandita Kulkarni 2019-04-30 9:33 ` Jani Nikula 2019-04-30 8:17 ` [v2 3/3] drm/i915: Fix pixel clock and crtc clock config mismatch Vandita Kulkarni 2019-04-30 13:04 ` ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915: Fix the pipe state timing mismatch warnings Patchwork 2 siblings, 1 reply; 8+ messages in thread From: Vandita Kulkarni @ 2019-04-30 8:17 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, ville.syrjala Read back the pixel fomrat register and get the bpp. v2: Read the PIPE_MISC register (Jani). Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/icl_dsi.c | 3 +++ drivers/gpu/drm/i915/intel_dsi.h | 1 + drivers/gpu/drm/i915/vlv_dsi.c | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index dbb2712..5cc58b2 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -1226,6 +1226,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ pipe_config->port_clock = @@ -1233,6 +1234,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; gen11_dsi_get_timings(encoder, pipe_config); pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); + pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); } static int gen11_dsi_compute_config(struct intel_encoder *encoder, @@ -1248,6 +1250,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder, struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; intel_fixed_panel_mode(fixed_mode, adjusted_mode); intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode); diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 705a609..cb9e3b9 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -166,6 +166,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector, struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, const struct mipi_dsi_host_ops *funcs, enum port port); +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); /* vlv_dsi_pll.c */ int vlv_dsi_pll_compute(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c index b4c6583..790ada8 100644 --- a/drivers/gpu/drm/i915/vlv_dsi.c +++ b/drivers/gpu/drm/i915/vlv_dsi.c @@ -260,7 +260,7 @@ static void band_gap_reset(struct drm_i915_private *dev_priv) vlv_flisdsi_put(dev_priv); } -static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 tmp; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format 2019-04-30 8:17 ` [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format Vandita Kulkarni @ 2019-04-30 9:33 ` Jani Nikula 2019-04-30 12:39 ` Kulkarni, Vandita 0 siblings, 1 reply; 8+ messages in thread From: Jani Nikula @ 2019-04-30 9:33 UTC (permalink / raw) To: Vandita Kulkarni, intel-gfx; +Cc: ville.syrjala On Tue, 30 Apr 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > Read back the pixel fomrat register and get the bpp. > > v2: Read the PIPE_MISC register (Jani). > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/icl_dsi.c | 3 +++ > drivers/gpu/drm/i915/intel_dsi.h | 1 + > drivers/gpu/drm/i915/vlv_dsi.c | 2 +- > 3 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c > index dbb2712..5cc58b2 100644 > --- a/drivers/gpu/drm/i915/icl_dsi.c > +++ b/drivers/gpu/drm/i915/icl_dsi.c > @@ -1226,6 +1226,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); > > /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ > pipe_config->port_clock = > @@ -1233,6 +1234,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, > pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; > gen11_dsi_get_timings(encoder, pipe_config); > pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); > + pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); > } > > static int gen11_dsi_compute_config(struct intel_encoder *encoder, > @@ -1248,6 +1250,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder, > struct drm_display_mode *adjusted_mode = > &pipe_config->base.adjusted_mode; > > + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; > intel_fixed_panel_mode(fixed_mode, adjusted_mode); > intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode); > > diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h > index 705a609..cb9e3b9 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.h > +++ b/drivers/gpu/drm/i915/intel_dsi.h > @@ -166,6 +166,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector, > struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, > const struct mipi_dsi_host_ops *funcs, > enum port port); > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); Until now this was internal to vlv_dsi.c and it was fine. Now, I think I'd move this to intel_display.c alongside haswell_set_pipemisc. Ville already has patches to rename haswell_set_pipemisc to bdw_set_pipemisc. BR, Jani. > > /* vlv_dsi_pll.c */ > int vlv_dsi_pll_compute(struct intel_encoder *encoder, > diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c > index b4c6583..790ada8 100644 > --- a/drivers/gpu/drm/i915/vlv_dsi.c > +++ b/drivers/gpu/drm/i915/vlv_dsi.c > @@ -260,7 +260,7 @@ static void band_gap_reset(struct drm_i915_private *dev_priv) > vlv_flisdsi_put(dev_priv); > } > > -static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > u32 tmp; -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format 2019-04-30 9:33 ` Jani Nikula @ 2019-04-30 12:39 ` Kulkarni, Vandita 2019-04-30 12:46 ` Jani Nikula 0 siblings, 1 reply; 8+ messages in thread From: Kulkarni, Vandita @ 2019-04-30 12:39 UTC (permalink / raw) To: Nikula, Jani, intel-gfx@lists.freedesktop.org; +Cc: Syrjala, Ville > -----Original Message----- > From: Nikula, Jani > Sent: Tuesday, April 30, 2019 3:03 PM > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel- > gfx@lists.freedesktop.org > Cc: Syrjala, Ville <ville.syrjala@intel.com>; Shankar, Uma > <uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com> > Subject: Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format > > On Tue, 30 Apr 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > > Read back the pixel fomrat register and get the bpp. > > > > v2: Read the PIPE_MISC register (Jani). > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > --- > > drivers/gpu/drm/i915/icl_dsi.c | 3 +++ > > drivers/gpu/drm/i915/intel_dsi.h | 1 + > > drivers/gpu/drm/i915/vlv_dsi.c | 2 +- > > 3 files changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c > > b/drivers/gpu/drm/i915/icl_dsi.c index dbb2712..5cc58b2 100644 > > --- a/drivers/gpu/drm/i915/icl_dsi.c > > +++ b/drivers/gpu/drm/i915/icl_dsi.c > > @@ -1226,6 +1226,7 @@ static void gen11_dsi_get_config(struct > > intel_encoder *encoder, { > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > > + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); > > > > /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ > > pipe_config->port_clock = > > @@ -1233,6 +1234,7 @@ static void gen11_dsi_get_config(struct > intel_encoder *encoder, > > pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; > > gen11_dsi_get_timings(encoder, pipe_config); > > pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); > > + pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); > > } > > > > static int gen11_dsi_compute_config(struct intel_encoder *encoder, @@ > > -1248,6 +1250,7 @@ static int gen11_dsi_compute_config(struct > intel_encoder *encoder, > > struct drm_display_mode *adjusted_mode = > > &pipe_config->base.adjusted_mode; > > > > + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; > > intel_fixed_panel_mode(fixed_mode, adjusted_mode); > > intel_pch_panel_fitting(crtc, pipe_config, > > conn_state->scaling_mode); > > > > diff --git a/drivers/gpu/drm/i915/intel_dsi.h > > b/drivers/gpu/drm/i915/intel_dsi.h > > index 705a609..cb9e3b9 100644 > > --- a/drivers/gpu/drm/i915/intel_dsi.h > > +++ b/drivers/gpu/drm/i915/intel_dsi.h > > @@ -166,6 +166,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct > > drm_connector *connector, struct intel_dsi_host *intel_dsi_host_init(struct > intel_dsi *intel_dsi, > > const struct mipi_dsi_host_ops > *funcs, > > enum port port); > > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); > > Until now this was internal to vlv_dsi.c and it was fine. Now, I think I'd move this > to intel_display.c alongside haswell_set_pipemisc. Ok, so I ll move thjs to intel_display.c and call it from haswell_get_pipe_config for is_dsi and gen >= 9 Thanks, Vandita > > Ville already has patches to rename haswell_set_pipemisc to bdw_set_pipemisc. > > BR, > Jani. > > > > > > /* vlv_dsi_pll.c */ > > int vlv_dsi_pll_compute(struct intel_encoder *encoder, diff --git > > a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c > > index b4c6583..790ada8 100644 > > --- a/drivers/gpu/drm/i915/vlv_dsi.c > > +++ b/drivers/gpu/drm/i915/vlv_dsi.c > > @@ -260,7 +260,7 @@ static void band_gap_reset(struct drm_i915_private > *dev_priv) > > vlv_flisdsi_put(dev_priv); > > } > > > > -static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) > > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) > > { > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > u32 tmp; > > -- > Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format 2019-04-30 12:39 ` Kulkarni, Vandita @ 2019-04-30 12:46 ` Jani Nikula 2019-04-30 12:59 ` Kulkarni, Vandita 0 siblings, 1 reply; 8+ messages in thread From: Jani Nikula @ 2019-04-30 12:46 UTC (permalink / raw) To: Kulkarni, Vandita, intel-gfx@lists.freedesktop.org; +Cc: Syrjala, Ville On Tue, 30 Apr 2019, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote: >> -----Original Message----- >> From: Nikula, Jani >> Sent: Tuesday, April 30, 2019 3:03 PM >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel- >> gfx@lists.freedesktop.org >> Cc: Syrjala, Ville <ville.syrjala@intel.com>; Shankar, Uma >> <uma.shankar@intel.com>; Kulkarni, Vandita <vandita.kulkarni@intel.com> >> Subject: Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format >> >> On Tue, 30 Apr 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: >> > Read back the pixel fomrat register and get the bpp. >> > >> > v2: Read the PIPE_MISC register (Jani). >> > >> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> >> > --- >> > drivers/gpu/drm/i915/icl_dsi.c | 3 +++ >> > drivers/gpu/drm/i915/intel_dsi.h | 1 + >> > drivers/gpu/drm/i915/vlv_dsi.c | 2 +- >> > 3 files changed, 5 insertions(+), 1 deletion(-) >> > >> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c >> > b/drivers/gpu/drm/i915/icl_dsi.c index dbb2712..5cc58b2 100644 >> > --- a/drivers/gpu/drm/i915/icl_dsi.c >> > +++ b/drivers/gpu/drm/i915/icl_dsi.c >> > @@ -1226,6 +1226,7 @@ static void gen11_dsi_get_config(struct >> > intel_encoder *encoder, { >> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); >> > + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); >> > >> > /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ >> > pipe_config->port_clock = >> > @@ -1233,6 +1234,7 @@ static void gen11_dsi_get_config(struct >> intel_encoder *encoder, >> > pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; >> > gen11_dsi_get_timings(encoder, pipe_config); >> > pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); >> > + pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); >> > } >> > >> > static int gen11_dsi_compute_config(struct intel_encoder *encoder, @@ >> > -1248,6 +1250,7 @@ static int gen11_dsi_compute_config(struct >> intel_encoder *encoder, >> > struct drm_display_mode *adjusted_mode = >> > &pipe_config->base.adjusted_mode; >> > >> > + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; >> > intel_fixed_panel_mode(fixed_mode, adjusted_mode); >> > intel_pch_panel_fitting(crtc, pipe_config, >> > conn_state->scaling_mode); >> > >> > diff --git a/drivers/gpu/drm/i915/intel_dsi.h >> > b/drivers/gpu/drm/i915/intel_dsi.h >> > index 705a609..cb9e3b9 100644 >> > --- a/drivers/gpu/drm/i915/intel_dsi.h >> > +++ b/drivers/gpu/drm/i915/intel_dsi.h >> > @@ -166,6 +166,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct >> > drm_connector *connector, struct intel_dsi_host *intel_dsi_host_init(struct >> intel_dsi *intel_dsi, >> > const struct mipi_dsi_host_ops >> *funcs, >> > enum port port); >> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); >> >> Until now this was internal to vlv_dsi.c and it was fine. Now, I think I'd move this >> to intel_display.c alongside haswell_set_pipemisc. > Ok, so I ll move thjs to intel_display.c and call it from haswell_get_pipe_config for is_dsi and gen >= 9 I'd actually prefer to call it from dsi encoder code instead. BR, Jani. > Thanks, > Vandita >> >> Ville already has patches to rename haswell_set_pipemisc to bdw_set_pipemisc. >> >> BR, >> Jani. >> >> >> > >> > /* vlv_dsi_pll.c */ >> > int vlv_dsi_pll_compute(struct intel_encoder *encoder, diff --git >> > a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c >> > index b4c6583..790ada8 100644 >> > --- a/drivers/gpu/drm/i915/vlv_dsi.c >> > +++ b/drivers/gpu/drm/i915/vlv_dsi.c >> > @@ -260,7 +260,7 @@ static void band_gap_reset(struct drm_i915_private >> *dev_priv) >> > vlv_flisdsi_put(dev_priv); >> > } >> > >> > -static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) >> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) >> > { >> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); >> > u32 tmp; >> >> -- >> Jani Nikula, Intel Open Source Graphics Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format 2019-04-30 12:46 ` Jani Nikula @ 2019-04-30 12:59 ` Kulkarni, Vandita 0 siblings, 0 replies; 8+ messages in thread From: Kulkarni, Vandita @ 2019-04-30 12:59 UTC (permalink / raw) To: Nikula, Jani, intel-gfx@lists.freedesktop.org; +Cc: Syrjala, Ville > -----Original Message----- > From: Nikula, Jani > Sent: Tuesday, April 30, 2019 6:16 PM > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel- > gfx@lists.freedesktop.org > Cc: Syrjala, Ville <ville.syrjala@intel.com> > Subject: Re: [Intel-gfx] [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, > output format > > On Tue, 30 Apr 2019, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote: > >> -----Original Message----- > >> From: Nikula, Jani > >> Sent: Tuesday, April 30, 2019 3:03 PM > >> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel- > >> gfx@lists.freedesktop.org > >> Cc: Syrjala, Ville <ville.syrjala@intel.com>; Shankar, Uma > >> <uma.shankar@intel.com>; Kulkarni, Vandita > >> <vandita.kulkarni@intel.com> > >> Subject: Re: [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, > >> output format > >> > >> On Tue, 30 Apr 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote: > >> > Read back the pixel fomrat register and get the bpp. > >> > > >> > v2: Read the PIPE_MISC register (Jani). > >> > > >> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > >> > --- > >> > drivers/gpu/drm/i915/icl_dsi.c | 3 +++ > >> > drivers/gpu/drm/i915/intel_dsi.h | 1 + > >> > drivers/gpu/drm/i915/vlv_dsi.c | 2 +- > >> > 3 files changed, 5 insertions(+), 1 deletion(-) > >> > > >> > diff --git a/drivers/gpu/drm/i915/icl_dsi.c > >> > b/drivers/gpu/drm/i915/icl_dsi.c index dbb2712..5cc58b2 100644 > >> > --- a/drivers/gpu/drm/i915/icl_dsi.c > >> > +++ b/drivers/gpu/drm/i915/icl_dsi.c > >> > @@ -1226,6 +1226,7 @@ static void gen11_dsi_get_config(struct > >> > intel_encoder *encoder, { > >> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > >> > + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); > >> > > >> > /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ > >> > pipe_config->port_clock = > >> > @@ -1233,6 +1234,7 @@ static void gen11_dsi_get_config(struct > >> intel_encoder *encoder, > >> > pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; > >> > gen11_dsi_get_timings(encoder, pipe_config); > >> > pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); > >> > + pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); > >> > } > >> > > >> > static int gen11_dsi_compute_config(struct intel_encoder *encoder, > >> > @@ > >> > -1248,6 +1250,7 @@ static int gen11_dsi_compute_config(struct > >> intel_encoder *encoder, > >> > struct drm_display_mode *adjusted_mode = > >> > &pipe_config->base.adjusted_mode; > >> > > >> > + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; > >> > intel_fixed_panel_mode(fixed_mode, adjusted_mode); > >> > intel_pch_panel_fitting(crtc, pipe_config, > >> > conn_state->scaling_mode); > >> > > >> > diff --git a/drivers/gpu/drm/i915/intel_dsi.h > >> > b/drivers/gpu/drm/i915/intel_dsi.h > >> > index 705a609..cb9e3b9 100644 > >> > --- a/drivers/gpu/drm/i915/intel_dsi.h > >> > +++ b/drivers/gpu/drm/i915/intel_dsi.h > >> > @@ -166,6 +166,7 @@ enum drm_mode_status > >> > intel_dsi_mode_valid(struct drm_connector *connector, struct > >> > intel_dsi_host *intel_dsi_host_init(struct > >> intel_dsi *intel_dsi, > >> > const struct mipi_dsi_host_ops > >> *funcs, > >> > enum port port); > >> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); > >> > >> Until now this was internal to vlv_dsi.c and it was fine. Now, I > >> think I'd move this to intel_display.c alongside haswell_set_pipemisc. > > Ok, so I ll move thjs to intel_display.c and call it from > > haswell_get_pipe_config for is_dsi and gen >= 9 > > I'd actually prefer to call it from dsi encoder code instead. Ok. Will do that. Thanks, Vandita > > BR, > Jani. > > > Thanks, > > Vandita > >> > >> Ville already has patches to rename haswell_set_pipemisc to > bdw_set_pipemisc. > >> > >> BR, > >> Jani. > >> > >> > >> > > >> > /* vlv_dsi_pll.c */ > >> > int vlv_dsi_pll_compute(struct intel_encoder *encoder, diff --git > >> > a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c > >> > index b4c6583..790ada8 100644 > >> > --- a/drivers/gpu/drm/i915/vlv_dsi.c > >> > +++ b/drivers/gpu/drm/i915/vlv_dsi.c > >> > @@ -260,7 +260,7 @@ static void band_gap_reset(struct > >> > drm_i915_private > >> *dev_priv) > >> > vlv_flisdsi_put(dev_priv); > >> > } > >> > > >> > -static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) > >> > +int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) > >> > { > >> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > >> > u32 tmp; > >> > >> -- > >> Jani Nikula, Intel Open Source Graphics Center > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [v2 3/3] drm/i915: Fix pixel clock and crtc clock config mismatch 2019-04-30 8:17 [v2 1/3] drm/i915: Fix the pipe state timing mismatch warnings Vandita Kulkarni 2019-04-30 8:17 ` [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format Vandita Kulkarni @ 2019-04-30 8:17 ` Vandita Kulkarni 2019-04-30 13:04 ` ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915: Fix the pipe state timing mismatch warnings Patchwork 2 siblings, 0 replies; 8+ messages in thread From: Vandita Kulkarni @ 2019-04-30 8:17 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, ville.syrjala In case of dual link mode, the mode clock that we get from the VBT is halved. v2: Simplify the calculation (Jani). Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/icl_dsi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 5cc58b2..9636cc2 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -1231,7 +1231,11 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); + pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; + if (intel_dsi->dual_link) + pipe_config->base.adjusted_mode.crtc_clock *= 2; + gen11_dsi_get_timings(encoder, pipe_config); pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915: Fix the pipe state timing mismatch warnings 2019-04-30 8:17 [v2 1/3] drm/i915: Fix the pipe state timing mismatch warnings Vandita Kulkarni 2019-04-30 8:17 ` [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format Vandita Kulkarni 2019-04-30 8:17 ` [v2 3/3] drm/i915: Fix pixel clock and crtc clock config mismatch Vandita Kulkarni @ 2019-04-30 13:04 ` Patchwork 2 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2019-04-30 13:04 UTC (permalink / raw) To: Kulkarni, Vandita; +Cc: intel-gfx == Series Details == Series: series starting with [v2,1/3] drm/i915: Fix the pipe state timing mismatch warnings URL : https://patchwork.freedesktop.org/series/60094/ State : failure == Summary == Applying: drm/i915: Fix the pipe state timing mismatch warnings Applying: drm/i915: Fix pipe config mismatch for bpp, output format error: sha1 information is lacking or useless (drivers/gpu/drm/i915/icl_dsi.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915: Fix pipe config mismatch for bpp, output format When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-04-30 13:04 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-04-30 8:17 [v2 1/3] drm/i915: Fix the pipe state timing mismatch warnings Vandita Kulkarni 2019-04-30 8:17 ` [v2 2/3] drm/i915: Fix pipe config mismatch for bpp, output format Vandita Kulkarni 2019-04-30 9:33 ` Jani Nikula 2019-04-30 12:39 ` Kulkarni, Vandita 2019-04-30 12:46 ` Jani Nikula 2019-04-30 12:59 ` Kulkarni, Vandita 2019-04-30 8:17 ` [v2 3/3] drm/i915: Fix pixel clock and crtc clock config mismatch Vandita Kulkarni 2019-04-30 13:04 ` ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915: Fix the pipe state timing mismatch warnings Patchwork
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