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From: "Keith Packard" <keithp@keithp.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
	Riku Voipio <riku.voipio@iki.fi>,
	Laurent Vivier <laurent@vivier.eu>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	"open list\:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH] riscv: Add semihosting support [v4]
Date: Wed, 29 Jan 2020 08:45:27 -0800	[thread overview]
Message-ID: <877e1arz2w.fsf@keithp.org> (raw)
In-Reply-To: <CAFEAcA_dD3eAfKvOGOoXe3NWKg1PiW8=s2Xk41w19Tk67R-R4A@mail.gmail.com>

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Peter Maydell <peter.maydell@linaro.org> writes:

> True but irrelevant. You need to refer to a proper
> risc-v specification for your semihosting.

The RISC-V Foundation defined semihosting as relative to the existing
ARM specification, so using a link to that is appropriate here.

Here's the current specification of the unprivileged ISA, which includes
the definition of semihosting

        https://riscv.org/specifications/

While it may be nice in some abstract sense to create a "better"
semihosting spec, that's not what the RISC-V foundation has decided to
do.

-- 
-keith

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WARNING: multiple messages have this Message-ID (diff)
From: "Keith Packard" via <qemu-devel@nongnu.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
	Riku Voipio <riku.voipio@iki.fi>,
	Laurent Vivier <laurent@vivier.eu>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	"open list\:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH] riscv: Add semihosting support [v4]
Date: Wed, 29 Jan 2020 08:45:27 -0800	[thread overview]
Message-ID: <877e1arz2w.fsf@keithp.org> (raw)
In-Reply-To: <CAFEAcA_dD3eAfKvOGOoXe3NWKg1PiW8=s2Xk41w19Tk67R-R4A@mail.gmail.com>

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Peter Maydell <peter.maydell@linaro.org> writes:

> True but irrelevant. You need to refer to a proper
> risc-v specification for your semihosting.

The RISC-V Foundation defined semihosting as relative to the existing
ARM specification, so using a link to that is appropriate here.

Here's the current specification of the unprivileged ISA, which includes
the definition of semihosting

        https://riscv.org/specifications/

While it may be nice in some abstract sense to create a "better"
semihosting spec, that's not what the RISC-V foundation has decided to
do.

-- 
-keith

[-- Attachment #2: signature.asc --]
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  reply	other threads:[~2020-01-29 16:45 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-28 23:32 [PATCH] riscv: Add semihosting support [v4] Keith Packard
2020-01-28 23:32 ` Keith Packard via
2020-01-29 15:58 ` Peter Maydell
2020-01-29 15:58   ` Peter Maydell
2020-01-29 16:45   ` Keith Packard [this message]
2020-01-29 16:45     ` Keith Packard via
2020-01-29 18:06     ` Jonathan Behrens
2020-01-29 18:06       ` Jonathan Behrens
2020-01-30 10:54     ` Peter Maydell
2020-01-30 10:54       ` Peter Maydell
2020-01-30 11:38       ` Palmer Dabbelt
2020-01-30 12:01         ` Peter Maydell
2020-01-30 12:01           ` Peter Maydell
2020-04-06  5:24           ` [PATCH] riscv: Add semihosting support [v5] Keith Packard
2020-04-06  5:24             ` Keith Packard via
2020-03-07 19:44         ` [PATCH] riscv: Add semihosting support [v4] Keith Packard
2020-03-07 19:44           ` Keith Packard via

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