* [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register
2016-12-08 8:49 [GLK MIPI DSI V1 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
@ 2016-12-08 8:49 ` Madhav Chauhan
2016-12-13 11:36 ` Jani Nikula
2016-12-08 8:49 ` [GLK MIPI DSI V1 2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK Madhav Chauhan
` (8 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Madhav Chauhan @ 2016-12-08 8:49 UTC (permalink / raw)
To: intel-gfx
Cc: ander.conselvan.de.oliveira, jani.nikula, shobhit.kumar, Deepak M
From: Deepak M <m.deepak@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 90685d2..6bd68bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8658,6 +8658,21 @@ enum {
#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
+#define PHY_STATUS (1 << 31) /* RO */
+#define ULPS_NOT_ACTIVE (1 << 30) /* RO */
+#define MIPIIO_RESET (1 << 28)
+#define CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
+#define DATA_LANE_STOP_STATE (1 << 26) /* RO */
+#define LP_WAKE (1 << 22)
+#define LP11_LOW_PWR_MODE (1 << 21)
+#define LP00_LOW_PWR_MODE (1 << 20)
+#define FIREWALL_ENABLE (1 << 16)
+#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
+#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
+#define DSC_ENABLE (1 << 3)
+#define RGB_FLIP (1 << 2)
+#define PWR_ACK (1 << 1) /* RO */
+#define MIPI_MODE (1 << 0)
#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
--
1.9.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register
2016-12-08 8:49 ` [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register Madhav Chauhan
@ 2016-12-13 11:36 ` Jani Nikula
2016-12-14 11:02 ` Chauhan, Madhav
0 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2016-12-13 11:36 UTC (permalink / raw)
To: Madhav Chauhan, intel-gfx
Cc: ander.conselvan.de.oliveira, Deepak M, shobhit.kumar
On Thu, 08 Dec 2016, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 90685d2..6bd68bf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8658,6 +8658,21 @@ enum {
> #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
> #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
> #define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
Ugh, the register has been completely changed between VLV/CHV and
BXT. *All* of the new bits will need BXT_ or GLK_ prefix, depending on
when they were introduced. Please also put them in high to low bit order
around BXT_PIPE_SELECT stuff below, to group all BXT+ stuff separately
from VLV/CHV.
> +#define PHY_STATUS (1 << 31) /* RO */
GLK_. The name could indicate the purpose, even if that's not the way
it's in the spec. It'll help us. GLK_PHY_STATUS_PORT_READY?
> +#define ULPS_NOT_ACTIVE (1 << 30) /* RO */
GLK_
> +#define MIPIIO_RESET (1 << 28)
GLK_MIPIIO_RESET_RELEASED?
> +#define CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
GLK_CLOCK_LANES_STOP_STATE
> +#define DATA_LANE_STOP_STATE (1 << 26) /* RO */
GLK_DATA_LANES_STOP_STATE
> +#define LP_WAKE (1 << 22)
GLK_
> +#define LP11_LOW_PWR_MODE (1 << 21)
GLK_LP11_LOW_POWER_MODE
> +#define LP00_LOW_PWR_MODE (1 << 20)
GLK_LP00_LOW_POWER_MODE
> +#define FIREWALL_ENABLE (1 << 16)
GLK_
> +#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
> +#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
> +#define DSC_ENABLE (1 << 3)
BXT_?
> +#define RGB_FLIP (1 << 2)
BXT_?
> +#define PWR_ACK (1 << 1) /* RO */
> +#define MIPI_MODE (1 << 0)
GLK_MIPIIO_ENABLE?
BR,
Jani.
> #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
> #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
> #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register
2016-12-13 11:36 ` Jani Nikula
@ 2016-12-14 11:02 ` Chauhan, Madhav
2016-12-14 11:46 ` Jani Nikula
0 siblings, 1 reply; 15+ messages in thread
From: Chauhan, Madhav @ 2016-12-14 11:02 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org
Cc: Conselvan De Oliveira, Ander, Deepak, M, Kumar, Shobhit
> -----Original Message-----
> From: Nikula, Jani
> Sent: Tuesday, December 13, 2016 5:07 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
> Saarinen, Jani <jani.saarinen@intel.com>; Konduru, Chandra
> <chandra.konduru@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Mukherjee, Indranil <indranil.mukherjee@intel.com>; Kumar, Shobhit
> <shobhit.kumar@intel.com>; Deepak, M <m.deepak@intel.com>; Chauhan,
> Madhav <madhav.chauhan@intel.com>
> Subject: Re: [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI
> CTRL register
>
> On Thu, 08 Dec 2016, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > From: Deepak M <m.deepak@intel.com>
> >
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 90685d2..6bd68bf 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8658,6 +8658,21 @@ enum {
> > #define _MIPIA_CTRL (dev_priv->mipi_mmio_base
> + 0xb104)
> > #define _MIPIC_CTRL (dev_priv->mipi_mmio_base
> + 0xb904)
> > #define MIPI_CTRL(port) _MMIO_MIPI(port,
> _MIPIA_CTRL, _MIPIC_CTRL)
>
> Ugh, the register has been completely changed between VLV/CHV and BXT.
> *All* of the new bits will need BXT_ or GLK_ prefix, depending on when they
> were introduced. Please also put them in high to low bit order around
> BXT_PIPE_SELECT stuff below, to group all BXT+ stuff separately from
> VLV/CHV.
Thanks for review Jani.
>
> > +#define PHY_STATUS (1 << 31) /*
> RO */
>
> GLK_. The name could indicate the purpose, even if that's not the way it's in
> the spec. It'll help us. GLK_PHY_STATUS_PORT_READY?
>
> > +#define ULPS_NOT_ACTIVE (1 << 30) /* RO */
>
> GLK_
>
> > +#define MIPIIO_RESET (1 << 28)
>
> GLK_MIPIIO_RESET_RELEASED?
>
> > +#define CLOCK_LANE_STOP_STATE (1 << 27) /*
> RO */
>
> GLK_CLOCK_LANES_STOP_STATE
>
> > +#define DATA_LANE_STOP_STATE (1 << 26) /*
> RO */
>
> GLK_DATA_LANES_STOP_STATE
>
> > +#define LP_WAKE (1 << 22)
>
> GLK_
>
> > +#define LP11_LOW_PWR_MODE (1 << 21)
>
> GLK_LP11_LOW_POWER_MODE
>
> > +#define LP00_LOW_PWR_MODE (1 << 20)
>
> GLK_LP00_LOW_POWER_MODE
>
> > +#define FIREWALL_ENABLE (1 << 16)
>
> GLK_
>
> > +#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
> > +#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
> > +#define DSC_ENABLE (1 << 3)
>
> BXT_?
DSC_ENABLE common for GLK and BXT, shouldn't we add GEN9LP_??
>
> > +#define RGB_FLIP (1 << 2)
>
> BXT_?
This is also common for GLK and BXT, GEN9LP_ ??
Overall, any bit field/register (added in this series) specific to GLK should have GLK_ and common to GLK/BXT should have GEN9LP_ ??
>
> > +#define PWR_ACK (1 << 1) /* RO */
> > +#define MIPI_MODE (1 << 0)
>
> GLK_MIPIIO_ENABLE?
>
> BR,
> Jani.
>
> > #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
> > #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
> > #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
>
>
> --
> Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register
2016-12-14 11:02 ` Chauhan, Madhav
@ 2016-12-14 11:46 ` Jani Nikula
2016-12-14 12:20 ` Chauhan, Madhav
0 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2016-12-14 11:46 UTC (permalink / raw)
To: Chauhan, Madhav, intel-gfx@lists.freedesktop.org
Cc: Conselvan De Oliveira, Ander, Deepak, M, Kumar, Shobhit
On Wed, 14 Dec 2016, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
> Overall, any bit field/register (added in this series) specific to GLK
> should have GLK_ and common to GLK/BXT should have GEN9LP_ ??
It's a long standing convention in the driver to name things after the
first platform they were introduced in.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register
2016-12-14 11:46 ` Jani Nikula
@ 2016-12-14 12:20 ` Chauhan, Madhav
0 siblings, 0 replies; 15+ messages in thread
From: Chauhan, Madhav @ 2016-12-14 12:20 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org
Cc: Conselvan De Oliveira, Ander, Deepak, M, Kumar, Shobhit
> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, December 14, 2016 5:17 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Conselvan De Oliveira, Ander <ander.conselvan.de.oliveira@intel.com>;
> Saarinen, Jani <jani.saarinen@intel.com>; Konduru, Chandra
> <chandra.konduru@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Mukherjee, Indranil <indranil.mukherjee@intel.com>; Kumar, Shobhit
> <shobhit.kumar@intel.com>; Deepak, M <m.deepak@intel.com>
> Subject: RE: [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI
> CTRL register
>
> On Wed, 14 Dec 2016, "Chauhan, Madhav" <madhav.chauhan@intel.com>
> wrote:
> > Overall, any bit field/register (added in this series) specific to GLK
> > should have GLK_ and common to GLK/BXT should have GEN9LP_ ??
>
> It's a long standing convention in the driver to name things after the
> first platform they were introduced in.
Thanks for clarification Jani. Will resend the patches after changes.
>
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [GLK MIPI DSI V1 2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK
2016-12-08 8:49 [GLK MIPI DSI V1 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2016-12-08 8:49 ` [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register Madhav Chauhan
@ 2016-12-08 8:49 ` Madhav Chauhan
2016-12-08 8:49 ` [GLK MIPI DSI V1 3/9] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
` (7 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Madhav Chauhan @ 2016-12-08 8:49 UTC (permalink / raw)
To: intel-gfx
Cc: ander.conselvan.de.oliveira, jani.nikula, shobhit.kumar, Deepak M
From: Deepak M <m.deepak@intel.com>
Program the clk lane and tlpx time count registers
to configure DSI PHY.
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++++
drivers/gpu/drm/i915/intel_dsi.c | 10 ++++++++++
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6bd68bf..cc6bb18 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8550,6 +8550,24 @@ enum {
#define LP_BYTECLK_SHIFT 0
#define LP_BYTECLK_MASK (0xffff << 0)
+#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
+#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
+#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
+#define DPHY_TLPX_TIME_CNT_SHIFT 0
+#define DPHY_TLPX_TIME_CNT_MASK (0xff << 0)
+
+#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
+#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
+#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
+#define MIPI_CLK_LANE_HS_PREP_SHIFT 0
+#define MIPI_CLK_LANE_HS_PREP_MASK (0xff << 0)
+#define MIPI_CLK_LANE_HS_ZERO_SHIFT 8
+#define MIPI_CLK_LANE_HS_ZERO_MASK (0xff00 << 0)
+#define MIPI_CLK_LANE_HS_TRAIL_SHIFT 16
+#define MIPI_CLK_LANE_HS_TRAIL_MASK (0xff0000 << 0)
+#define MIPI_CLK_LANE_HS_EXIT_SHIFT 24
+#define MIPI_CLK_LANE_HS_EXIT_MASK (0xff000000 << 0)
+
/* bits 31:0 */
#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 6b63355..34bbdc2 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1123,6 +1123,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+ struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
enum port port;
unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -1278,6 +1279,15 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
*/
I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
+ if (IS_GEMINILAKE(dev_priv)) {
+ I915_WRITE(MIPI_TLPX_TIME_COUNT(port), intel_dsi->lp_byte_clk);
+ val = ((mipi_config->ths_prepare << MIPI_CLK_LANE_HS_PREP_SHIFT) |
+ (mipi_config->ths_prepare_hszero << MIPI_CLK_LANE_HS_ZERO_SHIFT) |
+ (mipi_config->ths_trail << MIPI_CLK_LANE_HS_TRAIL_SHIFT) |
+ (mipi_config->ths_exit << MIPI_CLK_LANE_HS_EXIT_SHIFT));
+ I915_WRITE(MIPI_CLK_LANE_TIMING(port), val);
+ }
+
/* the bw essential for transmitting 16 long packets containing
* 252 bytes meant for dcs write memory command is programmed in
* this register in terms of byte clocks. based on dsi transfer
--
1.9.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [GLK MIPI DSI V1 3/9] drm/i915/glk: Add MIPIIO Enable/disable sequence
2016-12-08 8:49 [GLK MIPI DSI V1 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2016-12-08 8:49 ` [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register Madhav Chauhan
2016-12-08 8:49 ` [GLK MIPI DSI V1 2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK Madhav Chauhan
@ 2016-12-08 8:49 ` Madhav Chauhan
2016-12-08 8:49 ` [GLK MIPI DSI V1 4/9] drm/i915: Set the Z inversion overlap field Madhav Chauhan
` (6 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Madhav Chauhan @ 2016-12-08 8:49 UTC (permalink / raw)
To: intel-gfx
Cc: ander.conselvan.de.oliveira, jani.nikula, shobhit.kumar, Deepak M
From: Deepak M <m.deepak@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 130 +++++++++++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 34bbdc2..729fcc9 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -357,6 +357,130 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
return true;
}
+static void intel_dsi_disable_mipiio(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 tmp;
+
+ /* Put the IO into reset */
+ tmp = I915_READ(MIPI_CTRL(PORT_A));
+ tmp &= ~MIPIIO_RESET;
+ I915_WRITE(MIPI_CTRL(PORT_A), tmp);
+
+ /* Wait for MIPI PHY status bit to unset */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port), PHY_STATUS, 0, 20))
+ DRM_ERROR("PHY is not turning OFF\n");
+ }
+
+ /* Clear MIPI mode */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(MIPI_CTRL(port));
+ tmp &= ~MIPI_MODE;
+ I915_WRITE(MIPI_CTRL(port), tmp);
+ }
+}
+
+static void intel_dsi_enable_mipiio(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 tmp, val;
+
+ /* Put the IO into reset */
+ tmp = I915_READ(MIPI_CTRL(PORT_A));
+ tmp &= ~MIPIIO_RESET;
+ I915_WRITE(MIPI_CTRL(PORT_A), tmp);
+
+ /* Program LP Wake */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(MIPI_CTRL(port));
+ tmp &= ~LP_WAKE;
+ I915_WRITE(MIPI_CTRL(port), tmp);
+ }
+
+ /* Set the MIPI mode */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(MIPI_CTRL(port));
+ I915_WRITE(MIPI_CTRL(port), tmp | MIPI_MODE);
+ }
+
+ /* Wait for Pwr ACK */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port), PWR_ACK, PWR_ACK, 20))
+ DRM_ERROR("Power ACK not received\n");
+ }
+
+ /* Wait for MIPI PHY status bit to set */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port), PHY_STATUS, PHY_STATUS, 20))
+ DRM_ERROR("PHY is not ON\n");
+ }
+
+ /* Get IO out of reset */
+ tmp = I915_READ(MIPI_CTRL(PORT_A));
+ I915_WRITE(MIPI_CTRL(PORT_A), tmp | MIPIIO_RESET);
+
+ /* Get IO out of Low power state*/
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= DEVICE_READY;
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
+ usleep_range(10, 15);
+ }
+
+ /* Enter ULPS */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_ENTER | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+ /* Wait for ULPS Not active */
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port), ULPS_NOT_ACTIVE, ULPS_NOT_ACTIVE, 20))
+
+ /* Exit ULPS */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_EXIT | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+ /* Enter Normal Mode */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+ tmp = I915_READ(MIPI_CTRL(port));
+ tmp &= ~LP_WAKE;
+ I915_WRITE(MIPI_CTRL(port), tmp);
+ }
+
+ /* Wait for Stop state */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port), DATA_LANE_STOP_STATE,
+ DATA_LANE_STOP_STATE, 20))
+ DRM_ERROR("Date lane not in STOP state\n");
+ }
+
+ /* Wait for AFE LATCH */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
+ AFE_LATCHOUT, 20))
+ DRM_ERROR("D-PHY not entering LP-11 state\n");
+ }
+}
+
static void bxt_dsi_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -559,6 +683,9 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
intel_dsi_prepare(encoder, pipe_config);
+ if (IS_GEMINILAKE(dev_priv))
+ intel_dsi_enable_mipiio(encoder);
+
/* Panel Enable over CRC PMIC */
if (intel_dsi->gpio_panel)
gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
@@ -699,6 +826,9 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
usleep_range(2000, 2500);
}
+ if (IS_GEMINILAKE(dev_priv))
+ intel_dsi_disable_mipiio(encoder);
+
intel_disable_dsi_pll(encoder);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [GLK MIPI DSI V1 4/9] drm/i915: Set the Z inversion overlap field
2016-12-08 8:49 [GLK MIPI DSI V1 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (2 preceding siblings ...)
2016-12-08 8:49 ` [GLK MIPI DSI V1 3/9] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
@ 2016-12-08 8:49 ` Madhav Chauhan
2016-12-08 8:49 ` [GLK MIPI DSI V1 5/9] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
` (5 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Madhav Chauhan @ 2016-12-08 8:49 UTC (permalink / raw)
To: intel-gfx
Cc: ander.conselvan.de.oliveira, jani.nikula, shobhit.kumar, Deepak M
From: Deepak M <m.deepak@intel.com>
Dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the older platforms,
hence setting the same in this patch.
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 729fcc9..27a0e73 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -579,12 +579,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
u32 temp;
-
- temp = I915_READ(VLV_CHICKEN_3);
- temp &= ~PIXEL_OVERLAP_CNT_MASK |
+ if (IS_GEN9_LP(dev_priv)) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ temp = I915_READ(MIPI_CTRL(port));
+ temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
+ intel_dsi->pixel_overlap <<
+ BXT_PIXEL_OVERLAP_CNT_SHIFT;
+ I915_WRITE(MIPI_CTRL(port), temp);
+ }
+ } else {
+ temp = I915_READ(VLV_CHICKEN_3);
+ temp &= ~PIXEL_OVERLAP_CNT_MASK |
intel_dsi->pixel_overlap <<
PIXEL_OVERLAP_CNT_SHIFT;
- I915_WRITE(VLV_CHICKEN_3, temp);
+ I915_WRITE(VLV_CHICKEN_3, temp);
+ }
}
for_each_dsi_port(port, intel_dsi->ports) {
--
1.9.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [GLK MIPI DSI V1 5/9] drm/i915/glk: Add DSI PLL divider range for glk
2016-12-08 8:49 [GLK MIPI DSI V1 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (3 preceding siblings ...)
2016-12-08 8:49 ` [GLK MIPI DSI V1 4/9] drm/i915: Set the Z inversion overlap field Madhav Chauhan
@ 2016-12-08 8:49 ` Madhav Chauhan
2016-12-08 8:50 ` [GLK MIPI DSI V1 6/9] drm/i915/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
` (4 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Madhav Chauhan @ 2016-12-08 8:49 UTC (permalink / raw)
To: intel-gfx
Cc: ander.conselvan.de.oliveira, jani.nikula, shobhit.kumar, Deepak M
From: Deepak M <m.deepak@intel.com>
PLL divider range for GLK is different than that of
BXT, hence adding the GLK range check in this patch.
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_dsi_pll.c | 20 ++++++++++++++------
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc6bb18..e83482b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8268,10 +8268,12 @@ enum {
#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
+#define BXT_DSIC_16X_BY1 (0 << 10)
#define BXT_DSIC_16X_BY2 (1 << 10)
#define BXT_DSIC_16X_BY3 (2 << 10)
#define BXT_DSIC_16X_BY4 (3 << 10)
#define BXT_DSIC_16X_MASK (3 << 10)
+#define BXT_DSIA_16X_BY1 (0 << 8)
#define BXT_DSIA_16X_BY2 (1 << 8)
#define BXT_DSIA_16X_BY3 (2 << 8)
#define BXT_DSIA_16X_BY4 (3 << 8)
@@ -8281,6 +8283,8 @@ enum {
#define BXT_DSI_PLL_RATIO_MAX 0x7D
#define BXT_DSI_PLL_RATIO_MIN 0x22
+#define GLK_DSI_PLL_RATIO_MAX 0x6F
+#define GLK_DSI_PLL_RATIO_MIN 0x22
#define BXT_DSI_PLL_RATIO_MASK 0xFF
#define BXT_REF_CLOCK_KHZ 19200
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index cf8c1b0..6fdd08c 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -428,9 +428,10 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
}
-static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
+static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
struct intel_crtc_state *config)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u8 dsi_ratio;
u32 dsi_clk;
@@ -444,11 +445,18 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
* round 'up' the result
*/
dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
- if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
- dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
+
+ if (IS_BROXTON(dev_priv) && (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
+ dsi_ratio > BXT_DSI_PLL_RATIO_MAX)) {
DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
return -ECHRNG;
- }
+ } else if (IS_GEMINILAKE(dev_priv) &&
+ (dsi_ratio < GLK_DSI_PLL_RATIO_MIN ||
+ dsi_ratio > GLK_DSI_PLL_RATIO_MAX)) {
+ DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
+ return -ECHRNG;
+ } else
+ DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
/*
* Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
@@ -460,7 +468,7 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
/* As per recommendation from hardware team,
* Prog PVD ratio =1 if dsi ratio <= 50
*/
- if (dsi_ratio <= 50)
+ if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
return 0;
@@ -520,7 +528,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_compute_dsi_pll(encoder, config);
else if (IS_GEN9_LP(dev_priv))
- return bxt_compute_dsi_pll(encoder, config);
+ return gen9lp_compute_dsi_pll(encoder, config);
return -ENODEV;
}
--
1.9.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [GLK MIPI DSI V1 6/9] drm/i915/glk: Program MIPI_CLOCK_CTRL only for BXT
2016-12-08 8:49 [GLK MIPI DSI V1 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (4 preceding siblings ...)
2016-12-08 8:49 ` [GLK MIPI DSI V1 5/9] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
@ 2016-12-08 8:50 ` Madhav Chauhan
2016-12-08 8:50 ` [GLK MIPI DSI V1 7/9] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
` (3 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Madhav Chauhan @ 2016-12-08 8:50 UTC (permalink / raw)
To: intel-gfx
Cc: ander.conselvan.de.oliveira, jani.nikula, shobhit.kumar, Deepak M
From: Deepak M <m.deepak@intel.com>
Register MIPI_CLOCK_CTRL is applicable only
for BXT platform. Future platform have other
registers to program the escape clock dividers.
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 6fdd08c..f37f61f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -489,8 +489,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
POSTING_READ(BXT_DSI_PLL_CTL);
/* Program TX, RX, Dphy clocks */
- for_each_dsi_port(port, intel_dsi->ports)
- bxt_dsi_program_clocks(encoder->base.dev, port, config);
+ if (IS_BROXTON(dev_priv)) {
+ for_each_dsi_port(port, intel_dsi->ports)
+ bxt_dsi_program_clocks(encoder->base.dev, port, config);
+ }
/* Enable DSI PLL */
val = I915_READ(BXT_DSI_PLL_ENABLE);
@@ -554,19 +556,22 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
bxt_disable_dsi_pll(encoder);
}
-static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
+static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
+ enum port port)
{
u32 tmp;
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
/* Clear old configurations */
- tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
- tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
- tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
- I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+ if (IS_BROXTON(dev_priv)) {
+ tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
+ tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
+ I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+ }
I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
}
@@ -575,7 +580,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (IS_GEN9_LP(dev_priv))
- bxt_dsi_reset_clocks(encoder, port);
+ gen9lp_dsi_reset_clocks(encoder, port);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_reset_clocks(encoder, port);
}
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread* [GLK MIPI DSI V1 7/9] drm/i915/glk: Program txesc clock divider for GLK
2016-12-08 8:49 [GLK MIPI DSI V1 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (5 preceding siblings ...)
2016-12-08 8:50 ` [GLK MIPI DSI V1 6/9] drm/i915/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
@ 2016-12-08 8:50 ` Madhav Chauhan
2016-12-08 8:50 ` [GLK MIPI DSI V1 8/9] drm/i915/glk: Program dphy param reg " Madhav Chauhan
` (2 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Madhav Chauhan @ 2016-12-08 8:50 UTC (permalink / raw)
To: intel-gfx
Cc: ander.conselvan.de.oliveira, jani.nikula, shobhit.kumar, Deepak M
From: Deepak M <m.deepak@intel.com>
Txesc clock divider is calculated and programmed
for geminilake platform.
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++
drivers/gpu/drm/i915/intel_dsi_pll.c | 61 ++++++++++++++++++++++++++++++++++--
2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e83482b..3d7483e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8182,6 +8182,11 @@ enum {
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
+#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
+#define TX_ESC_CLK_DIV1_MASK 0x3FF
+#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
+#define TX_ESC_CLK_DIV2_MASK 0x3FF
+
/* BXT MIPI clock controls */
#define BXT_MAX_VAR_OUTPUT_KHZ 39500
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index f37f61f..94ba8157 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -370,6 +370,53 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
ESCAPE_CLOCK_DIVIDER_SHIFT);
}
+static void glk_dsi_program_esc_clock(struct drm_device *dev,
+ const struct intel_crtc_state *config)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ u32 dsi_rate = 0;
+ u32 pll_ratio = 0;
+ u32 ddr_clk = 0;
+ u32 div1_value = 0;
+ u32 div2_value = 0;
+ u32 txesc1_div = 0;
+ u32 txesc2_div = 0;
+
+ pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
+
+ dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
+
+ ddr_clk = dsi_rate / 2;
+
+ /* Variable divider value */
+ div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
+
+ /* Calculate TXESC1 divider */
+ if (div1_value <= 10)
+ txesc1_div = div1_value;
+ else if ((div1_value > 10) && (div1_value <= 20))
+ txesc1_div = DIV_ROUND_UP(div1_value, 2);
+ else if ((div1_value > 20) && (div1_value <= 30))
+ txesc1_div = DIV_ROUND_UP(div1_value, 4);
+ else if ((div1_value > 30) && (div1_value <= 40))
+ txesc1_div = DIV_ROUND_UP(div1_value, 6);
+ else if ((div1_value > 40) && (div1_value <= 50))
+ txesc1_div = DIV_ROUND_UP(div1_value, 8);
+ else
+ txesc1_div = 10;
+
+ /* Calculate TXESC2 divider */
+ div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
+
+ if (div2_value < 10)
+ txesc2_div = div2_value;
+ else
+ txesc2_div = 10;
+
+ I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & TX_ESC_CLK_DIV1_MASK);
+ I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & TX_ESC_CLK_DIV2_MASK);
+}
+
/* Program BXT Mipi clocks and dividers */
static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
const struct intel_crtc_state *config)
@@ -474,7 +521,7 @@ static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
return 0;
}
-static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
+static void gen9lp_enable_dsi_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -492,6 +539,8 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
if (IS_BROXTON(dev_priv)) {
for_each_dsi_port(port, intel_dsi->ports)
bxt_dsi_program_clocks(encoder->base.dev, port, config);
+ } else {
+ glk_dsi_program_esc_clock(encoder->base.dev, config);
}
/* Enable DSI PLL */
@@ -543,7 +592,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_enable_dsi_pll(encoder, config);
else if (IS_GEN9_LP(dev_priv))
- bxt_enable_dsi_pll(encoder, config);
+ gen9lp_enable_dsi_pll(encoder, config);
}
void intel_disable_dsi_pll(struct intel_encoder *encoder)
@@ -571,6 +620,14 @@ static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+ } else {
+ tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
+ tmp &= ~TX_ESC_CLK_DIV1_MASK;
+ I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
+
+ tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
+ tmp &= ~TX_ESC_CLK_DIV2_MASK;
+ I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp);
}
I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [GLK MIPI DSI V1 8/9] drm/i915/glk: Program dphy param reg for GLK
2016-12-08 8:49 [GLK MIPI DSI V1 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (6 preceding siblings ...)
2016-12-08 8:50 ` [GLK MIPI DSI V1 7/9] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
@ 2016-12-08 8:50 ` Madhav Chauhan
2016-12-08 8:50 ` [GLK MIPI DSI V1 9/9] drm/915: Parsing the missed out DTD fields from the VBT Madhav Chauhan
2016-12-08 9:22 ` ✓ Fi.CI.BAT: success for GLK MIPI DSI VIDEO MODE PATCHES Patchwork
9 siblings, 0 replies; 15+ messages in thread
From: Madhav Chauhan @ 2016-12-08 8:50 UTC (permalink / raw)
To: intel-gfx; +Cc: ander.conselvan.de.oliveira, jani.nikula, shobhit.kumar
For GEMINILAKE, dphy param reg values are programmed in terms
of HS byte clock while for legacy platforms in terms of ddrclk
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 33 +++++++++++++++++++++++-------
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 0d8ff00..647eca4 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -668,16 +668,26 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
/* count values in UI = (ns value) * (bitrate / (2 * 10^6))
*
* Since txddrclkhs_i is 2xUI, all the count values programmed in
- * DPHY param register are divided by 2
+ * DPHY param register are divided by 2 except GEMINILAKE where it is
+ * programmed in terms of HS byte clock so divided by 8
*
* prepare count
*/
ths_prepare_ns = max(mipi_config->ths_prepare,
mipi_config->tclk_prepare);
- prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
+ if (IS_GEMINILAKE(dev_priv))
+ prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 8);
+ else
+ prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
/* exit zero count */
- exit_zero_cnt = DIV_ROUND_UP(
+ if (IS_GEMINILAKE(dev_priv))
+ exit_zero_cnt = DIV_ROUND_UP(
+ (ths_prepare_hszero - ths_prepare_ns) * ui_den,
+ ui_num * 8
+ );
+ else
+ exit_zero_cnt = DIV_ROUND_UP(
(ths_prepare_hszero - ths_prepare_ns) * ui_den,
ui_num * 2
);
@@ -692,13 +702,22 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
exit_zero_cnt += 1;
/* clk zero count */
- clk_zero_cnt = DIV_ROUND_UP(
- (tclk_prepare_clkzero - ths_prepare_ns)
- * ui_den, 2 * ui_num);
+ if (IS_GEMINILAKE(dev_priv))
+ clk_zero_cnt = DIV_ROUND_UP(
+ (tclk_prepare_clkzero - ths_prepare_ns)
+ * ui_den, 8 * ui_num);
+ else
+ clk_zero_cnt = DIV_ROUND_UP(
+ (tclk_prepare_clkzero - ths_prepare_ns)
+ * ui_den, 2 * ui_num);
/* trail count */
tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
- trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
+
+ if (IS_GEMINILAKE(dev_priv))
+ trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 8 * ui_num);
+ else
+ trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
if (prepare_cnt > PREPARE_CNT_MAX ||
exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
--
1.9.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* [GLK MIPI DSI V1 9/9] drm/915: Parsing the missed out DTD fields from the VBT
2016-12-08 8:49 [GLK MIPI DSI V1 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (7 preceding siblings ...)
2016-12-08 8:50 ` [GLK MIPI DSI V1 8/9] drm/i915/glk: Program dphy param reg " Madhav Chauhan
@ 2016-12-08 8:50 ` Madhav Chauhan
2016-12-08 9:22 ` ✓ Fi.CI.BAT: success for GLK MIPI DSI VIDEO MODE PATCHES Patchwork
9 siblings, 0 replies; 15+ messages in thread
From: Madhav Chauhan @ 2016-12-08 8:50 UTC (permalink / raw)
To: intel-gfx
Cc: ander.conselvan.de.oliveira, jani.nikula, shobhit.kumar,
Vincente Tsou
From: Vincente Tsou <vincente.tsou@intel.com>
The upper bits of the vsync width, vsync offset and hsync width
were not parsed form the VBT. Parse these fields in this patch.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vincente Tsou <vincente.tsou@intel.com>
---
drivers/gpu/drm/i915/intel_bios.c | 8 +++++---
drivers/gpu/drm/i915/intel_vbt_defs.h | 6 ++++--
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index eaade27..e1d014b 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -114,16 +114,18 @@ static u32 get_blocksize(const void *block_data)
panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
- dvo_timing->hsync_pulse_width;
+ ((dvo_timing->hsync_pulse_width_hi << 8) |
+ dvo_timing->hsync_pulse_width);
panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
dvo_timing->vactive_lo;
panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
- dvo_timing->vsync_off;
+ ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off);
panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
- dvo_timing->vsync_pulse_width;
+ ((dvo_timing->vsync_pulse_width_hi << 4) |
+ dvo_timing->vsync_pulse_width);
panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
panel_fixed_mode->clock = dvo_timing->clock * 10;
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 8886cab1..bf9d2d3 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -402,7 +402,9 @@ struct lvds_dvo_timing {
u8 hsync_pulse_width;
u8 vsync_pulse_width:4;
u8 vsync_off:4;
- u8 rsvd0:6;
+ u8 vsync_pulse_width_hi:2;
+ u8 vsync_off_hi:2;
+ u8 hsync_pulse_width_hi:2;
u8 hsync_off_hi:2;
u8 himage_lo;
u8 vimage_lo;
@@ -414,7 +416,7 @@ struct lvds_dvo_timing {
u8 digital:2;
u8 vsync_positive:1;
u8 hsync_positive:1;
- u8 rsvd2:1;
+ u8 interlaced:1;
} __packed;
struct lvds_pnp_id {
--
1.9.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread* ✓ Fi.CI.BAT: success for GLK MIPI DSI VIDEO MODE PATCHES
2016-12-08 8:49 [GLK MIPI DSI V1 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (8 preceding siblings ...)
2016-12-08 8:50 ` [GLK MIPI DSI V1 9/9] drm/915: Parsing the missed out DTD fields from the VBT Madhav Chauhan
@ 2016-12-08 9:22 ` Patchwork
9 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2016-12-08 9:22 UTC (permalink / raw)
To: Madhav Chauhan; +Cc: intel-gfx
== Series Details ==
Series: GLK MIPI DSI VIDEO MODE PATCHES
URL : https://patchwork.freedesktop.org/series/16542/
State : success
== Summary ==
Series 16542v1 GLK MIPI DSI VIDEO MODE PATCHES
https://patchwork.freedesktop.org/api/1.0/series/16542/revisions/1/mbox/
fi-bdw-5557u total:247 pass:219 dwarn:0 dfail:0 fail:0 skip:28
fi-bsw-n3050 total:247 pass:195 dwarn:0 dfail:0 fail:0 skip:52
fi-bxt-t5700 total:247 pass:206 dwarn:0 dfail:0 fail:0 skip:41
fi-byt-j1900 total:247 pass:206 dwarn:0 dfail:0 fail:0 skip:41
fi-byt-n2820 total:247 pass:202 dwarn:0 dfail:0 fail:0 skip:45
fi-hsw-4770 total:247 pass:214 dwarn:0 dfail:0 fail:0 skip:33
fi-hsw-4770r total:247 pass:214 dwarn:0 dfail:0 fail:0 skip:33
fi-ilk-650 total:247 pass:181 dwarn:0 dfail:0 fail:0 skip:66
fi-ivb-3520m total:247 pass:213 dwarn:0 dfail:0 fail:0 skip:34
fi-ivb-3770 total:247 pass:212 dwarn:0 dfail:0 fail:0 skip:35
fi-kbl-7500u total:247 pass:212 dwarn:0 dfail:0 fail:0 skip:35
fi-skl-6260u total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27
fi-skl-6700hq total:247 pass:214 dwarn:0 dfail:0 fail:0 skip:33
fi-skl-6700k total:247 pass:210 dwarn:3 dfail:0 fail:0 skip:34
fi-skl-6770hq total:247 pass:220 dwarn:0 dfail:0 fail:0 skip:27
fi-snb-2520m total:247 pass:202 dwarn:0 dfail:0 fail:0 skip:45
fi-snb-2600 total:247 pass:201 dwarn:0 dfail:0 fail:0 skip:46
ffcd96e45b3b3e4ca57d4879405d02b7b1b58946 drm-tip: 2016y-12m-07d-21h-45m-40s UTC integration manifest
1dc936f drm/915: Parsing the missed out DTD fields from the VBT
d8e70e0 drm/i915/glk: Program dphy param reg for GLK
aef354d drm/i915/glk: Program txesc clock divider for GLK
e1142a4 drm/i915/glk: Program MIPI_CLOCK_CTRL only for BXT
6d35420 drm/i915/glk: Add DSI PLL divider range for glk
f8c63e3 drm/i915: Set the Z inversion overlap field
a5f966d drm/i915/glk: Add MIPIIO Enable/disable sequence
e2032f6 drm/i915/glk: Program new MIPI DSI PHY registers for GLK
7672e79 drm/i915/glk: Add new bit fields in MIPI CTRL register
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3231/
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^ permalink raw reply [flat|nested] 15+ messages in thread