[PATCH 0/9] Don't whitelist OA registers unconditionally

[PATCH 0/9] Don't whitelist OA registers unconditionally

[Ashutosh Dixit]

Whitelisting OA registers unconditionally is a security violation. In this
series we resolve this issue as follows:

* Set the 'deny' bit (bit 30) for all OA registers, ensuring OA registers
  are not whitelisted by default after probe/reset/restart
* Reset the 'deny' bit when an OA stream is opened and certain conditions
  are met, whitelisting OA registers only for the duration when OA streams
  are open for a gt
* Set the 'deny' bit again, when OA streams are closed
* To manage this scheme, separate out OA whitelists from non-OA whitelists
  (into separate save-restore lists)

Ashutosh Dixit (9):
  drm/xe/rtp: Add RING_FORCE_TO_NONPRIV_DENY to OA whitelists
  drm/xe/rtp: Maintain OA whitelists separately
  drm/xe/rtp: Keep track of non-OA nonpriv slots
  drm/xe/rtp: Generalize whitelist_apply_to_hwe
  drm/xe/rtp: Save OA nonpriv registers to register save/restore lists
  drm/xe/rtp: Toggle 'deny' bit to (de-)whitelist OA regs
  drm/xe/rtp: (De-)whitelist OA registers for all hwe's for a gt
  drm/xe/oa: (De-)whitelist OA registers on OA stream open/release
  drm/xe/rtp: Ensure locking/ref counting for OA whitelists

 drivers/gpu/drm/xe/xe_gt_debugfs.c      |  4 +-
 drivers/gpu/drm/xe/xe_hw_engine.c       |  2 +
 drivers/gpu/drm/xe/xe_hw_engine_types.h |  8 +++
 drivers/gpu/drm/xe/xe_oa.c              |  7 ++
 drivers/gpu/drm/xe/xe_oa_types.h        |  3 +
 drivers/gpu/drm/xe/xe_reg_whitelist.c   | 92 ++++++++++++++++++++++---
 drivers/gpu/drm/xe/xe_reg_whitelist.h   |  4 ++
 7 files changed, 111 insertions(+), 9 deletions(-)

-- 
2.54.0

[PATCH 1/9] drm/xe/rtp: Add RING_FORCE_TO_NONPRIV_DENY to OA whitelists

[Ashutosh Dixit]

Unconditionally whitelisting OA registers is a security violation. Set
RING_FORCE_TO_NONPRIV_DENY bit in OA nonpriv slots, so that OA registers
don't get whitelisted by default after probe/reset/restart.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index fb65940848d7a..d6a5d499373bc 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -105,9 +105,10 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
 	},
 
 #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
-	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
-	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \
-	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4)
+	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW | RING_FORCE_TO_NONPRIV_DENY), \
+	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_DENY), \
+	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4 | \
+		  RING_FORCE_TO_NONPRIV_DENY)
 
 #define WHITELIST_OAG_MMIO_TRG \
 	WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR)
-- 
2.54.0

Re: [PATCH 1/9] drm/xe/rtp: Add RING_FORCE_TO_NONPRIV_DENY to OA whitelists

[Umesh Nerlige Ramappa]

On Mon, May 18, 2026 at 04:47:08PM -0700, Ashutosh Dixit wrote:
>Unconditionally whitelisting OA registers is a security violation. Set
>RING_FORCE_TO_NONPRIV_DENY bit in OA nonpriv slots, so that OA registers
>don't get whitelisted by default after probe/reset/restart.
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>---
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>index fb65940848d7a..d6a5d499373bc 100644
>--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>@@ -105,9 +105,10 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
> 	},
>
> #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
>-	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
>-	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \
>-	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4)
>+	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW | RING_FORCE_TO_NONPRIV_DENY), \
>+	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_DENY), \
>+	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4 | \
>+		  RING_FORCE_TO_NONPRIV_DENY)

status and head should be clubbed into one slot, starting with status 
and RANGE_4. Maybe that can be a patch before this one.

Umesh
>
> #define WHITELIST_OAG_MMIO_TRG \
> 	WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR)
>-- 
>2.54.0
>

Re: [PATCH 1/9] drm/xe/rtp: Add RING_FORCE_TO_NONPRIV_DENY to OA whitelists

[Dixit, Ashutosh]

On Thu, 21 May 2026 16:14:50 -0700, Umesh Nerlige Ramappa wrote:
>
> On Mon, May 18, 2026 at 04:47:08PM -0700, Ashutosh Dixit wrote:
> > Unconditionally whitelisting OA registers is a security violation. Set
> > RING_FORCE_TO_NONPRIV_DENY bit in OA nonpriv slots, so that OA registers
> > don't get whitelisted by default after probe/reset/restart.
> >
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > index fb65940848d7a..d6a5d499373bc 100644
> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > @@ -105,9 +105,10 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
> >	},
> >
> > #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
> > -	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
> > -	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \
> > -	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4)
> > +	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW | RING_FORCE_TO_NONPRIV_DENY), \
> > +	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_DENY), \
> > +	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4 | \
> > +		  RING_FORCE_TO_NONPRIV_DENY)
>
> status and head should be clubbed into one slot, starting with status and
> RANGE_4. Maybe that can be a patch before this one.

No, e.g. for OAG, status is 0xdafc which is not a multiple of 16, which is
a requirement for RANGE_4.

Also, about RANGE_4 above, there were different suggestions, e.g. tail and
oabuffer should be different slots, rather than grouping in a single
RANGE_4 above. To avoid any such controversy, I decided to focus this
series only on removing unconditional whitelisting for OA registers. Any
other changes, such as removing or retaining RANGE_4, we can do after this
series is reviewed/merged.

Thanks.
--
Ashutosh

> > #define WHITELIST_OAG_MMIO_TRG \
> >	WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR)
> > --
> > 2.54.0
> >

Re: [PATCH 1/9] drm/xe/rtp: Add RING_FORCE_TO_NONPRIV_DENY to OA whitelists

[Umesh Nerlige Ramappa]

On Thu, May 21, 2026 at 04:35:25PM -0700, Dixit, Ashutosh wrote:
>On Thu, 21 May 2026 16:14:50 -0700, Umesh Nerlige Ramappa wrote:
>>
>> On Mon, May 18, 2026 at 04:47:08PM -0700, Ashutosh Dixit wrote:
>> > Unconditionally whitelisting OA registers is a security violation. Set
>> > RING_FORCE_TO_NONPRIV_DENY bit in OA nonpriv slots, so that OA registers
>> > don't get whitelisted by default after probe/reset/restart.
>> >
>> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>> > ---
>> > drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 ++++---
>> > 1 file changed, 4 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> > index fb65940848d7a..d6a5d499373bc 100644
>> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> > @@ -105,9 +105,10 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
>> >	},
>> >
>> > #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
>> > -	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
>> > -	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \
>> > -	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4)
>> > +	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW | RING_FORCE_TO_NONPRIV_DENY), \
>> > +	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_DENY), \
>> > +	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4 | \
>> > +		  RING_FORCE_TO_NONPRIV_DENY)
>>
>> status and head should be clubbed into one slot, starting with status and
>> RANGE_4. Maybe that can be a patch before this one.
>
>No, e.g. for OAG, status is 0xdafc which is not a multiple of 16, which is
>a requirement for RANGE_4.

I missed that. I thought HW compared ranges differently. In that case, 
this is correct and the individual registers can be whitelisted 
separately if needed. Otherwise some registers can be dropped whenever 
you plan to do it.

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>


Umesh.
>
>Also, about RANGE_4 above, there were different suggestions, e.g. tail and
>oabuffer should be different slots, rather than grouping in a single
>RANGE_4 above. To avoid any such controversy, I decided to focus this
>series only on removing unconditional whitelisting for OA registers. Any
>other changes, such as removing or retaining RANGE_4, we can do after this
>series is reviewed/merged.
>
>Thanks.
>--
>Ashutosh
>
>> > #define WHITELIST_OAG_MMIO_TRG \
>> >	WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR)
>> > --
>> > 2.54.0
>> >

Re: [PATCH 1/9] drm/xe/rtp: Add RING_FORCE_TO_NONPRIV_DENY to OA whitelists

[Umesh Nerlige Ramappa]

On Tue, May 26, 2026 at 12:12:33PM -0700, Umesh Nerlige Ramappa wrote:
>On Thu, May 21, 2026 at 04:35:25PM -0700, Dixit, Ashutosh wrote:
>>On Thu, 21 May 2026 16:14:50 -0700, Umesh Nerlige Ramappa wrote:
>>>
>>>On Mon, May 18, 2026 at 04:47:08PM -0700, Ashutosh Dixit wrote:
>>>> Unconditionally whitelisting OA registers is a security violation. Set
>>>> RING_FORCE_TO_NONPRIV_DENY bit in OA nonpriv slots, so that OA registers
>>>> don't get whitelisted by default after probe/reset/restart.

probe/gt-reset/resume to be precise. During resume and gt-reset flows 
KMD will apply the reg_sr to mmio, so you are ensuring DENY is enforced 
in these paths as well. As for engine-reset, the hwe->reg_sr is 
registered with GuC and GuC will save and restore these values.

Some of this info would be helpful in the commit messages OR comments to 
understand the bigger picture (for reviewers at least)

Thanks,
Umesh

>>>>
>>>> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>>>> ---
>>>> drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 ++++---
>>>> 1 file changed, 4 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>>>> index fb65940848d7a..d6a5d499373bc 100644
>>>> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>>>> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>>>> @@ -105,9 +105,10 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
>>>>	},
>>>>
>>>> #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
>>>> -	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
>>>> -	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \
>>>> -	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4)
>>>> +	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW | RING_FORCE_TO_NONPRIV_DENY), \
>>>> +	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_DENY), \
>>>> +	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4 | \
>>>> +		  RING_FORCE_TO_NONPRIV_DENY)
>>>
>>>status and head should be clubbed into one slot, starting with status and
>>>RANGE_4. Maybe that can be a patch before this one.
>>
>>No, e.g. for OAG, status is 0xdafc which is not a multiple of 16, which is
>>a requirement for RANGE_4.
>
>I missed that. I thought HW compared ranges differently. In that case, 
>this is correct and the individual registers can be whitelisted 
>separately if needed. Otherwise some registers can be dropped whenever 
>you plan to do it.
>
>Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>
>
>Umesh.
>>
>>Also, about RANGE_4 above, there were different suggestions, e.g. tail and
>>oabuffer should be different slots, rather than grouping in a single
>>RANGE_4 above. To avoid any such controversy, I decided to focus this
>>series only on removing unconditional whitelisting for OA registers. Any
>>other changes, such as removing or retaining RANGE_4, we can do after this
>>series is reviewed/merged.
>>
>>Thanks.
>>--
>>Ashutosh
>>
>>>> #define WHITELIST_OAG_MMIO_TRG \
>>>>	WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR)
>>>> --
>>>> 2.54.0
>>>>

Re: [PATCH 1/9] drm/xe/rtp: Add RING_FORCE_TO_NONPRIV_DENY to OA whitelists

[Dixit, Ashutosh]

On Wed, 27 May 2026 13:03:53 -0700, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> On Tue, May 26, 2026 at 12:12:33PM -0700, Umesh Nerlige Ramappa wrote:
> > On Thu, May 21, 2026 at 04:35:25PM -0700, Dixit, Ashutosh wrote:
> >> On Thu, 21 May 2026 16:14:50 -0700, Umesh Nerlige Ramappa wrote:
> >>>
> >>> On Mon, May 18, 2026 at 04:47:08PM -0700, Ashutosh Dixit wrote:
> >>>> Unconditionally whitelisting OA registers is a security violation. Set
> >>>> RING_FORCE_TO_NONPRIV_DENY bit in OA nonpriv slots, so that OA registers
> >>>> don't get whitelisted by default after probe/reset/restart.
>
> probe/gt-reset/resume to be precise.

Yes, good idea, I'll change these and maybe add a comment too near
WHITELIST_OA_MMIO_TRG().

> During resume and gt-reset flows KMD will apply the reg_sr to mmio, so
> you are ensuring DENY is enforced in these paths as well. As for
> engine-reset, the hwe->reg_sr is registered with GuC and GuC will save
> and restore these values.
>

This will likely need to go to Patch 5 ("drm/xe/rtp: Save OA nonpriv
registers to register save/restore lists"), let me see. I already added a
hint there, but will see if the commit message can be improved in the next
rev. We can take a look again at v2.

> Some of this info would be helpful in the commit messages OR comments to
> understand the bigger picture (for reviewers at least)

Thanks.
--
Ashutosh



>
> >>>>
> >>>> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> >>>> ---
> >>>> drivers/gpu/drm/xe/xe_reg_whitelist.c | 7 ++++---
> >>>> 1 file changed, 4 insertions(+), 3 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> >>>> index fb65940848d7a..d6a5d499373bc 100644
> >>>> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> >>>> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> >>>> @@ -105,9 +105,10 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
> >>>>	},
> >>>>
> >>>> #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
> >>>> -	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
> >>>> -	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD), \
> >>>> -	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4)
> >>>> +	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW | RING_FORCE_TO_NONPRIV_DENY), \
> >>>> +	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_DENY), \
> >>>> +	WHITELIST(head, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4 | \
> >>>> +		  RING_FORCE_TO_NONPRIV_DENY)
> >>>
> >>> status and head should be clubbed into one slot, starting with status and
> >>> RANGE_4. Maybe that can be a patch before this one.
> >>
> >> No, e.g. for OAG, status is 0xdafc which is not a multiple of 16, which is
> >> a requirement for RANGE_4.
> >
> > I missed that. I thought HW compared ranges differently. In that case,
> > this is correct and the individual registers can be whitelisted
> > separately if needed. Otherwise some registers can be dropped whenever
> > you plan to do it.
> >
> > Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> >
> >
> > Umesh.
> >>
> >> Also, about RANGE_4 above, there were different suggestions, e.g. tail and
> >> oabuffer should be different slots, rather than grouping in a single
> >> RANGE_4 above. To avoid any such controversy, I decided to focus this
> >> series only on removing unconditional whitelisting for OA registers. Any
> >> other changes, such as removing or retaining RANGE_4, we can do after this
> >> series is reviewed/merged.
> >>
> >> Thanks.
> >> --
> >> Ashutosh
> >>
> >>>> #define WHITELIST_OAG_MMIO_TRG \
> >>>>	WHITELIST_OA_MMIO_TRG(OAG_MMIOTRIGGER, OAG_OASTATUS, OAG_OAHEADPTR)
> >>>> --
> >>>> 2.54.0
> >>>>

[PATCH 2/9] drm/xe/rtp: Maintain OA whitelists separately

[Ashutosh Dixit]

OA registers are dynamically whitelisted (and again dewhitelisted) on OA
stream open/close. Maintaining OA whitelists separately from non-OA
register whitlists simplifies this management of OA register
whitelisting/dewhitelisting.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_debugfs.c      | 4 +++-
 drivers/gpu/drm/xe/xe_hw_engine.c       | 2 ++
 drivers/gpu/drm/xe/xe_hw_engine_types.h | 8 ++++++++
 drivers/gpu/drm/xe/xe_reg_whitelist.c   | 5 +++++
 4 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
index f45306308cd66..c38bcacb27e4a 100644
--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
@@ -149,8 +149,10 @@ static int register_save_restore(struct xe_gt *gt, struct drm_printer *p)
 	drm_printf(p, "\n");
 
 	drm_printf(p, "Whitelist\n");
-	for_each_hw_engine(hwe, gt, id)
+	for_each_hw_engine(hwe, gt, id) {
 		xe_reg_whitelist_dump(&hwe->reg_whitelist, p);
+		xe_reg_whitelist_dump(&hwe->oa_whitelist, p);
+	}
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 05f0932dbb948..9b0175ef05093 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -569,6 +569,8 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
 	hw_engine_setup_default_state(hwe);
 
 	xe_reg_sr_init(&hwe->reg_whitelist, hwe->name, gt_to_xe(gt));
+	xe_reg_sr_init(&hwe->oa_whitelist, hwe->name, gt_to_xe(gt));
+	xe_reg_sr_init(&hwe->oa_sr, hwe->name, gt_to_xe(gt));
 	xe_reg_whitelist_process_engine(hwe);
 }
 
diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h
index 0f87128c65290..3499bc09ee219 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
+++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
@@ -128,6 +128,14 @@ struct xe_hw_engine {
 	 * @reg_whitelist: table with registers to be whitelisted
 	 */
 	struct xe_reg_sr reg_whitelist;
+	/**
+	 * @oa_whitelist: oa registers to be whitelisted
+	 */
+	struct xe_reg_sr oa_whitelist;
+	/**
+	 * @oa_sr: oa nonpriv whitelist registers, changed on oa stream open/close
+	 */
+	struct xe_reg_sr oa_sr;
 	/**
 	 * @reg_lrc: LRC workaround registers
 	 */
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index d6a5d499373bc..6cc81f53fc601 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -103,7 +103,9 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
 			 WHITELIST(VFLSKPD,
 				   RING_FORCE_TO_NONPRIV_ACCESS_RW))
 	},
+};
 
+static const struct xe_rtp_entry_sr oa_whitelist[] = {
 #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
 	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW | RING_FORCE_TO_NONPRIV_DENY), \
 	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_DENY), \
@@ -206,6 +208,9 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
 	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
 			     &hwe->reg_whitelist, false);
 	whitelist_apply_to_hwe(hwe);
+
+	xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist),
+			     &hwe->oa_whitelist, false);
 }
 
 /**
-- 
2.54.0

Re: [PATCH 2/9] drm/xe/rtp: Maintain OA whitelists separately

[Umesh Nerlige Ramappa]

On Mon, May 18, 2026 at 04:47:09PM -0700, Ashutosh Dixit wrote:
>OA registers are dynamically whitelisted (and again dewhitelisted) on OA
>stream open/close. Maintaining OA whitelists separately from non-OA
>register whitlists simplifies this management of OA register
>whitelisting/dewhitelisting.
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

LGTM,

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

>---
> drivers/gpu/drm/xe/xe_gt_debugfs.c      | 4 +++-
> drivers/gpu/drm/xe/xe_hw_engine.c       | 2 ++
> drivers/gpu/drm/xe/xe_hw_engine_types.h | 8 ++++++++
> drivers/gpu/drm/xe/xe_reg_whitelist.c   | 5 +++++
> 4 files changed, 18 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_gt_debugfs.c b/drivers/gpu/drm/xe/xe_gt_debugfs.c
>index f45306308cd66..c38bcacb27e4a 100644
>--- a/drivers/gpu/drm/xe/xe_gt_debugfs.c
>+++ b/drivers/gpu/drm/xe/xe_gt_debugfs.c
>@@ -149,8 +149,10 @@ static int register_save_restore(struct xe_gt *gt, struct drm_printer *p)
> 	drm_printf(p, "\n");
>
> 	drm_printf(p, "Whitelist\n");
>-	for_each_hw_engine(hwe, gt, id)
>+	for_each_hw_engine(hwe, gt, id) {
> 		xe_reg_whitelist_dump(&hwe->reg_whitelist, p);
>+		xe_reg_whitelist_dump(&hwe->oa_whitelist, p);
>+	}
>
> 	return 0;
> }
>diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>index 05f0932dbb948..9b0175ef05093 100644
>--- a/drivers/gpu/drm/xe/xe_hw_engine.c
>+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>@@ -569,6 +569,8 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
> 	hw_engine_setup_default_state(hwe);
>
> 	xe_reg_sr_init(&hwe->reg_whitelist, hwe->name, gt_to_xe(gt));
>+	xe_reg_sr_init(&hwe->oa_whitelist, hwe->name, gt_to_xe(gt));
>+	xe_reg_sr_init(&hwe->oa_sr, hwe->name, gt_to_xe(gt));
> 	xe_reg_whitelist_process_engine(hwe);
> }
>
>diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h
>index 0f87128c65290..3499bc09ee219 100644
>--- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
>+++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
>@@ -128,6 +128,14 @@ struct xe_hw_engine {
> 	 * @reg_whitelist: table with registers to be whitelisted
> 	 */
> 	struct xe_reg_sr reg_whitelist;
>+	/**
>+	 * @oa_whitelist: oa registers to be whitelisted
>+	 */
>+	struct xe_reg_sr oa_whitelist;
>+	/**
>+	 * @oa_sr: oa nonpriv whitelist registers, changed on oa stream open/close
>+	 */
>+	struct xe_reg_sr oa_sr;
> 	/**
> 	 * @reg_lrc: LRC workaround registers
> 	 */
>diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>index d6a5d499373bc..6cc81f53fc601 100644
>--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>@@ -103,7 +103,9 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
> 			 WHITELIST(VFLSKPD,
> 				   RING_FORCE_TO_NONPRIV_ACCESS_RW))
> 	},
>+};
>
>+static const struct xe_rtp_entry_sr oa_whitelist[] = {
> #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
> 	WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW | RING_FORCE_TO_NONPRIV_DENY), \
> 	WHITELIST(status, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_DENY), \
>@@ -206,6 +208,9 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
> 	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
> 			     &hwe->reg_whitelist, false);
> 	whitelist_apply_to_hwe(hwe);
>+
>+	xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist),
>+			     &hwe->oa_whitelist, false);
> }
>
> /**
>-- 
>2.54.0
>

[PATCH 3/9] drm/xe/rtp: Keep track of non-OA nonpriv slots

[Ashutosh Dixit]

In order to dynamically whitelist/dewhitelist OA registers on OA stream
open/close, we need to keep track of nonpriv slots occupied by non-OA
register whitelists.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 6cc81f53fc601..1e788e2ee4014 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -159,7 +159,7 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = {
 	},
 };
 
-static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
+static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
 {
 	struct xe_reg_sr *sr = &hwe->reg_whitelist;
 	struct xe_reg_sr_entry *entry;
@@ -191,6 +191,8 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
 
 		slot++;
 	}
+
+	return slot;
 }
 
 /**
@@ -203,11 +205,13 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
  */
 void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
 {
+	int nonpriv_slots;
+
 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
 
 	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
 			     &hwe->reg_whitelist, false);
-	whitelist_apply_to_hwe(hwe);
+	nonpriv_slots = whitelist_apply_to_hwe(hwe);
 
 	xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist),
 			     &hwe->oa_whitelist, false);
-- 
2.54.0

Re: [PATCH 3/9] drm/xe/rtp: Keep track of non-OA nonpriv slots

[Umesh Nerlige Ramappa]

On Mon, May 18, 2026 at 04:47:10PM -0700, Ashutosh Dixit wrote:
>In order to dynamically whitelist/dewhitelist OA registers on OA stream
>open/close, we need to keep track of nonpriv slots occupied by non-OA
>register whitelists.

Can we maintain the slot index within hwe, so that the caller does not 
need to keep track of it? I am assuming this will only be used in the 
probe path. For all other paths the *_sr registers are used directly 
which already have the registre<->slot association stored within them.

i.e.

hwe->slot;

Regards,
Umesh
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>---
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>index 6cc81f53fc601..1e788e2ee4014 100644
>--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>@@ -159,7 +159,7 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = {
> 	},
> };
>
>-static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
>+static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
> {
> 	struct xe_reg_sr *sr = &hwe->reg_whitelist;
> 	struct xe_reg_sr_entry *entry;
>@@ -191,6 +191,8 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
>
> 		slot++;
> 	}
>+
>+	return slot;
> }
>
> /**
>@@ -203,11 +205,13 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
>  */
> void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
> {
>+	int nonpriv_slots;
>+
> 	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>
> 	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
> 			     &hwe->reg_whitelist, false);
>-	whitelist_apply_to_hwe(hwe);
>+	nonpriv_slots = whitelist_apply_to_hwe(hwe);
>
> 	xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist),
> 			     &hwe->oa_whitelist, false);
>-- 
>2.54.0
>

Re: [PATCH 3/9] drm/xe/rtp: Keep track of non-OA nonpriv slots

[Dixit, Ashutosh]

On Fri, 29 May 2026 11:30:34 -0700, Umesh Nerlige Ramappa wrote:
>
> On Mon, May 18, 2026 at 04:47:10PM -0700, Ashutosh Dixit wrote:
> > In order to dynamically whitelist/dewhitelist OA registers on OA stream
> > open/close, we need to keep track of nonpriv slots occupied by non-OA
> > register whitelists.
>
> Can we maintain the slot index within hwe, so that the caller does not need
> to keep track of it? I am assuming this will only be used in the probe
> path. For all other paths the *_sr registers are used directly which
> already have the registre<->slot association stored within them.
>
> i.e.
>
> hwe->slot;

Hmm, when I first wrote the code, I had this in hwe: hwe->nonpriv_slots.
But later realized it is only needed in xe_reg_whitelist_process_engine(),
so moved it to the local variable nonpriv_slots there.

Also, nonpriv_slots is actually number of slots occupied by non-OA
registers. So if it part of hwe, the question becomes more complicated:
what do we store there, number of slots excluding OA or including OA? Since
we only need number of slots excluding OA.

Therefore, to avoid these complications, I decided that the best way was a
temporary local variable.

What do you think we'd gain by maintaining it as part of hwe? If things
change later, we could add it, but for now the local variable seems
sufficient?

Thanks.
--
Ashutosh

> >
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 ++++++--
> > 1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > index 6cc81f53fc601..1e788e2ee4014 100644
> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > @@ -159,7 +159,7 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = {
> >	},
> > };
> >
> > -static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
> > +static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
> > {
> >	struct xe_reg_sr *sr = &hwe->reg_whitelist;
> >	struct xe_reg_sr_entry *entry;
> > @@ -191,6 +191,8 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
> >
> >		slot++;
> >	}
> > +
> > +	return slot;
> > }
> >
> > /**
> > @@ -203,11 +205,13 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
> >  */
> > void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
> > {
> > +	int nonpriv_slots;
> > +
> >	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
> >
> >	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
> >			     &hwe->reg_whitelist, false);
> > -	whitelist_apply_to_hwe(hwe);
> > +	nonpriv_slots = whitelist_apply_to_hwe(hwe);
> >
> >	xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist),
> >			     &hwe->oa_whitelist, false);
> > --
> > 2.54.0
> >

Re: [PATCH 3/9] drm/xe/rtp: Keep track of non-OA nonpriv slots

[Umesh Nerlige Ramappa]

On Fri, May 29, 2026 at 01:45:12PM -0700, Dixit, Ashutosh wrote:
>On Fri, 29 May 2026 11:30:34 -0700, Umesh Nerlige Ramappa wrote:
>>
>> On Mon, May 18, 2026 at 04:47:10PM -0700, Ashutosh Dixit wrote:
>> > In order to dynamically whitelist/dewhitelist OA registers on OA stream
>> > open/close, we need to keep track of nonpriv slots occupied by non-OA
>> > register whitelists.
>>
>> Can we maintain the slot index within hwe, so that the caller does not need
>> to keep track of it? I am assuming this will only be used in the probe
>> path. For all other paths the *_sr registers are used directly which
>> already have the registre<->slot association stored within them.
>>
>> i.e.
>>
>> hwe->slot;
>
>Hmm, when I first wrote the code, I had this in hwe: hwe->nonpriv_slots.
>But later realized it is only needed in xe_reg_whitelist_process_engine(),
>so moved it to the local variable nonpriv_slots there.
>
>Also, nonpriv_slots is actually number of slots occupied by non-OA
>registers. So if it part of hwe, the question becomes more complicated:
>what do we store there, number of slots excluding OA or including OA? Since
>we only need number of slots excluding OA.

I would just think of it as the next available nonpriv slot for the 
caller to use. It's just a state w.r.t the hwe. When you let the caller 
(even if internal to the KMD) manage it, it's prone to errors - not 
about this series or current code, but in general.

Thanks,
Umesh

>
>Therefore, to avoid these complications, I decided that the best way was a
>temporary local variable.
>
>What do you think we'd gain by maintaining it as part of hwe? If things
>change later, we could add it, but for now the local variable seems
>sufficient?

>
>Thanks.
>--
>Ashutosh
>
>> >
>> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>> > ---
>> > drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 ++++++--
>> > 1 file changed, 6 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> > index 6cc81f53fc601..1e788e2ee4014 100644
>> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> > @@ -159,7 +159,7 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = {
>> >	},
>> > };
>> >
>> > -static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
>> > +static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
>> > {
>> >	struct xe_reg_sr *sr = &hwe->reg_whitelist;
>> >	struct xe_reg_sr_entry *entry;
>> > @@ -191,6 +191,8 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
>> >
>> >		slot++;
>> >	}
>> > +
>> > +	return slot;
>> > }
>> >
>> > /**
>> > @@ -203,11 +205,13 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
>> >  */
>> > void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
>> > {
>> > +	int nonpriv_slots;
>> > +
>> >	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
>> >
>> >	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
>> >			     &hwe->reg_whitelist, false);
>> > -	whitelist_apply_to_hwe(hwe);
>> > +	nonpriv_slots = whitelist_apply_to_hwe(hwe);
>> >
>> >	xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist),
>> >			     &hwe->oa_whitelist, false);
>> > --
>> > 2.54.0
>> >

Re: [PATCH 3/9] drm/xe/rtp: Keep track of non-OA nonpriv slots

[Dixit, Ashutosh]

On Fri, 29 May 2026 16:24:30 -0700, Umesh Nerlige Ramappa wrote:
>
> On Fri, May 29, 2026 at 01:45:12PM -0700, Dixit, Ashutosh wrote:
> > On Fri, 29 May 2026 11:30:34 -0700, Umesh Nerlige Ramappa wrote:
> >>
> >> On Mon, May 18, 2026 at 04:47:10PM -0700, Ashutosh Dixit wrote:
> >> > In order to dynamically whitelist/dewhitelist OA registers on OA stream
> >> > open/close, we need to keep track of nonpriv slots occupied by non-OA
> >> > register whitelists.
> >>
> >> Can we maintain the slot index within hwe, so that the caller does not need
> >> to keep track of it? I am assuming this will only be used in the probe
> >> path. For all other paths the *_sr registers are used directly which
> >> already have the registre<->slot association stored within them.
> >>
> >> i.e.
> >>
> >> hwe->slot;
> >
> > Hmm, when I first wrote the code, I had this in hwe: hwe->nonpriv_slots.
> > But later realized it is only needed in xe_reg_whitelist_process_engine(),
> > so moved it to the local variable nonpriv_slots there.
> >
> > Also, nonpriv_slots is actually number of slots occupied by non-OA
> > registers. So if it part of hwe, the question becomes more complicated:
> > what do we store there, number of slots excluding OA or including OA? Since
> > we only need number of slots excluding OA.
>
> I would just think of it as the next available nonpriv slot for the caller
> to use. It's just a state w.r.t the hwe. When you let the caller (even if
> internal to the KMD) manage it, it's prone to errors - not about this
> series or current code, but in general.

OK, will do this in v2. Thanks.

> >
> > Therefore, to avoid these complications, I decided that the best way was a
> > temporary local variable.
> >
> > What do you think we'd gain by maintaining it as part of hwe? If things
> > change later, we could add it, but for now the local variable seems
> > sufficient?
>
> >
> > Thanks.
> > --
> > Ashutosh
> >
> >> >
> >> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> >> > ---
> >> > drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 ++++++--
> >> > 1 file changed, 6 insertions(+), 2 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> >> > index 6cc81f53fc601..1e788e2ee4014 100644
> >> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> >> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> >> > @@ -159,7 +159,7 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = {
> >> >	},
> >> > };
> >> >
> >> > -static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
> >> > +static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
> >> > {
> >> >	struct xe_reg_sr *sr = &hwe->reg_whitelist;
> >> >	struct xe_reg_sr_entry *entry;
> >> > @@ -191,6 +191,8 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
> >> >
> >> >		slot++;
> >> >	}
> >> > +
> >> > +	return slot;
> >> > }
> >> >
> >> > /**
> >> > @@ -203,11 +205,13 @@ static void whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
> >> >  */
> >> > void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
> >> > {
> >> > +	int nonpriv_slots;
> >> > +
> >> >	struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
> >> >
> >> >	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
> >> >			     &hwe->reg_whitelist, false);
> >> > -	whitelist_apply_to_hwe(hwe);
> >> > +	nonpriv_slots = whitelist_apply_to_hwe(hwe);
> >> >
> >> >	xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist),
> >> >			     &hwe->oa_whitelist, false);
> >> > --
> >> > 2.54.0
> >> >

[PATCH 4/9] drm/xe/rtp: Generalize whitelist_apply_to_hwe

[Ashutosh Dixit]

Generalize whitelist_apply_to_hwe to construct both non-OA and OA
whitelist nonpriv registers.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_reg_whitelist.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 1e788e2ee4014..6d42c00c1d75b 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -159,9 +159,10 @@ static const struct xe_rtp_entry_sr oa_whitelist[] = {
 	},
 };
 
-static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
+static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe, struct xe_reg_sr *in,
+				  struct xe_reg_sr *out, int slot_in)
 {
-	struct xe_reg_sr *sr = &hwe->reg_whitelist;
+	struct xe_reg_sr *sr = in;
 	struct xe_reg_sr_entry *entry;
 	struct drm_printer p;
 	unsigned long reg;
@@ -170,7 +171,7 @@ static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
 	xe_gt_dbg(hwe->gt, "Add %s whitelist to engine\n", sr->name);
 	p = xe_gt_dbg_printer(hwe->gt);
 
-	slot = 0;
+	slot = slot_in;
 	xa_for_each(&sr->xa, reg, entry) {
 		struct xe_reg_sr_entry hwe_entry = {
 			.reg = RING_FORCE_TO_NONPRIV(hwe->mmio_base, slot),
@@ -187,7 +188,7 @@ static int whitelist_apply_to_hwe(struct xe_hw_engine *hwe)
 		}
 
 		xe_reg_whitelist_print_entry(&p, 0, reg, entry);
-		xe_reg_sr_add(&hwe->reg_sr, &hwe_entry, hwe->gt);
+		xe_reg_sr_add(out, &hwe_entry, hwe->gt);
 
 		slot++;
 	}
@@ -211,7 +212,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
 
 	xe_rtp_process_to_sr(&ctx, register_whitelist, ARRAY_SIZE(register_whitelist),
 			     &hwe->reg_whitelist, false);
-	nonpriv_slots = whitelist_apply_to_hwe(hwe);
+	nonpriv_slots = whitelist_apply_to_hwe(hwe, &hwe->reg_whitelist, &hwe->reg_sr, 0);
 
 	xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist),
 			     &hwe->oa_whitelist, false);
-- 
2.54.0

[PATCH 5/9] drm/xe/rtp: Save OA nonpriv registers to register save/restore lists

[Ashutosh Dixit]

Now we can save OA whitelisting nonpriv registers to register save/restore
lists. OA nonpriv registers are saved to both hwe->oa_sr as well as
hwe->reg_sr, for reasons explained in coments.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_reg_whitelist.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 6d42c00c1d75b..18053582a6afa 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -216,6 +216,17 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
 
 	xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist),
 			     &hwe->oa_whitelist, false);
+	/*
+	 * Save oa nonpriv registers to hwe->oa_sr, from which oa registers are whitelisted
+	 * or de-whitelisted, by toggling the 'deny' bit on oa stream open/close
+	 */
+	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->oa_sr, nonpriv_slots);
+
+	/*
+	 * Also save oa nonpriv registers to hwe->reg_sr, to ensure oa registers are not
+	 * whitelisted by default after probe/reset/restart
+	 */
+	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, nonpriv_slots);
 }
 
 /**
-- 
2.54.0

Re: [PATCH 5/9] drm/xe/rtp: Save OA nonpriv registers to register save/restore lists

[Umesh Nerlige Ramappa]

On Mon, May 18, 2026 at 04:47:12PM -0700, Ashutosh Dixit wrote:
>Now we can save OA whitelisting nonpriv registers to register save/restore
>lists. OA nonpriv registers are saved to both hwe->oa_sr as well as
>hwe->reg_sr, for reasons explained in coments.
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>---
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>index 6d42c00c1d75b..18053582a6afa 100644
>--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>@@ -216,6 +216,17 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
>
> 	xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist),
> 			     &hwe->oa_whitelist, false);
>+	/*
>+	 * Save oa nonpriv registers to hwe->oa_sr, from which oa registers are whitelisted
>+	 * or de-whitelisted, by toggling the 'deny' bit on oa stream open/close
>+	 */
>+	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->oa_sr, nonpriv_slots);
>+
>+	/*
>+	 * Also save oa nonpriv registers to hwe->reg_sr, to ensure oa registers are not
>+	 * whitelisted by default after probe/reset/restart
>+	 */
>+	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, nonpriv_slots);

I would prefer that we fail if the registers overshoot the max slots for 
whitelisiting, but not sure why the overshoot is just a gt error log.

Also, max NONPRIV slots should be bumped up to 20 for Xe.

Umesh
> }
>
> /**
>-- 
>2.54.0
>

Re: [PATCH 5/9] drm/xe/rtp: Save OA nonpriv registers to register save/restore lists

[Dixit, Ashutosh]

On Wed, 27 May 2026 15:00:38 -0700, Umesh Nerlige Ramappa wrote:
>
> On Mon, May 18, 2026 at 04:47:12PM -0700, Ashutosh Dixit wrote:
> > Now we can save OA whitelisting nonpriv registers to register save/restore
> > lists. OA nonpriv registers are saved to both hwe->oa_sr as well as
> > hwe->reg_sr, for reasons explained in coments.
> >
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_reg_whitelist.c | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > index 6d42c00c1d75b..18053582a6afa 100644
> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > @@ -216,6 +216,17 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
> >
> >	xe_rtp_process_to_sr(&ctx, oa_whitelist, ARRAY_SIZE(oa_whitelist),
> >			     &hwe->oa_whitelist, false);
> > +	/*
> > +	 * Save oa nonpriv registers to hwe->oa_sr, from which oa registers are whitelisted
> > +	 * or de-whitelisted, by toggling the 'deny' bit on oa stream open/close
> > +	 */
> > +	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->oa_sr, nonpriv_slots);
> > +
> > +	/*
> > +	 * Also save oa nonpriv registers to hwe->reg_sr, to ensure oa registers are not
> > +	 * whitelisted by default after probe/reset/restart
> > +	 */
> > +	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, nonpriv_slots);
>
> I would prefer that we fail if the registers overshoot the max slots for
> whitelisiting, but not sure why the overshoot is just a gt error log.

Yes, this is pre-existing, but I believe it is to not fail the probe if we
overshoot. The last time I ran into a situation like this, I was told that
it is better to continue with reduced functionality, rather than no
functionality at all.

Also, xe_gt_err() will signal a failure in our CI, so the error will not be
missed.

>
> Also, max NONPRIV slots should be bumped up to 20 for Xe.

There is this:

https://patchwork.freedesktop.org/patch/717191/?series=159772&rev=5

Though I believe the patch is incorrect, I will respond separately to
this. A couple of other patches from the above series will also be nice to
have.

As I mentioned, I want to focus this series only on removing unconditional
whitelisting for OA registers. Once this is merged, I am planning to have a
follow-up series with changes such as this. E.g. the 'head' value in
WHITELIST_OA_MERT_MMIO_TRG is incorrect (not a multiple of 16, as is
required for RANGE_4), so that needs to be fixed too.

Thanks.
--
Ashutosh


>
> Umesh
> > }
> >
> > /**
> > --
> > 2.54.0
> >

[PATCH 6/9] drm/xe/rtp: Toggle 'deny' bit to (de-)whitelist OA regs

[Ashutosh Dixit]

Whitelist or de-whitelist OA registers by setting or resetting the 'deny'
bit in OA nonpriv registers and writing new register values to HW.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_reg_whitelist.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 18053582a6afa..0d2cf3d964a51 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -229,6 +229,21 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
 	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, nonpriv_slots);
 }
 
+__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
+{
+	struct xe_reg_sr_entry *entry;
+	unsigned long reg;
+
+	xa_for_each(&hwe->oa_sr.xa, reg, entry) {
+		if (whitelist)
+			entry->set_bits &= ~RING_FORCE_TO_NONPRIV_DENY;
+		else
+			entry->set_bits |= RING_FORCE_TO_NONPRIV_DENY;
+	}
+
+	xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt);
+}
+
 /**
  * xe_reg_whitelist_print_entry - print one whitelist entry
  * @p: DRM printer
-- 
2.54.0

Re: [PATCH 6/9] drm/xe/rtp: Toggle 'deny' bit to (de-)whitelist OA regs

[Umesh Nerlige Ramappa]

On Mon, May 18, 2026 at 04:47:13PM -0700, Ashutosh Dixit wrote:
>Whitelist or de-whitelist OA registers by setting or resetting the 'deny'
>bit in OA nonpriv registers and writing new register values to HW.
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

LGTM

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

>---
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>index 18053582a6afa..0d2cf3d964a51 100644
>--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>@@ -229,6 +229,21 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
> 	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, nonpriv_slots);
> }
>
>+__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
>+{
>+	struct xe_reg_sr_entry *entry;
>+	unsigned long reg;
>+
>+	xa_for_each(&hwe->oa_sr.xa, reg, entry) {
>+		if (whitelist)
>+			entry->set_bits &= ~RING_FORCE_TO_NONPRIV_DENY;
>+		else
>+			entry->set_bits |= RING_FORCE_TO_NONPRIV_DENY;
>+	}
>+
>+	xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt);
>+}
>+
> /**
>  * xe_reg_whitelist_print_entry - print one whitelist entry
>  * @p: DRM printer
>-- 
>2.54.0
>

[PATCH 7/9] drm/xe/rtp: (De-)whitelist OA registers for all hwe's for a gt

[Ashutosh Dixit]

Whitelist or de-whitelist OA registers for all hwe's on the gt on which the
OA stream is opened. This simplifies the case where an oa unit has 0
attached hwe's (but which monitors OA events on the associated GT).

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_reg_whitelist.c | 32 ++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_reg_whitelist.h |  4 ++++
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 0d2cf3d964a51..50b34c5008df7 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -229,7 +229,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
 	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, nonpriv_slots);
 }
 
-__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
+static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
 {
 	struct xe_reg_sr_entry *entry;
 	unsigned long reg;
@@ -244,6 +244,36 @@ __maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool wh
 	xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt);
 }
 
+/**
+ * xe_reg_whitelist_oa_regs - whitelist oa registers for gt
+ * @gt: gt to whitelist oa registers for
+ *
+ * Whitelist OA registers by resetting RING_FORCE_TO_NONPRIV_DENY
+ */
+void xe_reg_whitelist_oa_regs(struct xe_gt *gt)
+{
+	struct xe_hw_engine *hwe;
+	enum xe_hw_engine_id id;
+
+	for_each_hw_engine(hwe, gt, id)
+		__whitelist_oa_regs(hwe, true);
+}
+
+/**
+ * xe_reg_dewhitelist_oa_regs - dewhitelist oa registers for gt
+ * @gt: gt to dewhitelist oa registers for
+ *
+ * Dewhitelist OA registers by setting RING_FORCE_TO_NONPRIV_DENY
+ */
+void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt)
+{
+	struct xe_hw_engine *hwe;
+	enum xe_hw_engine_id id;
+
+	for_each_hw_engine(hwe, gt, id)
+		__whitelist_oa_regs(hwe, false);
+}
+
 /**
  * xe_reg_whitelist_print_entry - print one whitelist entry
  * @p: DRM printer
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.h b/drivers/gpu/drm/xe/xe_reg_whitelist.h
index 3b64b42fe96e9..e1eb1b7d5480b 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.h
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.h
@@ -9,12 +9,16 @@
 #include <linux/types.h>
 
 struct drm_printer;
+struct xe_gt;
 struct xe_hw_engine;
 struct xe_reg_sr;
 struct xe_reg_sr_entry;
 
 void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe);
 
+void xe_reg_whitelist_oa_regs(struct xe_gt *gt);
+void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt);
+
 void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
 				  u32 reg, struct xe_reg_sr_entry *entry);
 
-- 
2.54.0

Re: [PATCH 7/9] drm/xe/rtp: (De-)whitelist OA registers for all hwe's for a gt

[Umesh Nerlige Ramappa]

On Mon, May 18, 2026 at 04:47:14PM -0700, Ashutosh Dixit wrote:
>Whitelist or de-whitelist OA registers for all hwe's on the gt on which the
>OA stream is opened. This simplifies the case where an oa unit has 0
>attached hwe's (but which monitors OA events on the associated GT).
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>---
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 32 ++++++++++++++++++++++++++-
> drivers/gpu/drm/xe/xe_reg_whitelist.h |  4 ++++
> 2 files changed, 35 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>index 0d2cf3d964a51..50b34c5008df7 100644
>--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>@@ -229,7 +229,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
> 	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, nonpriv_slots);
> }
>
>-__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
>+static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
> {
> 	struct xe_reg_sr_entry *entry;
> 	unsigned long reg;
>@@ -244,6 +244,36 @@ __maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool wh
> 	xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt);
> }
>
>+/**
>+ * xe_reg_whitelist_oa_regs - whitelist oa registers for gt
>+ * @gt: gt to whitelist oa registers for
>+ *
>+ * Whitelist OA registers by resetting RING_FORCE_TO_NONPRIV_DENY
>+ */
>+void xe_reg_whitelist_oa_regs(struct xe_gt *gt)
>+{
>+	struct xe_hw_engine *hwe;
>+	enum xe_hw_engine_id id;
>+
>+	for_each_hw_engine(hwe, gt, id)
>+		__whitelist_oa_regs(hwe, true);

I think we should only apply the whitelist to the hwe that will use this 
specific OA unit. That will help do away with the ref counting in patch 
9 here.

Thanks,
Umesh
>+}
>+
>+/**
>+ * xe_reg_dewhitelist_oa_regs - dewhitelist oa registers for gt
>+ * @gt: gt to dewhitelist oa registers for
>+ *
>+ * Dewhitelist OA registers by setting RING_FORCE_TO_NONPRIV_DENY
>+ */
>+void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt)
>+{
>+	struct xe_hw_engine *hwe;
>+	enum xe_hw_engine_id id;
>+
>+	for_each_hw_engine(hwe, gt, id)
>+		__whitelist_oa_regs(hwe, false);
>+}
>+
> /**
>  * xe_reg_whitelist_print_entry - print one whitelist entry
>  * @p: DRM printer
>diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.h b/drivers/gpu/drm/xe/xe_reg_whitelist.h
>index 3b64b42fe96e9..e1eb1b7d5480b 100644
>--- a/drivers/gpu/drm/xe/xe_reg_whitelist.h
>+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.h
>@@ -9,12 +9,16 @@
> #include <linux/types.h>
>
> struct drm_printer;
>+struct xe_gt;
> struct xe_hw_engine;
> struct xe_reg_sr;
> struct xe_reg_sr_entry;
>
> void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe);
>
>+void xe_reg_whitelist_oa_regs(struct xe_gt *gt);
>+void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt);
>+
> void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
> 				  u32 reg, struct xe_reg_sr_entry *entry);
>
>-- 
>2.54.0
>

Re: [PATCH 7/9] drm/xe/rtp: (De-)whitelist OA registers for all hwe's for a gt

[Dixit, Ashutosh]

On Wed, 27 May 2026 14:49:12 -0700, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> On Mon, May 18, 2026 at 04:47:14PM -0700, Ashutosh Dixit wrote:
> > Whitelist or de-whitelist OA registers for all hwe's on the gt on which the
> > OA stream is opened. This simplifies the case where an oa unit has 0
> > attached hwe's (but which monitors OA events on the associated GT).
> >
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_reg_whitelist.c | 32 ++++++++++++++++++++++++++-
> > drivers/gpu/drm/xe/xe_reg_whitelist.h |  4 ++++
> > 2 files changed, 35 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > index 0d2cf3d964a51..50b34c5008df7 100644
> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > @@ -229,7 +229,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
> >	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, nonpriv_slots);
> > }
> >
> > -__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
> > +static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
> > {
> >	struct xe_reg_sr_entry *entry;
> >	unsigned long reg;
> > @@ -244,6 +244,36 @@ __maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool wh
> >	xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt);
> > }
> >
> > +/**
> > + * xe_reg_whitelist_oa_regs - whitelist oa registers for gt
> > + * @gt: gt to whitelist oa registers for
> > + *
> > + * Whitelist OA registers by resetting RING_FORCE_TO_NONPRIV_DENY
> > + */
> > +void xe_reg_whitelist_oa_regs(struct xe_gt *gt)
> > +{
> > +	struct xe_hw_engine *hwe;
> > +	enum xe_hw_engine_id id;
> > +
> > +	for_each_hw_engine(hwe, gt, id)
> > +		__whitelist_oa_regs(hwe, true);
>
> I think we should only apply the whitelist to the hwe that will use this
> specific OA unit. That will help do away with the ref counting in patch 9
> here.

No, if we do this we will need to introduce per hwe refcounts (instead of
per gt refcounts, as done in Patch 9).

Each OA unit has a set of attached hwe's. Then there are OA units such as
oam-sag and mertoa, which don't have any attached hwe's. For these we allow
mmio triggers to be submitted on any hwe's attached to that gt. Also some
hwe's like copy engines are common between OA units. Since multiple OA
streams might be open simultaneously, because of these reasons, we'd have
to introduce per hwe refcounts.

Also, if the concern is that we are opening up all hwe's on a gt, rather
than hwe's attached to the OA unit on which an OA stream is opened, I do
not consider this a serious issue, because after all registers are being
whitlisted by an explicit permission from root. The root, e.g. is free to
load up a custom module which can whitelist whatever they want.

So, if we want to implement whitelisting only hwe's attached to the an OA
unit (including OA units which don't have any hwe's attached, so would
include all hwe's on a gt), this is substantial increase in code
complexity, that will need a separate series of patches, over and above the
current series.

So if we do this, that's a separate set of patches. Since the current
series is already a big improvement in closing down unconditional OA
register whitelisting, I'd say let's get this reviewed and merged first and
then we debate if we at all need to restrict the whitelisting further and
then do that if we need to, but I really don't think it is needed.

Thanks.
--
Ashutosh

> > +}
> > +
> > +/**
> > + * xe_reg_dewhitelist_oa_regs - dewhitelist oa registers for gt
> > + * @gt: gt to dewhitelist oa registers for
> > + *
> > + * Dewhitelist OA registers by setting RING_FORCE_TO_NONPRIV_DENY
> > + */
> > +void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt)
> > +{
> > +	struct xe_hw_engine *hwe;
> > +	enum xe_hw_engine_id id;
> > +
> > +	for_each_hw_engine(hwe, gt, id)
> > +		__whitelist_oa_regs(hwe, false);
> > +}
> > +
> > /**
> >  * xe_reg_whitelist_print_entry - print one whitelist entry
> >  * @p: DRM printer
> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.h b/drivers/gpu/drm/xe/xe_reg_whitelist.h
> > index 3b64b42fe96e9..e1eb1b7d5480b 100644
> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.h
> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.h
> > @@ -9,12 +9,16 @@
> > #include <linux/types.h>
> >
> > struct drm_printer;
> > +struct xe_gt;
> > struct xe_hw_engine;
> > struct xe_reg_sr;
> > struct xe_reg_sr_entry;
> >
> > void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe);
> >
> > +void xe_reg_whitelist_oa_regs(struct xe_gt *gt);
> > +void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt);
> > +
> > void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
> >				  u32 reg, struct xe_reg_sr_entry *entry);
> >
> > --
> > 2.54.0
> >

Re: [PATCH 7/9] drm/xe/rtp: (De-)whitelist OA registers for all hwe's for a gt

[Umesh Nerlige Ramappa]

On Fri, May 29, 2026 at 04:03:13PM -0700, Dixit, Ashutosh wrote:
>On Wed, 27 May 2026 14:49:12 -0700, Umesh Nerlige Ramappa wrote:
>>
>
>Hi Umesh,
>
>> On Mon, May 18, 2026 at 04:47:14PM -0700, Ashutosh Dixit wrote:
>> > Whitelist or de-whitelist OA registers for all hwe's on the gt on which the
>> > OA stream is opened. This simplifies the case where an oa unit has 0
>> > attached hwe's (but which monitors OA events on the associated GT).
>> >
>> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>> > ---
>> > drivers/gpu/drm/xe/xe_reg_whitelist.c | 32 ++++++++++++++++++++++++++-
>> > drivers/gpu/drm/xe/xe_reg_whitelist.h |  4 ++++
>> > 2 files changed, 35 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> > index 0d2cf3d964a51..50b34c5008df7 100644
>> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>> > @@ -229,7 +229,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
>> >	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, nonpriv_slots);
>> > }
>> >
>> > -__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
>> > +static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
>> > {
>> >	struct xe_reg_sr_entry *entry;
>> >	unsigned long reg;
>> > @@ -244,6 +244,36 @@ __maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool wh
>> >	xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt);
>> > }
>> >
>> > +/**
>> > + * xe_reg_whitelist_oa_regs - whitelist oa registers for gt
>> > + * @gt: gt to whitelist oa registers for
>> > + *
>> > + * Whitelist OA registers by resetting RING_FORCE_TO_NONPRIV_DENY
>> > + */
>> > +void xe_reg_whitelist_oa_regs(struct xe_gt *gt)
>> > +{
>> > +	struct xe_hw_engine *hwe;
>> > +	enum xe_hw_engine_id id;
>> > +
>> > +	for_each_hw_engine(hwe, gt, id)
>> > +		__whitelist_oa_regs(hwe, true);
>>
>> I think we should only apply the whitelist to the hwe that will use this
>> specific OA unit. That will help do away with the ref counting in patch 9
>> here.
>
>No, if we do this we will need to introduce per hwe refcounts (instead of
>per gt refcounts, as done in Patch 9).
>
>Each OA unit has a set of attached hwe's. Then there are OA units such as
>oam-sag and mertoa, which don't have any attached hwe's. For these we allow
>mmio triggers to be submitted on any hwe's attached to that gt. Also some
>hwe's like copy engines are common between OA units. Since multiple OA
>streams might be open simultaneously, because of these reasons, we'd have
>to introduce per hwe refcounts.
>
>Also, if the concern is that we are opening up all hwe's on a gt, rather
>than hwe's attached to the OA unit on which an OA stream is opened, I do
>not consider this a serious issue, because after all registers are being
>whitlisted by an explicit permission from root. The root, e.g. is free to
>load up a custom module which can whitelist whatever they want.
>
>So, if we want to implement whitelisting only hwe's attached to the an OA
>unit (including OA units which don't have any hwe's attached, so would
>include all hwe's on a gt), this is substantial increase in code
>complexity, that will need a separate series of patches, over and above the
>current series.
>
>So if we do this, that's a separate set of patches. Since the current
>series is already a big improvement in closing down unconditional OA
>register whitelisting, I'd say let's get this reviewed and merged first and
>then we debate if we at all need to restrict the whitelisting further and
>then do that if we need to, but I really don't think it is needed.

I see what you are saying w.r.t. simplicity and reference tracking. At 
the same time I think it's wasteful to whitelist OAM_TRIGGER from 
ccs/rcs or and OAG register from media CS.

My intention is to use the NONPRIV slots sparingly. If not, we should 
have some sort of fallback for UMDs if we run out of NONPRIV slots (like 
provide a query that tells them whether whitelist is supported on an OA 
unit or not).

We can discuss after this series is concluded.

Thanks,
Umesh

>
>Thanks.
>--
>Ashutosh
>
>> > +}
>> > +
>> > +/**
>> > + * xe_reg_dewhitelist_oa_regs - dewhitelist oa registers for gt
>> > + * @gt: gt to dewhitelist oa registers for
>> > + *
>> > + * Dewhitelist OA registers by setting RING_FORCE_TO_NONPRIV_DENY
>> > + */
>> > +void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt)
>> > +{
>> > +	struct xe_hw_engine *hwe;
>> > +	enum xe_hw_engine_id id;
>> > +
>> > +	for_each_hw_engine(hwe, gt, id)
>> > +		__whitelist_oa_regs(hwe, false);
>> > +}
>> > +
>> > /**
>> >  * xe_reg_whitelist_print_entry - print one whitelist entry
>> >  * @p: DRM printer
>> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.h b/drivers/gpu/drm/xe/xe_reg_whitelist.h
>> > index 3b64b42fe96e9..e1eb1b7d5480b 100644
>> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.h
>> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.h
>> > @@ -9,12 +9,16 @@
>> > #include <linux/types.h>
>> >
>> > struct drm_printer;
>> > +struct xe_gt;
>> > struct xe_hw_engine;
>> > struct xe_reg_sr;
>> > struct xe_reg_sr_entry;
>> >
>> > void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe);
>> >
>> > +void xe_reg_whitelist_oa_regs(struct xe_gt *gt);
>> > +void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt);
>> > +
>> > void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
>> >				  u32 reg, struct xe_reg_sr_entry *entry);
>> >
>> > --
>> > 2.54.0
>> >

Re: [PATCH 7/9] drm/xe/rtp: (De-)whitelist OA registers for all hwe's for a gt

[Dixit, Ashutosh]

On Tue, 02 Jun 2026 15:47:48 -0700, Umesh Nerlige Ramappa wrote:
>
> On Fri, May 29, 2026 at 04:03:13PM -0700, Dixit, Ashutosh wrote:
> > On Wed, 27 May 2026 14:49:12 -0700, Umesh Nerlige Ramappa wrote:
> >>
> >
> > Hi Umesh,
> >
> >> On Mon, May 18, 2026 at 04:47:14PM -0700, Ashutosh Dixit wrote:
> >> > Whitelist or de-whitelist OA registers for all hwe's on the gt on which the
> >> > OA stream is opened. This simplifies the case where an oa unit has 0
> >> > attached hwe's (but which monitors OA events on the associated GT).
> >> >
> >> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> >> > ---
> >> > drivers/gpu/drm/xe/xe_reg_whitelist.c | 32 ++++++++++++++++++++++++++-
> >> > drivers/gpu/drm/xe/xe_reg_whitelist.h |  4 ++++
> >> > 2 files changed, 35 insertions(+), 1 deletion(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> >> > index 0d2cf3d964a51..50b34c5008df7 100644
> >> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> >> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> >> > @@ -229,7 +229,7 @@ void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe)
> >> >	whitelist_apply_to_hwe(hwe, &hwe->oa_whitelist, &hwe->reg_sr, nonpriv_slots);
> >> > }
> >> >
> >> > -__maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
> >> > +static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool whitelist)
> >> > {
> >> >	struct xe_reg_sr_entry *entry;
> >> >	unsigned long reg;
> >> > @@ -244,6 +244,36 @@ __maybe_unused static void __whitelist_oa_regs(struct xe_hw_engine *hwe, bool wh
> >> >	xe_reg_sr_apply_mmio(&hwe->oa_sr, hwe->gt);
> >> > }
> >> >
> >> > +/**
> >> > + * xe_reg_whitelist_oa_regs - whitelist oa registers for gt
> >> > + * @gt: gt to whitelist oa registers for
> >> > + *
> >> > + * Whitelist OA registers by resetting RING_FORCE_TO_NONPRIV_DENY
> >> > + */
> >> > +void xe_reg_whitelist_oa_regs(struct xe_gt *gt)
> >> > +{
> >> > +	struct xe_hw_engine *hwe;
> >> > +	enum xe_hw_engine_id id;
> >> > +
> >> > +	for_each_hw_engine(hwe, gt, id)
> >> > +		__whitelist_oa_regs(hwe, true);
> >>
> >> I think we should only apply the whitelist to the hwe that will use this
> >> specific OA unit. That will help do away with the ref counting in patch 9
> >> here.
> >
> > No, if we do this we will need to introduce per hwe refcounts (instead of
> > per gt refcounts, as done in Patch 9).
> >
> > Each OA unit has a set of attached hwe's. Then there are OA units such as
> > oam-sag and mertoa, which don't have any attached hwe's. For these we allow
> > mmio triggers to be submitted on any hwe's attached to that gt. Also some
> > hwe's like copy engines are common between OA units. Since multiple OA
> > streams might be open simultaneously, because of these reasons, we'd have
> > to introduce per hwe refcounts.
> >
> > Also, if the concern is that we are opening up all hwe's on a gt, rather
> > than hwe's attached to the OA unit on which an OA stream is opened, I do
> > not consider this a serious issue, because after all registers are being
> > whitlisted by an explicit permission from root. The root, e.g. is free to
> > load up a custom module which can whitelist whatever they want.
> >
> > So, if we want to implement whitelisting only hwe's attached to the an OA
> > unit (including OA units which don't have any hwe's attached, so would
> > include all hwe's on a gt), this is substantial increase in code
> > complexity, that will need a separate series of patches, over and above the
> > current series.
> >
> > So if we do this, that's a separate set of patches. Since the current
> > series is already a big improvement in closing down unconditional OA
> > register whitelisting, I'd say let's get this reviewed and merged first and
> > then we debate if we at all need to restrict the whitelisting further and
> > then do that if we need to, but I really don't think it is needed.
>
> I see what you are saying w.r.t. simplicity and reference tracking. At the
> same time I think it's wasteful to whitelist OAM_TRIGGER from ccs/rcs or
> and OAG register from media CS.

Given that media is a separate gt, these scenarios cannot happen.

>
> My intention is to use the NONPRIV slots sparingly. If not, we should have
> some sort of fallback for UMDs if we run out of NONPRIV slots (like provide
> a query that tells them whether whitelist is supported on an OA unit or
> not).
>
> We can discuss after this series is concluded.

Sure, but note that we didn't even use up 12 nonpriv slots, and should be
able to increase them to 20. And any such optimization/query can be
postponed till/if they are really needed.

Thanks!

> >
> >> > +}
> >> > +
> >> > +/**
> >> > + * xe_reg_dewhitelist_oa_regs - dewhitelist oa registers for gt
> >> > + * @gt: gt to dewhitelist oa registers for
> >> > + *
> >> > + * Dewhitelist OA registers by setting RING_FORCE_TO_NONPRIV_DENY
> >> > + */
> >> > +void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt)
> >> > +{
> >> > +	struct xe_hw_engine *hwe;
> >> > +	enum xe_hw_engine_id id;
> >> > +
> >> > +	for_each_hw_engine(hwe, gt, id)
> >> > +		__whitelist_oa_regs(hwe, false);
> >> > +}
> >> > +
> >> > /**
> >> >  * xe_reg_whitelist_print_entry - print one whitelist entry
> >> >  * @p: DRM printer
> >> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.h b/drivers/gpu/drm/xe/xe_reg_whitelist.h
> >> > index 3b64b42fe96e9..e1eb1b7d5480b 100644
> >> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.h
> >> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.h
> >> > @@ -9,12 +9,16 @@
> >> > #include <linux/types.h>
> >> >
> >> > struct drm_printer;
> >> > +struct xe_gt;
> >> > struct xe_hw_engine;
> >> > struct xe_reg_sr;
> >> > struct xe_reg_sr_entry;
> >> >
> >> > void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe);
> >> >
> >> > +void xe_reg_whitelist_oa_regs(struct xe_gt *gt);
> >> > +void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt);
> >> > +
> >> > void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
> >> >				  u32 reg, struct xe_reg_sr_entry *entry);
> >> >
> >> > --
> >> > 2.54.0
> >> >

[PATCH 8/9] drm/xe/oa: (De-)whitelist OA registers on OA stream open/release

[Ashutosh Dixit]

Whitelist OA registers on stream open and de-whitelist on stream
close/release. Whitelisting is only done when 'stream->sample' is
true. 'stream->sample' is only true when (a) xe_observation_paranoid is set
to false by system admin, or (b) the process is perfmon_capable(). This
therefore enforces the OA register whitelisting security requirements.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 7c9071abb44f1..8d2865a66bf1f 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -37,6 +37,7 @@
 #include "xe_oa.h"
 #include "xe_observation.h"
 #include "xe_pm.h"
+#include "xe_reg_whitelist.h"
 #include "xe_sched_job.h"
 #include "xe_sriov.h"
 #include "xe_sync.h"
@@ -885,6 +886,9 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream)
 
 	mutex_destroy(&stream->stream_lock);
 
+	if (stream->sample)
+		xe_reg_dewhitelist_oa_regs(stream->gt);
+
 	xe_oa_disable_metric_set(stream);
 	xe_exec_queue_put(stream->k_exec_q);
 
@@ -1885,6 +1889,9 @@ static int xe_oa_stream_open_ioctl_locked(struct xe_oa *oa,
 		goto err_disable;
 	}
 
+	if (stream->sample)
+		xe_reg_whitelist_oa_regs(stream->gt);
+
 	/* Hold a reference on the drm device till stream_fd is released */
 	drm_dev_get(&stream->oa->xe->drm);
 
-- 
2.54.0

Re: [PATCH 8/9] drm/xe/oa: (De-)whitelist OA registers on OA stream open/release

[Umesh Nerlige Ramappa]

On Mon, May 18, 2026 at 04:47:15PM -0700, Ashutosh Dixit wrote:
>Whitelist OA registers on stream open and de-whitelist on stream
>close/release. Whitelisting is only done when 'stream->sample' is
>true. 'stream->sample' is only true when (a) xe_observation_paranoid is set
>to false by system admin, or (b) the process is perfmon_capable(). This
>therefore enforces the OA register whitelisting security requirements.
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

LGTM

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

>---
> drivers/gpu/drm/xe/xe_oa.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
>index 7c9071abb44f1..8d2865a66bf1f 100644
>--- a/drivers/gpu/drm/xe/xe_oa.c
>+++ b/drivers/gpu/drm/xe/xe_oa.c
>@@ -37,6 +37,7 @@
> #include "xe_oa.h"
> #include "xe_observation.h"
> #include "xe_pm.h"
>+#include "xe_reg_whitelist.h"
> #include "xe_sched_job.h"
> #include "xe_sriov.h"
> #include "xe_sync.h"
>@@ -885,6 +886,9 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream)
>
> 	mutex_destroy(&stream->stream_lock);
>
>+	if (stream->sample)
>+		xe_reg_dewhitelist_oa_regs(stream->gt);
>+
> 	xe_oa_disable_metric_set(stream);
> 	xe_exec_queue_put(stream->k_exec_q);
>
>@@ -1885,6 +1889,9 @@ static int xe_oa_stream_open_ioctl_locked(struct xe_oa *oa,
> 		goto err_disable;
> 	}
>
>+	if (stream->sample)
>+		xe_reg_whitelist_oa_regs(stream->gt);
>+
> 	/* Hold a reference on the drm device till stream_fd is released */
> 	drm_dev_get(&stream->oa->xe->drm);
>
>-- 
>2.54.0
>

[PATCH 9/9] drm/xe/rtp: Ensure locking/ref counting for OA whitelists

[Ashutosh Dixit]

Since multiple OA streams might be open in parallel on a gt, ensure that
proper locking is in place. Also ensure that OA registers are whitelisted
when the first OA stream is open and de-whitelisted after the last OA
stream is closed.

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_oa_types.h      | 3 +++
 drivers/gpu/drm/xe/xe_reg_whitelist.c | 9 +++++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_oa_types.h b/drivers/gpu/drm/xe/xe_oa_types.h
index 3d9ec8490899c..e876e9be92ba5 100644
--- a/drivers/gpu/drm/xe/xe_oa_types.h
+++ b/drivers/gpu/drm/xe/xe_oa_types.h
@@ -126,6 +126,9 @@ struct xe_oa_gt {
 
 	/** @oa_unit: array of oa_units */
 	struct xe_oa_unit *oa_unit;
+
+	/** @whitelist_count: number of open streams for which oa registers are whitelisted */
+	u32 whitelist_count;
 };
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 50b34c5008df7..1b72f0d2935a2 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -255,6 +255,10 @@ void xe_reg_whitelist_oa_regs(struct xe_gt *gt)
 	struct xe_hw_engine *hwe;
 	enum xe_hw_engine_id id;
 
+	lockdep_assert_held(&gt->oa.gt_lock);
+	if (gt->oa.whitelist_count++)
+		return;
+
 	for_each_hw_engine(hwe, gt, id)
 		__whitelist_oa_regs(hwe, true);
 }
@@ -270,6 +274,11 @@ void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt)
 	struct xe_hw_engine *hwe;
 	enum xe_hw_engine_id id;
 
+	lockdep_assert_held(&gt->oa.gt_lock);
+	xe_assert(gt_to_xe(gt), gt->oa.whitelist_count);
+	if (--gt->oa.whitelist_count)
+		return;
+
 	for_each_hw_engine(hwe, gt, id)
 		__whitelist_oa_regs(hwe, false);
 }
-- 
2.54.0

Re: [PATCH 9/9] drm/xe/rtp: Ensure locking/ref counting for OA whitelists

[Umesh Nerlige Ramappa]

On Mon, May 18, 2026 at 04:47:16PM -0700, Ashutosh Dixit wrote:
>Since multiple OA streams might be open in parallel on a gt, ensure that
>proper locking is in place. Also ensure that OA registers are whitelisted
>when the first OA stream is open and de-whitelisted after the last OA
>stream is closed.
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
>---
> drivers/gpu/drm/xe/xe_oa_types.h      | 3 +++
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 9 +++++++++
> 2 files changed, 12 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_oa_types.h b/drivers/gpu/drm/xe/xe_oa_types.h
>index 3d9ec8490899c..e876e9be92ba5 100644
>--- a/drivers/gpu/drm/xe/xe_oa_types.h
>+++ b/drivers/gpu/drm/xe/xe_oa_types.h
>@@ -126,6 +126,9 @@ struct xe_oa_gt {
>
> 	/** @oa_unit: array of oa_units */
> 	struct xe_oa_unit *oa_unit;
>+
>+	/** @whitelist_count: number of open streams for which oa registers are whitelisted */
>+	u32 whitelist_count;
> };
>
> /**
>diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>index 50b34c5008df7..1b72f0d2935a2 100644
>--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
>+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
>@@ -255,6 +255,10 @@ void xe_reg_whitelist_oa_regs(struct xe_gt *gt)
> 	struct xe_hw_engine *hwe;
> 	enum xe_hw_engine_id id;
>
>+	lockdep_assert_held(&gt->oa.gt_lock);
>+	if (gt->oa.whitelist_count++)
>+		return;

Any reason why not using kref here?

Thanks,
Umesh
>+
> 	for_each_hw_engine(hwe, gt, id)
> 		__whitelist_oa_regs(hwe, true);
> }
>@@ -270,6 +274,11 @@ void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt)
> 	struct xe_hw_engine *hwe;
> 	enum xe_hw_engine_id id;
>
>+	lockdep_assert_held(&gt->oa.gt_lock);
>+	xe_assert(gt_to_xe(gt), gt->oa.whitelist_count);
>+	if (--gt->oa.whitelist_count)
>+		return;
>+
> 	for_each_hw_engine(hwe, gt, id)
> 		__whitelist_oa_regs(hwe, false);
> }
>-- 
>2.54.0
>

Re: [PATCH 9/9] drm/xe/rtp: Ensure locking/ref counting for OA whitelists

[Dixit, Ashutosh]

On Wed, 27 May 2026 13:04:31 -0700, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> On Mon, May 18, 2026 at 04:47:16PM -0700, Ashutosh Dixit wrote:
> > Since multiple OA streams might be open in parallel on a gt, ensure that
> > proper locking is in place. Also ensure that OA registers are whitelisted
> > when the first OA stream is open and de-whitelisted after the last OA
> > stream is closed.
> >
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_oa_types.h      | 3 +++
> > drivers/gpu/drm/xe/xe_reg_whitelist.c | 9 +++++++++
> > 2 files changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_oa_types.h b/drivers/gpu/drm/xe/xe_oa_types.h
> > index 3d9ec8490899c..e876e9be92ba5 100644
> > --- a/drivers/gpu/drm/xe/xe_oa_types.h
> > +++ b/drivers/gpu/drm/xe/xe_oa_types.h
> > @@ -126,6 +126,9 @@ struct xe_oa_gt {
> >
> >	/** @oa_unit: array of oa_units */
> >	struct xe_oa_unit *oa_unit;
> > +
> > +	/** @whitelist_count: number of open streams for which oa registers are whitelisted */
> > +	u32 whitelist_count;
> > };
> >
> > /**
> > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > index 50b34c5008df7..1b72f0d2935a2 100644
> > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> > @@ -255,6 +255,10 @@ void xe_reg_whitelist_oa_regs(struct xe_gt *gt)
> >	struct xe_hw_engine *hwe;
> >	enum xe_hw_engine_id id;
> >
> > +	lockdep_assert_held(&gt->oa.gt_lock);
> > +	if (gt->oa.whitelist_count++)
> > +		return;
>
> Any reason why not using kref here?

Maybe I am wrong, but I looked into it and to me it seems kref is not
appropriate to use here. That is because:

1. A kref is first initialized to value 1 using kref_init().
2. Then subsequently you do kref_get()'s and kref_put()'s
3. Even if we have matching kref_get()'s and kref_put()'s, a final
   kref_put() is needed to bring the value down to 0 and trigger the
   release() function

Also, there is only a release() function, but nothing to trigger something
when the value goes from 0 to 1. So in this case, you'd explicitly need to
check the kref value.

Further, kref's are really useful for tracking arbitrary/asymmetrical
producers/consumers (say as part of dma_fence's), but in a strictly
symmetric situation such as what we have here, kref's don't seem to be very
useful. (See also previous use of kref in 'struct xe_oa_config' e.g.).

So here what we want is, whitelist OA registers when gt->oa.whitelist_count
goes from 0 to 1 and dewhitelist them when gt->oa.whitelist_count goes from
1 to 0. Also, we already take 'gt->oa.gt_lock' in both these cases, so even
an atomic_t refcount is not needed.

So, overall, it seems to me that if we use a kref here, it will look forced
and the code will be uglier than what we have here.

Let me know what you think about this, but for now I am tending to leaving
this as is.

Thanks.
--
Ashutosh

> > +
> >	for_each_hw_engine(hwe, gt, id)
> >		__whitelist_oa_regs(hwe, true);
> > }
> > @@ -270,6 +274,11 @@ void xe_reg_dewhitelist_oa_regs(struct xe_gt *gt)
> >	struct xe_hw_engine *hwe;
> >	enum xe_hw_engine_id id;
> >
> > +	lockdep_assert_held(&gt->oa.gt_lock);
> > +	xe_assert(gt_to_xe(gt), gt->oa.whitelist_count);
> > +	if (--gt->oa.whitelist_count)
> > +		return;
> > +
> >	for_each_hw_engine(hwe, gt, id)
> >		__whitelist_oa_regs(hwe, false);
> > }
> > --
> > 2.54.0
> >

✓ CI.KUnit: success for Don't whitelist OA registers unconditionally

[Patchwork]

== Series Details ==

Series: Don't whitelist OA registers unconditionally
URL   : https://patchwork.freedesktop.org/series/166809/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[23:53:02] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:53:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:53:38] Starting KUnit Kernel (1/1)...
[23:53:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:53:38] ================== guc_buf (11 subtests) ===================
[23:53:38] [PASSED] test_smallest
[23:53:38] [PASSED] test_largest
[23:53:38] [PASSED] test_granular
[23:53:38] [PASSED] test_unique
[23:53:38] [PASSED] test_overlap
[23:53:38] [PASSED] test_reusable
[23:53:38] [PASSED] test_too_big
[23:53:38] [PASSED] test_flush
[23:53:38] [PASSED] test_lookup
[23:53:38] [PASSED] test_data
[23:53:38] [PASSED] test_class
[23:53:38] ===================== [PASSED] guc_buf =====================
[23:53:38] =================== guc_dbm (7 subtests) ===================
[23:53:38] [PASSED] test_empty
[23:53:38] [PASSED] test_default
[23:53:38] ======================== test_size  ========================
[23:53:38] [PASSED] 4
[23:53:38] [PASSED] 8
[23:53:38] [PASSED] 32
[23:53:38] [PASSED] 256
[23:53:38] ==================== [PASSED] test_size ====================
[23:53:38] ======================= test_reuse  ========================
[23:53:38] [PASSED] 4
[23:53:38] [PASSED] 8
[23:53:38] [PASSED] 32
[23:53:38] [PASSED] 256
[23:53:38] =================== [PASSED] test_reuse ====================
[23:53:38] =================== test_range_overlap  ====================
[23:53:38] [PASSED] 4
[23:53:38] [PASSED] 8
[23:53:38] [PASSED] 32
[23:53:38] [PASSED] 256
[23:53:38] =============== [PASSED] test_range_overlap ================
[23:53:38] =================== test_range_compact  ====================
[23:53:38] [PASSED] 4
[23:53:38] [PASSED] 8
[23:53:38] [PASSED] 32
[23:53:38] [PASSED] 256
[23:53:38] =============== [PASSED] test_range_compact ================
[23:53:38] ==================== test_range_spare  =====================
[23:53:38] [PASSED] 4
[23:53:38] [PASSED] 8
[23:53:38] [PASSED] 32
[23:53:38] [PASSED] 256
[23:53:38] ================ [PASSED] test_range_spare =================
[23:53:38] ===================== [PASSED] guc_dbm =====================
[23:53:38] =================== guc_idm (6 subtests) ===================
[23:53:38] [PASSED] bad_init
[23:53:38] [PASSED] no_init
[23:53:38] [PASSED] init_fini
[23:53:38] [PASSED] check_used
[23:53:38] [PASSED] check_quota
[23:53:38] [PASSED] check_all
[23:53:38] ===================== [PASSED] guc_idm =====================
[23:53:38] ================== no_relay (3 subtests) ===================
[23:53:38] [PASSED] xe_drops_guc2pf_if_not_ready
[23:53:38] [PASSED] xe_drops_guc2vf_if_not_ready
[23:53:38] [PASSED] xe_rejects_send_if_not_ready
[23:53:38] ==================== [PASSED] no_relay =====================
[23:53:38] ================== pf_relay (14 subtests) ==================
[23:53:38] [PASSED] pf_rejects_guc2pf_too_short
[23:53:38] [PASSED] pf_rejects_guc2pf_too_long
[23:53:38] [PASSED] pf_rejects_guc2pf_no_payload
[23:53:38] [PASSED] pf_fails_no_payload
[23:53:38] [PASSED] pf_fails_bad_origin
[23:53:38] [PASSED] pf_fails_bad_type
[23:53:38] [PASSED] pf_txn_reports_error
[23:53:38] [PASSED] pf_txn_sends_pf2guc
[23:53:38] [PASSED] pf_sends_pf2guc
[23:53:38] [SKIPPED] pf_loopback_nop
[23:53:38] [SKIPPED] pf_loopback_echo
[23:53:38] [SKIPPED] pf_loopback_fail
[23:53:38] [SKIPPED] pf_loopback_busy
[23:53:38] [SKIPPED] pf_loopback_retry
[23:53:38] ==================== [PASSED] pf_relay =====================
[23:53:38] ================== vf_relay (3 subtests) ===================
[23:53:38] [PASSED] vf_rejects_guc2vf_too_short
[23:53:38] [PASSED] vf_rejects_guc2vf_too_long
[23:53:38] [PASSED] vf_rejects_guc2vf_no_payload
[23:53:38] ==================== [PASSED] vf_relay =====================
[23:53:38] ================ pf_gt_config (9 subtests) =================
[23:53:38] [PASSED] fair_contexts_1vf
[23:53:38] [PASSED] fair_doorbells_1vf
[23:53:38] [PASSED] fair_ggtt_1vf
[23:53:38] ====================== fair_vram_1vf  ======================
[23:53:38] [PASSED] 3.50 GiB
[23:53:38] [PASSED] 11.5 GiB
[23:53:38] [PASSED] 15.5 GiB
[23:53:38] [PASSED] 31.5 GiB
[23:53:38] [PASSED] 63.5 GiB
[23:53:38] [PASSED] 1.91 GiB
[23:53:38] ================== [PASSED] fair_vram_1vf ==================
[23:53:38] ================ fair_vram_1vf_admin_only  =================
[23:53:38] [PASSED] 3.50 GiB
[23:53:38] [PASSED] 11.5 GiB
[23:53:38] [PASSED] 15.5 GiB
[23:53:38] [PASSED] 31.5 GiB
[23:53:38] [PASSED] 63.5 GiB
[23:53:38] [PASSED] 1.91 GiB
[23:53:38] ============ [PASSED] fair_vram_1vf_admin_only =============
[23:53:38] ====================== fair_contexts  ======================
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[23:53:38] ================== [PASSED] fair_contexts ==================
[23:53:38] ===================== fair_doorbells  ======================
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[23:53:38] ================= [PASSED] fair_doorbells ==================
[23:53:38] ======================== fair_ggtt  ========================
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[23:53:38] ==================== [PASSED] fair_ggtt ====================
[23:53:38] ======================== fair_vram  ========================
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[23:53:38] [PASSED] 46 VFs
[23:53:38] [PASSED] 47 VFs
[23:53:38] [PASSED] 48 VFs
[23:53:38] [PASSED] 49 VFs
[23:53:38] [PASSED] 50 VFs
[23:53:38] [PASSED] 51 VFs
[23:53:38] [PASSED] 52 VFs
[23:53:38] [PASSED] 53 VFs
[23:53:38] [PASSED] 54 VFs
[23:53:38] [PASSED] 55 VFs
[23:53:38] [PASSED] 56 VFs
[23:53:38] [PASSED] 57 VFs
[23:53:38] [PASSED] 58 VFs
[23:53:38] [PASSED] 59 VFs
[23:53:38] [PASSED] 60 VFs
[23:53:38] [PASSED] 61 VFs
[23:53:38] [PASSED] 62 VFs
[23:53:38] [PASSED] 63 VFs
[23:53:38] ==================== [PASSED] fair_vram ====================
[23:53:38] ================== [PASSED] pf_gt_config ===================
[23:53:38] ===================== lmtt (1 subtest) =====================
[23:53:38] ======================== test_ops  =========================
[23:53:38] [PASSED] 2-level
[23:53:38] [PASSED] multi-level
[23:53:38] ==================== [PASSED] test_ops =====================
[23:53:38] ====================== [PASSED] lmtt =======================
[23:53:38] ================= pf_service (11 subtests) =================
[23:53:38] [PASSED] pf_negotiate_any
[23:53:38] [PASSED] pf_negotiate_base_match
[23:53:38] [PASSED] pf_negotiate_base_newer
[23:53:38] [PASSED] pf_negotiate_base_next
[23:53:38] [SKIPPED] pf_negotiate_base_older
[23:53:38] [PASSED] pf_negotiate_base_prev
[23:53:38] [PASSED] pf_negotiate_latest_match
[23:53:38] [PASSED] pf_negotiate_latest_newer
[23:53:38] [PASSED] pf_negotiate_latest_next
[23:53:38] [SKIPPED] pf_negotiate_latest_older
[23:53:38] [SKIPPED] pf_negotiate_latest_prev
[23:53:38] =================== [PASSED] pf_service ====================
[23:53:38] ================= xe_guc_g2g (2 subtests) ==================
[23:53:38] ============== xe_live_guc_g2g_kunit_default  ==============
[23:53:38] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[23:53:38] ============== xe_live_guc_g2g_kunit_allmem  ===============
[23:53:38] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[23:53:38] =================== [SKIPPED] xe_guc_g2g ===================
[23:53:38] =================== xe_mocs (2 subtests) ===================
[23:53:38] ================ xe_live_mocs_kernel_kunit  ================
[23:53:38] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[23:53:38] ================ xe_live_mocs_reset_kunit  =================
[23:53:38] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[23:53:38] ==================== [SKIPPED] xe_mocs =====================
[23:53:38] ================= xe_migrate (2 subtests) ==================
[23:53:38] ================= xe_migrate_sanity_kunit  =================
[23:53:38] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[23:53:38] ================== xe_validate_ccs_kunit  ==================
[23:53:38] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[23:53:38] =================== [SKIPPED] xe_migrate ===================
[23:53:38] ================== xe_dma_buf (1 subtest) ==================
[23:53:38] ==================== xe_dma_buf_kunit  =====================
[23:53:38] ================ [SKIPPED] xe_dma_buf_kunit ================
[23:53:38] =================== [SKIPPED] xe_dma_buf ===================
[23:53:38] ================= xe_bo_shrink (1 subtest) =================
[23:53:38] =================== xe_bo_shrink_kunit  ====================
[23:53:38] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[23:53:38] ================== [SKIPPED] xe_bo_shrink ==================
[23:53:38] ==================== xe_bo (2 subtests) ====================
[23:53:38] ================== xe_ccs_migrate_kunit  ===================
[23:53:38] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[23:53:38] ==================== xe_bo_evict_kunit  ====================
[23:53:38] =============== [SKIPPED] xe_bo_evict_kunit ================
[23:53:38] ===================== [SKIPPED] xe_bo ======================
[23:53:38] ==================== args (13 subtests) ====================
[23:53:38] [PASSED] count_args_test
[23:53:38] [PASSED] call_args_example
[23:53:38] [PASSED] call_args_test
[23:53:38] [PASSED] drop_first_arg_example
[23:53:38] [PASSED] drop_first_arg_test
[23:53:38] [PASSED] first_arg_example
[23:53:38] [PASSED] first_arg_test
[23:53:38] [PASSED] last_arg_example
[23:53:38] [PASSED] last_arg_test
[23:53:38] [PASSED] pick_arg_example
[23:53:38] [PASSED] if_args_example
[23:53:38] [PASSED] if_args_test
[23:53:38] [PASSED] sep_comma_example
[23:53:38] ====================== [PASSED] args =======================
[23:53:38] =================== xe_pci (3 subtests) ====================
[23:53:38] ==================== check_graphics_ip  ====================
[23:53:38] [PASSED] 12.00 Xe_LP
[23:53:38] [PASSED] 12.10 Xe_LP+
[23:53:38] [PASSED] 12.55 Xe_HPG
[23:53:38] [PASSED] 12.60 Xe_HPC
[23:53:38] [PASSED] 12.70 Xe_LPG
[23:53:38] [PASSED] 12.71 Xe_LPG
[23:53:38] [PASSED] 12.74 Xe_LPG+
[23:53:38] [PASSED] 20.01 Xe2_HPG
[23:53:38] [PASSED] 20.02 Xe2_HPG
[23:53:38] [PASSED] 20.04 Xe2_LPG
[23:53:38] [PASSED] 30.00 Xe3_LPG
[23:53:38] [PASSED] 30.01 Xe3_LPG
[23:53:38] [PASSED] 30.03 Xe3_LPG
[23:53:38] [PASSED] 30.04 Xe3_LPG
[23:53:38] [PASSED] 30.05 Xe3_LPG
[23:53:38] [PASSED] 35.10 Xe3p_LPG
[23:53:38] [PASSED] 35.11 Xe3p_XPC
[23:53:38] ================ [PASSED] check_graphics_ip ================
[23:53:38] ===================== check_media_ip  ======================
[23:53:38] [PASSED] 12.00 Xe_M
[23:53:38] [PASSED] 12.55 Xe_HPM
[23:53:38] [PASSED] 13.00 Xe_LPM+
[23:53:38] [PASSED] 13.01 Xe2_HPM
[23:53:38] [PASSED] 20.00 Xe2_LPM
[23:53:38] [PASSED] 30.00 Xe3_LPM
[23:53:38] [PASSED] 30.02 Xe3_LPM
[23:53:38] [PASSED] 35.00 Xe3p_LPM
[23:53:38] [PASSED] 35.03 Xe3p_HPM
[23:53:38] ================= [PASSED] check_media_ip ==================
[23:53:38] =================== check_platform_desc  ===================
[23:53:38] [PASSED] 0x9A60 (TIGERLAKE)
[23:53:38] [PASSED] 0x9A68 (TIGERLAKE)
[23:53:38] [PASSED] 0x9A70 (TIGERLAKE)
[23:53:38] [PASSED] 0x9A40 (TIGERLAKE)
[23:53:38] [PASSED] 0x9A49 (TIGERLAKE)
[23:53:38] [PASSED] 0x9A59 (TIGERLAKE)
[23:53:38] [PASSED] 0x9A78 (TIGERLAKE)
[23:53:38] [PASSED] 0x9AC0 (TIGERLAKE)
[23:53:38] [PASSED] 0x9AC9 (TIGERLAKE)
[23:53:38] [PASSED] 0x9AD9 (TIGERLAKE)
[23:53:38] [PASSED] 0x9AF8 (TIGERLAKE)
[23:53:38] [PASSED] 0x4C80 (ROCKETLAKE)
[23:53:38] [PASSED] 0x4C8A (ROCKETLAKE)
[23:53:38] [PASSED] 0x4C8B (ROCKETLAKE)
[23:53:38] [PASSED] 0x4C8C (ROCKETLAKE)
[23:53:38] [PASSED] 0x4C90 (ROCKETLAKE)
[23:53:38] [PASSED] 0x4C9A (ROCKETLAKE)
[23:53:38] [PASSED] 0x4680 (ALDERLAKE_S)
[23:53:38] [PASSED] 0x4682 (ALDERLAKE_S)
[23:53:38] [PASSED] 0x4688 (ALDERLAKE_S)
[23:53:38] [PASSED] 0x468A (ALDERLAKE_S)
[23:53:38] [PASSED] 0x468B (ALDERLAKE_S)
[23:53:38] [PASSED] 0x4690 (ALDERLAKE_S)
[23:53:38] [PASSED] 0x4692 (ALDERLAKE_S)
[23:53:38] [PASSED] 0x4693 (ALDERLAKE_S)
[23:53:38] [PASSED] 0x46A0 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46A1 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46A2 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46A3 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46A6 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46A8 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46AA (ALDERLAKE_P)
[23:53:38] [PASSED] 0x462A (ALDERLAKE_P)
[23:53:38] [PASSED] 0x4626 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x4628 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46B0 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46B1 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46B2 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46B3 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46C0 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46C1 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46C2 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46C3 (ALDERLAKE_P)
[23:53:38] [PASSED] 0x46D0 (ALDERLAKE_N)
[23:53:38] [PASSED] 0x46D1 (ALDERLAKE_N)
[23:53:38] [PASSED] 0x46D2 (ALDERLAKE_N)
[23:53:38] [PASSED] 0x46D3 (ALDERLAKE_N)
[23:53:38] [PASSED] 0x46D4 (ALDERLAKE_N)
[23:53:38] [PASSED] 0xA721 (ALDERLAKE_P)
[23:53:38] [PASSED] 0xA7A1 (ALDERLAKE_P)
[23:53:38] [PASSED] 0xA7A9 (ALDERLAKE_P)
[23:53:38] [PASSED] 0xA7AC (ALDERLAKE_P)
[23:53:38] [PASSED] 0xA7AD (ALDERLAKE_P)
[23:53:38] [PASSED] 0xA720 (ALDERLAKE_P)
[23:53:38] [PASSED] 0xA7A0 (ALDERLAKE_P)
[23:53:38] [PASSED] 0xA7A8 (ALDERLAKE_P)
[23:53:38] [PASSED] 0xA7AA (ALDERLAKE_P)
[23:53:38] [PASSED] 0xA7AB (ALDERLAKE_P)
[23:53:38] [PASSED] 0xA780 (ALDERLAKE_S)
[23:53:38] [PASSED] 0xA781 (ALDERLAKE_S)
[23:53:38] [PASSED] 0xA782 (ALDERLAKE_S)
[23:53:38] [PASSED] 0xA783 (ALDERLAKE_S)
[23:53:38] [PASSED] 0xA788 (ALDERLAKE_S)
[23:53:38] [PASSED] 0xA789 (ALDERLAKE_S)
[23:53:38] [PASSED] 0xA78A (ALDERLAKE_S)
[23:53:38] [PASSED] 0xA78B (ALDERLAKE_S)
[23:53:38] [PASSED] 0x4905 (DG1)
[23:53:38] [PASSED] 0x4906 (DG1)
[23:53:38] [PASSED] 0x4907 (DG1)
[23:53:38] [PASSED] 0x4908 (DG1)
[23:53:38] [PASSED] 0x4909 (DG1)
[23:53:38] [PASSED] 0x56C0 (DG2)
[23:53:38] [PASSED] 0x56C2 (DG2)
[23:53:38] [PASSED] 0x56C1 (DG2)
[23:53:38] [PASSED] 0x7D51 (METEORLAKE)
[23:53:38] [PASSED] 0x7DD1 (METEORLAKE)
[23:53:38] [PASSED] 0x7D41 (METEORLAKE)
[23:53:38] [PASSED] 0x7D67 (METEORLAKE)
[23:53:38] [PASSED] 0xB640 (METEORLAKE)
[23:53:38] [PASSED] 0x56A0 (DG2)
[23:53:38] [PASSED] 0x56A1 (DG2)
[23:53:38] [PASSED] 0x56A2 (DG2)
[23:53:38] [PASSED] 0x56BE (DG2)
[23:53:38] [PASSED] 0x56BF (DG2)
[23:53:38] [PASSED] 0x5690 (DG2)
[23:53:38] [PASSED] 0x5691 (DG2)
[23:53:38] [PASSED] 0x5692 (DG2)
[23:53:38] [PASSED] 0x56A5 (DG2)
[23:53:38] [PASSED] 0x56A6 (DG2)
[23:53:38] [PASSED] 0x56B0 (DG2)
[23:53:38] [PASSED] 0x56B1 (DG2)
[23:53:38] [PASSED] 0x56BA (DG2)
[23:53:38] [PASSED] 0x56BB (DG2)
[23:53:38] [PASSED] 0x56BC (DG2)
[23:53:38] [PASSED] 0x56BD (DG2)
[23:53:38] [PASSED] 0x5693 (DG2)
[23:53:38] [PASSED] 0x5694 (DG2)
[23:53:38] [PASSED] 0x5695 (DG2)
[23:53:38] [PASSED] 0x56A3 (DG2)
[23:53:38] [PASSED] 0x56A4 (DG2)
[23:53:38] [PASSED] 0x56B2 (DG2)
[23:53:38] [PASSED] 0x56B3 (DG2)
[23:53:38] [PASSED] 0x5696 (DG2)
[23:53:38] [PASSED] 0x5697 (DG2)
[23:53:38] [PASSED] 0xB69 (PVC)
[23:53:38] [PASSED] 0xB6E (PVC)
[23:53:38] [PASSED] 0xBD4 (PVC)
[23:53:38] [PASSED] 0xBD5 (PVC)
[23:53:38] [PASSED] 0xBD6 (PVC)
[23:53:38] [PASSED] 0xBD7 (PVC)
[23:53:38] [PASSED] 0xBD8 (PVC)
[23:53:38] [PASSED] 0xBD9 (PVC)
[23:53:38] [PASSED] 0xBDA (PVC)
[23:53:38] [PASSED] 0xBDB (PVC)
[23:53:38] [PASSED] 0xBE0 (PVC)
[23:53:38] [PASSED] 0xBE1 (PVC)
[23:53:38] [PASSED] 0xBE5 (PVC)
[23:53:38] [PASSED] 0x7D40 (METEORLAKE)
[23:53:38] [PASSED] 0x7D45 (METEORLAKE)
[23:53:38] [PASSED] 0x7D55 (METEORLAKE)
[23:53:38] [PASSED] 0x7D60 (METEORLAKE)
[23:53:38] [PASSED] 0x7DD5 (METEORLAKE)
[23:53:38] [PASSED] 0x6420 (LUNARLAKE)
[23:53:38] [PASSED] 0x64A0 (LUNARLAKE)
[23:53:38] [PASSED] 0x64B0 (LUNARLAKE)
[23:53:38] [PASSED] 0xE202 (BATTLEMAGE)
[23:53:38] [PASSED] 0xE209 (BATTLEMAGE)
[23:53:38] [PASSED] 0xE20B (BATTLEMAGE)
[23:53:38] [PASSED] 0xE20C (BATTLEMAGE)
[23:53:38] [PASSED] 0xE20D (BATTLEMAGE)
[23:53:38] [PASSED] 0xE210 (BATTLEMAGE)
[23:53:38] [PASSED] 0xE211 (BATTLEMAGE)
[23:53:38] [PASSED] 0xE212 (BATTLEMAGE)
[23:53:38] [PASSED] 0xE216 (BATTLEMAGE)
[23:53:38] [PASSED] 0xE220 (BATTLEMAGE)
[23:53:38] [PASSED] 0xE221 (BATTLEMAGE)
[23:53:38] [PASSED] 0xE222 (BATTLEMAGE)
[23:53:38] [PASSED] 0xE223 (BATTLEMAGE)
[23:53:38] [PASSED] 0xB080 (PANTHERLAKE)
[23:53:38] [PASSED] 0xB081 (PANTHERLAKE)
[23:53:38] [PASSED] 0xB082 (PANTHERLAKE)
[23:53:38] [PASSED] 0xB083 (PANTHERLAKE)
[23:53:38] [PASSED] 0xB084 (PANTHERLAKE)
[23:53:38] [PASSED] 0xB085 (PANTHERLAKE)
[23:53:38] [PASSED] 0xB086 (PANTHERLAKE)
[23:53:38] [PASSED] 0xB087 (PANTHERLAKE)
[23:53:38] [PASSED] 0xB08F (PANTHERLAKE)
[23:53:38] [PASSED] 0xB090 (PANTHERLAKE)
[23:53:38] [PASSED] 0xB0A0 (PANTHERLAKE)
[23:53:38] [PASSED] 0xB0B0 (PANTHERLAKE)
[23:53:38] [PASSED] 0xFD80 (PANTHERLAKE)
[23:53:38] [PASSED] 0xFD81 (PANTHERLAKE)
[23:53:38] [PASSED] 0xD740 (NOVALAKE_S)
[23:53:38] [PASSED] 0xD741 (NOVALAKE_S)
[23:53:38] [PASSED] 0xD742 (NOVALAKE_S)
[23:53:38] [PASSED] 0xD743 (NOVALAKE_S)
[23:53:38] [PASSED] 0xD744 (NOVALAKE_S)
[23:53:38] [PASSED] 0xD745 (NOVALAKE_S)
[23:53:38] [PASSED] 0x674C (CRESCENTISLAND)
[23:53:38] [PASSED] 0x674D (CRESCENTISLAND)
[23:53:38] [PASSED] 0x674E (CRESCENTISLAND)
[23:53:38] [PASSED] 0x674F (CRESCENTISLAND)
[23:53:38] [PASSED] 0x6750 (CRESCENTISLAND)
[23:53:38] [PASSED] 0xD750 (NOVALAKE_P)
[23:53:38] [PASSED] 0xD751 (NOVALAKE_P)
[23:53:38] [PASSED] 0xD752 (NOVALAKE_P)
[23:53:38] [PASSED] 0xD753 (NOVALAKE_P)
[23:53:38] [PASSED] 0xD754 (NOVALAKE_P)
[23:53:38] [PASSED] 0xD755 (NOVALAKE_P)
[23:53:38] [PASSED] 0xD756 (NOVALAKE_P)
[23:53:38] [PASSED] 0xD757 (NOVALAKE_P)
[23:53:38] [PASSED] 0xD75F (NOVALAKE_P)
[23:53:38] =============== [PASSED] check_platform_desc ===============
[23:53:38] ===================== [PASSED] xe_pci ======================
[23:53:38] =================== xe_rtp (2 subtests) ====================
[23:53:38] =============== xe_rtp_process_to_sr_tests  ================
[23:53:38] [PASSED] coalesce-same-reg
[23:53:38] [PASSED] no-match-no-add
[23:53:38] [PASSED] match-or
[23:53:38] [PASSED] match-or-xfail
[23:53:38] [PASSED] no-match-no-add-multiple-rules
[23:53:38] [PASSED] two-regs-two-entries
[23:53:38] [PASSED] clr-one-set-other
[23:53:38] [PASSED] set-field
[23:53:38] [PASSED] conflict-duplicate
[23:53:38] [PASSED] conflict-not-disjoint
[23:53:38] [PASSED] conflict-reg-type
[23:53:38] [PASSED] bad-mcr-reg-forced-to-regular
[23:53:38] [PASSED] bad-regular-reg-forced-to-mcr
[23:53:38] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[23:53:38] ================== xe_rtp_process_tests  ===================
[23:53:38] [PASSED] active1
[23:53:38] [PASSED] active2
[23:53:38] [PASSED] active-inactive
[23:53:38] [PASSED] inactive-active
[23:53:38] [PASSED] inactive-1st_or_active-inactive
[23:53:38] [PASSED] inactive-2nd_or_active-inactive
[23:53:38] [PASSED] inactive-last_or_active-inactive
[23:53:38] [PASSED] inactive-no_or_active-inactive
[23:53:38] ============== [PASSED] xe_rtp_process_tests ===============
[23:53:38] ===================== [PASSED] xe_rtp ======================
[23:53:38] ==================== xe_wa (1 subtest) =====================
[23:53:38] ======================== xe_wa_gt  =========================
[23:53:38] [PASSED] TIGERLAKE B0
[23:53:38] [PASSED] DG1 A0
[23:53:38] [PASSED] DG1 B0
[23:53:38] [PASSED] ALDERLAKE_S A0
[23:53:38] [PASSED] ALDERLAKE_S B0
[23:53:38] [PASSED] ALDERLAKE_S C0
[23:53:38] [PASSED] ALDERLAKE_S D0
[23:53:38] [PASSED] ALDERLAKE_P A0
[23:53:38] [PASSED] ALDERLAKE_P B0
[23:53:38] [PASSED] ALDERLAKE_P C0
[23:53:38] [PASSED] ALDERLAKE_S RPLS D0
[23:53:38] [PASSED] ALDERLAKE_P RPLU E0
[23:53:38] [PASSED] DG2 G10 C0
[23:53:38] [PASSED] DG2 G11 B1
[23:53:38] [PASSED] DG2 G12 A1
[23:53:38] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:53:38] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[23:53:38] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[23:53:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[23:53:38] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[23:53:38] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[23:53:38] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[23:53:38] ==================== [PASSED] xe_wa_gt =====================
[23:53:38] ====================== [PASSED] xe_wa ======================
[23:53:38] ============================================================
[23:53:38] Testing complete. Ran 603 tests: passed: 585, skipped: 18
[23:53:38] Elapsed time: 36.120s total, 4.363s configuring, 31.141s building, 0.610s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[23:53:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:53:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:54:04] Starting KUnit Kernel (1/1)...
[23:54:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:54:05] ============ drm_test_pick_cmdline (2 subtests) ============
[23:54:05] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[23:54:05] =============== drm_test_pick_cmdline_named  ===============
[23:54:05] [PASSED] NTSC
[23:54:05] [PASSED] NTSC-J
[23:54:05] [PASSED] PAL
[23:54:05] [PASSED] PAL-M
[23:54:05] =========== [PASSED] drm_test_pick_cmdline_named ===========
[23:54:05] ============== [PASSED] drm_test_pick_cmdline ==============
[23:54:05] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[23:54:05] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[23:54:05] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[23:54:05] =========== drm_validate_clone_mode (2 subtests) ===========
[23:54:05] ============== drm_test_check_in_clone_mode  ===============
[23:54:05] [PASSED] in_clone_mode
[23:54:05] [PASSED] not_in_clone_mode
[23:54:05] ========== [PASSED] drm_test_check_in_clone_mode ===========
[23:54:05] =============== drm_test_check_valid_clones  ===============
[23:54:05] [PASSED] not_in_clone_mode
[23:54:05] [PASSED] valid_clone
[23:54:05] [PASSED] invalid_clone
[23:54:05] =========== [PASSED] drm_test_check_valid_clones ===========
[23:54:05] ============= [PASSED] drm_validate_clone_mode =============
[23:54:05] ============= drm_validate_modeset (1 subtest) =============
[23:54:05] [PASSED] drm_test_check_connector_changed_modeset
[23:54:05] ============== [PASSED] drm_validate_modeset ===============
[23:54:05] ====== drm_test_bridge_get_current_state (2 subtests) ======
[23:54:05] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[23:54:05] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[23:54:05] ======== [PASSED] drm_test_bridge_get_current_state ========
[23:54:05] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[23:54:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[23:54:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[23:54:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[23:54:05] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[23:54:05] ============== drm_bridge_alloc (2 subtests) ===============
[23:54:05] [PASSED] drm_test_drm_bridge_alloc_basic
[23:54:05] [PASSED] drm_test_drm_bridge_alloc_get_put
[23:54:05] ================ [PASSED] drm_bridge_alloc =================
[23:54:05] ============= drm_cmdline_parser (40 subtests) =============
[23:54:05] [PASSED] drm_test_cmdline_force_d_only
[23:54:05] [PASSED] drm_test_cmdline_force_D_only_dvi
[23:54:05] [PASSED] drm_test_cmdline_force_D_only_hdmi
[23:54:05] [PASSED] drm_test_cmdline_force_D_only_not_digital
[23:54:05] [PASSED] drm_test_cmdline_force_e_only
[23:54:05] [PASSED] drm_test_cmdline_res
[23:54:05] [PASSED] drm_test_cmdline_res_vesa
[23:54:05] [PASSED] drm_test_cmdline_res_vesa_rblank
[23:54:05] [PASSED] drm_test_cmdline_res_rblank
[23:54:05] [PASSED] drm_test_cmdline_res_bpp
[23:54:05] [PASSED] drm_test_cmdline_res_refresh
[23:54:05] [PASSED] drm_test_cmdline_res_bpp_refresh
[23:54:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[23:54:05] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[23:54:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[23:54:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[23:54:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[23:54:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[23:54:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[23:54:05] [PASSED] drm_test_cmdline_res_margins_force_on
[23:54:05] [PASSED] drm_test_cmdline_res_vesa_margins
[23:54:05] [PASSED] drm_test_cmdline_name
[23:54:05] [PASSED] drm_test_cmdline_name_bpp
[23:54:05] [PASSED] drm_test_cmdline_name_option
[23:54:05] [PASSED] drm_test_cmdline_name_bpp_option
[23:54:05] [PASSED] drm_test_cmdline_rotate_0
[23:54:05] [PASSED] drm_test_cmdline_rotate_90
[23:54:05] [PASSED] drm_test_cmdline_rotate_180
[23:54:05] [PASSED] drm_test_cmdline_rotate_270
[23:54:05] [PASSED] drm_test_cmdline_hmirror
[23:54:05] [PASSED] drm_test_cmdline_vmirror
[23:54:05] [PASSED] drm_test_cmdline_margin_options
[23:54:05] [PASSED] drm_test_cmdline_multiple_options
[23:54:05] [PASSED] drm_test_cmdline_bpp_extra_and_option
[23:54:05] [PASSED] drm_test_cmdline_extra_and_option
[23:54:05] [PASSED] drm_test_cmdline_freestanding_options
[23:54:05] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[23:54:05] [PASSED] drm_test_cmdline_panel_orientation
[23:54:05] ================ drm_test_cmdline_invalid  =================
[23:54:05] [PASSED] margin_only
[23:54:05] [PASSED] interlace_only
[23:54:05] [PASSED] res_missing_x
[23:54:05] [PASSED] res_missing_y
[23:54:05] [PASSED] res_bad_y
[23:54:05] [PASSED] res_missing_y_bpp
[23:54:05] [PASSED] res_bad_bpp
[23:54:05] [PASSED] res_bad_refresh
[23:54:05] [PASSED] res_bpp_refresh_force_on_off
[23:54:05] [PASSED] res_invalid_mode
[23:54:05] [PASSED] res_bpp_wrong_place_mode
[23:54:05] [PASSED] name_bpp_refresh
[23:54:05] [PASSED] name_refresh
[23:54:05] [PASSED] name_refresh_wrong_mode
[23:54:05] [PASSED] name_refresh_invalid_mode
[23:54:05] [PASSED] rotate_multiple
[23:54:05] [PASSED] rotate_invalid_val
[23:54:05] [PASSED] rotate_truncated
[23:54:05] [PASSED] invalid_option
[23:54:05] [PASSED] invalid_tv_option
[23:54:05] [PASSED] truncated_tv_option
[23:54:05] ============ [PASSED] drm_test_cmdline_invalid =============
[23:54:05] =============== drm_test_cmdline_tv_options  ===============
[23:54:05] [PASSED] NTSC
[23:54:05] [PASSED] NTSC_443
[23:54:05] [PASSED] NTSC_J
[23:54:05] [PASSED] PAL
[23:54:05] [PASSED] PAL_M
[23:54:05] [PASSED] PAL_N
[23:54:05] [PASSED] SECAM
[23:54:05] [PASSED] MONO_525
[23:54:05] [PASSED] MONO_625
[23:54:05] =========== [PASSED] drm_test_cmdline_tv_options ===========
[23:54:05] =============== [PASSED] drm_cmdline_parser ================
[23:54:05] ========== drmm_connector_hdmi_init (20 subtests) ==========
[23:54:05] [PASSED] drm_test_connector_hdmi_init_valid
[23:54:05] [PASSED] drm_test_connector_hdmi_init_bpc_8
[23:54:05] [PASSED] drm_test_connector_hdmi_init_bpc_10
[23:54:05] [PASSED] drm_test_connector_hdmi_init_bpc_12
[23:54:05] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[23:54:05] [PASSED] drm_test_connector_hdmi_init_bpc_null
[23:54:05] [PASSED] drm_test_connector_hdmi_init_formats_empty
[23:54:05] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[23:54:05] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[23:54:05] [PASSED] supported_formats=0x9 yuv420_allowed=1
[23:54:05] [PASSED] supported_formats=0x9 yuv420_allowed=0
[23:54:05] [PASSED] supported_formats=0x5 yuv420_allowed=1
[23:54:05] [PASSED] supported_formats=0x5 yuv420_allowed=0
[23:54:05] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[23:54:05] [PASSED] drm_test_connector_hdmi_init_null_ddc
[23:54:05] [PASSED] drm_test_connector_hdmi_init_null_product
[23:54:05] [PASSED] drm_test_connector_hdmi_init_null_vendor
[23:54:05] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[23:54:05] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[23:54:05] [PASSED] drm_test_connector_hdmi_init_product_valid
[23:54:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[23:54:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[23:54:05] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[23:54:05] ========= drm_test_connector_hdmi_init_type_valid  =========
[23:54:05] [PASSED] HDMI-A
[23:54:05] [PASSED] HDMI-B
[23:54:05] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[23:54:05] ======== drm_test_connector_hdmi_init_type_invalid  ========
[23:54:05] [PASSED] Unknown
[23:54:05] [PASSED] VGA
[23:54:05] [PASSED] DVI-I
[23:54:05] [PASSED] DVI-D
[23:54:05] [PASSED] DVI-A
[23:54:05] [PASSED] Composite
[23:54:05] [PASSED] SVIDEO
[23:54:05] [PASSED] LVDS
[23:54:05] [PASSED] Component
[23:54:05] [PASSED] DIN
[23:54:05] [PASSED] DP
[23:54:05] [PASSED] TV
[23:54:05] [PASSED] eDP
[23:54:05] [PASSED] Virtual
[23:54:05] [PASSED] DSI
[23:54:05] [PASSED] DPI
[23:54:05] [PASSED] Writeback
[23:54:05] [PASSED] SPI
[23:54:05] [PASSED] USB
[23:54:05] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[23:54:05] ============ [PASSED] drmm_connector_hdmi_init =============
[23:54:05] ============= drmm_connector_init (3 subtests) =============
[23:54:05] [PASSED] drm_test_drmm_connector_init
[23:54:05] [PASSED] drm_test_drmm_connector_init_null_ddc
[23:54:05] ========= drm_test_drmm_connector_init_type_valid  =========
[23:54:05] [PASSED] Unknown
[23:54:05] [PASSED] VGA
[23:54:05] [PASSED] DVI-I
[23:54:05] [PASSED] DVI-D
[23:54:05] [PASSED] DVI-A
[23:54:05] [PASSED] Composite
[23:54:05] [PASSED] SVIDEO
[23:54:05] [PASSED] LVDS
[23:54:05] [PASSED] Component
[23:54:05] [PASSED] DIN
[23:54:05] [PASSED] DP
[23:54:05] [PASSED] HDMI-A
[23:54:05] [PASSED] HDMI-B
[23:54:05] [PASSED] TV
[23:54:05] [PASSED] eDP
[23:54:05] [PASSED] Virtual
[23:54:05] [PASSED] DSI
[23:54:05] [PASSED] DPI
[23:54:05] [PASSED] Writeback
[23:54:05] [PASSED] SPI
[23:54:05] [PASSED] USB
[23:54:05] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[23:54:05] =============== [PASSED] drmm_connector_init ===============
[23:54:05] ========= drm_connector_dynamic_init (6 subtests) ==========
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_init
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_init_properties
[23:54:05] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[23:54:05] [PASSED] Unknown
[23:54:05] [PASSED] VGA
[23:54:05] [PASSED] DVI-I
[23:54:05] [PASSED] DVI-D
[23:54:05] [PASSED] DVI-A
[23:54:05] [PASSED] Composite
[23:54:05] [PASSED] SVIDEO
[23:54:05] [PASSED] LVDS
[23:54:05] [PASSED] Component
[23:54:05] [PASSED] DIN
[23:54:05] [PASSED] DP
[23:54:05] [PASSED] HDMI-A
[23:54:05] [PASSED] HDMI-B
[23:54:05] [PASSED] TV
[23:54:05] [PASSED] eDP
[23:54:05] [PASSED] Virtual
[23:54:05] [PASSED] DSI
[23:54:05] [PASSED] DPI
[23:54:05] [PASSED] Writeback
[23:54:05] [PASSED] SPI
[23:54:05] [PASSED] USB
[23:54:05] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[23:54:05] ======== drm_test_drm_connector_dynamic_init_name  =========
[23:54:05] [PASSED] Unknown
[23:54:05] [PASSED] VGA
[23:54:05] [PASSED] DVI-I
[23:54:05] [PASSED] DVI-D
[23:54:05] [PASSED] DVI-A
[23:54:05] [PASSED] Composite
[23:54:05] [PASSED] SVIDEO
[23:54:05] [PASSED] LVDS
[23:54:05] [PASSED] Component
[23:54:05] [PASSED] DIN
[23:54:05] [PASSED] DP
[23:54:05] [PASSED] HDMI-A
[23:54:05] [PASSED] HDMI-B
[23:54:05] [PASSED] TV
[23:54:05] [PASSED] eDP
[23:54:05] [PASSED] Virtual
[23:54:05] [PASSED] DSI
[23:54:05] [PASSED] DPI
[23:54:05] [PASSED] Writeback
[23:54:05] [PASSED] SPI
[23:54:05] [PASSED] USB
[23:54:05] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[23:54:05] =========== [PASSED] drm_connector_dynamic_init ============
[23:54:05] ==== drm_connector_dynamic_register_early (4 subtests) =====
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[23:54:05] ====== [PASSED] drm_connector_dynamic_register_early =======
[23:54:05] ======= drm_connector_dynamic_register (7 subtests) ========
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[23:54:05] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[23:54:05] ========= [PASSED] drm_connector_dynamic_register ==========
[23:54:05] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[23:54:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[23:54:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[23:54:05] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[23:54:05] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[23:54:05] ========== drm_test_get_tv_mode_from_name_valid  ===========
[23:54:05] [PASSED] NTSC
[23:54:05] [PASSED] NTSC-443
[23:54:05] [PASSED] NTSC-J
[23:54:05] [PASSED] PAL
[23:54:05] [PASSED] PAL-M
[23:54:05] [PASSED] PAL-N
[23:54:05] [PASSED] SECAM
[23:54:05] [PASSED] Mono
[23:54:05] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[23:54:05] [PASSED] drm_test_get_tv_mode_from_name_truncated
[23:54:05] ============ [PASSED] drm_get_tv_mode_from_name ============
[23:54:05] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[23:54:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[23:54:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[23:54:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[23:54:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[23:54:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[23:54:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[23:54:05] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[23:54:05] [PASSED] VIC 96
[23:54:05] [PASSED] VIC 97
[23:54:05] [PASSED] VIC 101
[23:54:05] [PASSED] VIC 102
[23:54:05] [PASSED] VIC 106
[23:54:05] [PASSED] VIC 107
[23:54:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[23:54:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[23:54:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[23:54:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[23:54:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[23:54:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[23:54:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[23:54:05] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[23:54:05] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[23:54:05] [PASSED] Automatic
[23:54:05] [PASSED] Full
[23:54:05] [PASSED] Limited 16:235
[23:54:05] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[23:54:05] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[23:54:05] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[23:54:05] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[23:54:05] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[23:54:05] [PASSED] RGB
[23:54:05] [PASSED] YUV 4:2:0
[23:54:05] [PASSED] YUV 4:2:2
[23:54:05] [PASSED] YUV 4:4:4
[23:54:05] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[23:54:05] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[23:54:05] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[23:54:05] ============= drm_damage_helper (21 subtests) ==============
[23:54:05] [PASSED] drm_test_damage_iter_no_damage
[23:54:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[23:54:05] [PASSED] drm_test_damage_iter_no_damage_src_moved
[23:54:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[23:54:05] [PASSED] drm_test_damage_iter_no_damage_not_visible
[23:54:05] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[23:54:05] [PASSED] drm_test_damage_iter_no_damage_no_fb
[23:54:05] [PASSED] drm_test_damage_iter_simple_damage
[23:54:05] [PASSED] drm_test_damage_iter_single_damage
[23:54:05] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[23:54:05] [PASSED] drm_test_damage_iter_single_damage_outside_src
[23:54:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[23:54:05] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[23:54:05] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[23:54:05] [PASSED] drm_test_damage_iter_single_damage_src_moved
[23:54:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[23:54:05] [PASSED] drm_test_damage_iter_damage
[23:54:05] [PASSED] drm_test_damage_iter_damage_one_intersect
[23:54:05] [PASSED] drm_test_damage_iter_damage_one_outside
[23:54:05] [PASSED] drm_test_damage_iter_damage_src_moved
[23:54:05] [PASSED] drm_test_damage_iter_damage_not_visible
[23:54:05] ================ [PASSED] drm_damage_helper ================
[23:54:05] ============== drm_dp_mst_helper (3 subtests) ==============
[23:54:05] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[23:54:05] [PASSED] Clock 154000 BPP 30 DSC disabled
[23:54:05] [PASSED] Clock 234000 BPP 30 DSC disabled
[23:54:05] [PASSED] Clock 297000 BPP 24 DSC disabled
[23:54:05] [PASSED] Clock 332880 BPP 24 DSC enabled
[23:54:05] [PASSED] Clock 324540 BPP 24 DSC enabled
[23:54:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[23:54:05] ============== drm_test_dp_mst_calc_pbn_div  ===============
[23:54:05] [PASSED] Link rate 2000000 lane count 4
[23:54:05] [PASSED] Link rate 2000000 lane count 2
[23:54:05] [PASSED] Link rate 2000000 lane count 1
[23:54:05] [PASSED] Link rate 1350000 lane count 4
[23:54:05] [PASSED] Link rate 1350000 lane count 2
[23:54:05] [PASSED] Link rate 1350000 lane count 1
[23:54:05] [PASSED] Link rate 1000000 lane count 4
[23:54:05] [PASSED] Link rate 1000000 lane count 2
[23:54:05] [PASSED] Link rate 1000000 lane count 1
[23:54:05] [PASSED] Link rate 810000 lane count 4
[23:54:05] [PASSED] Link rate 810000 lane count 2
[23:54:05] [PASSED] Link rate 810000 lane count 1
[23:54:05] [PASSED] Link rate 540000 lane count 4
[23:54:05] [PASSED] Link rate 540000 lane count 2
[23:54:05] [PASSED] Link rate 540000 lane count 1
[23:54:05] [PASSED] Link rate 270000 lane count 4
[23:54:05] [PASSED] Link rate 270000 lane count 2
[23:54:05] [PASSED] Link rate 270000 lane count 1
[23:54:05] [PASSED] Link rate 162000 lane count 4
[23:54:05] [PASSED] Link rate 162000 lane count 2
[23:54:05] [PASSED] Link rate 162000 lane count 1
[23:54:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[23:54:05] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[23:54:05] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[23:54:05] [PASSED] DP_POWER_UP_PHY with port number
[23:54:05] [PASSED] DP_POWER_DOWN_PHY with port number
[23:54:05] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[23:54:05] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[23:54:05] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[23:54:05] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[23:54:05] [PASSED] DP_QUERY_PAYLOAD with port number
[23:54:05] [PASSED] DP_QUERY_PAYLOAD with VCPI
[23:54:05] [PASSED] DP_REMOTE_DPCD_READ with port number
[23:54:05] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[23:54:05] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[23:54:05] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[23:54:05] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[23:54:05] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[23:54:05] [PASSED] DP_REMOTE_I2C_READ with port number
[23:54:05] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[23:54:05] [PASSED] DP_REMOTE_I2C_READ with transactions array
[23:54:05] [PASSED] DP_REMOTE_I2C_WRITE with port number
[23:54:05] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[23:54:05] [PASSED] DP_REMOTE_I2C_WRITE with data array
[23:54:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[23:54:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[23:54:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[23:54:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[23:54:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[23:54:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[23:54:05] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[23:54:05] ================ [PASSED] drm_dp_mst_helper ================
[23:54:05] ================== drm_exec (7 subtests) ===================
[23:54:05] [PASSED] sanitycheck
[23:54:05] [PASSED] test_lock
[23:54:05] [PASSED] test_lock_unlock
[23:54:05] [PASSED] test_duplicates
[23:54:05] [PASSED] test_prepare
[23:54:05] [PASSED] test_prepare_array
[23:54:05] [PASSED] test_multiple_loops
[23:54:05] ==================== [PASSED] drm_exec =====================
[23:54:05] =========== drm_format_helper_test (17 subtests) ===========
[23:54:05] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[23:54:05] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[23:54:05] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[23:54:05] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[23:54:05] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[23:54:05] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[23:54:05] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[23:54:05] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[23:54:05] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[23:54:05] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[23:54:05] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[23:54:05] ============== drm_test_fb_xrgb8888_to_mono  ===============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[23:54:05] ==================== drm_test_fb_swab  =====================
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ================ [PASSED] drm_test_fb_swab =================
[23:54:05] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[23:54:05] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[23:54:05] [PASSED] single_pixel_source_buffer
[23:54:05] [PASSED] single_pixel_clip_rectangle
[23:54:05] [PASSED] well_known_colors
[23:54:05] [PASSED] destination_pitch
[23:54:05] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[23:54:05] ================= drm_test_fb_clip_offset  =================
[23:54:05] [PASSED] pass through
[23:54:05] [PASSED] horizontal offset
[23:54:05] [PASSED] vertical offset
[23:54:05] [PASSED] horizontal and vertical offset
[23:54:05] [PASSED] horizontal offset (custom pitch)
[23:54:05] [PASSED] vertical offset (custom pitch)
[23:54:05] [PASSED] horizontal and vertical offset (custom pitch)
[23:54:05] ============= [PASSED] drm_test_fb_clip_offset =============
[23:54:05] =================== drm_test_fb_memcpy  ====================
[23:54:05] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[23:54:05] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[23:54:05] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[23:54:05] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[23:54:05] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[23:54:05] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[23:54:05] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[23:54:05] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[23:54:05] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[23:54:05] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[23:54:05] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[23:54:05] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[23:54:05] =============== [PASSED] drm_test_fb_memcpy ================
[23:54:05] ============= [PASSED] drm_format_helper_test ==============
[23:54:05] ================= drm_format (18 subtests) =================
[23:54:05] [PASSED] drm_test_format_block_width_invalid
[23:54:05] [PASSED] drm_test_format_block_width_one_plane
[23:54:05] [PASSED] drm_test_format_block_width_two_plane
[23:54:05] [PASSED] drm_test_format_block_width_three_plane
[23:54:05] [PASSED] drm_test_format_block_width_tiled
[23:54:05] [PASSED] drm_test_format_block_height_invalid
[23:54:05] [PASSED] drm_test_format_block_height_one_plane
[23:54:05] [PASSED] drm_test_format_block_height_two_plane
[23:54:05] [PASSED] drm_test_format_block_height_three_plane
[23:54:05] [PASSED] drm_test_format_block_height_tiled
[23:54:05] [PASSED] drm_test_format_min_pitch_invalid
[23:54:05] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[23:54:05] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[23:54:05] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[23:54:05] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[23:54:05] [PASSED] drm_test_format_min_pitch_two_plane
[23:54:05] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[23:54:05] [PASSED] drm_test_format_min_pitch_tiled
[23:54:05] =================== [PASSED] drm_format ====================
[23:54:05] ============== drm_framebuffer (10 subtests) ===============
[23:54:05] ========== drm_test_framebuffer_check_src_coords  ==========
[23:54:05] [PASSED] Success: source fits into fb
[23:54:05] [PASSED] Fail: overflowing fb with x-axis coordinate
[23:54:05] [PASSED] Fail: overflowing fb with y-axis coordinate
[23:54:05] [PASSED] Fail: overflowing fb with source width
[23:54:05] [PASSED] Fail: overflowing fb with source height
[23:54:05] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[23:54:05] [PASSED] drm_test_framebuffer_cleanup
[23:54:05] =============== drm_test_framebuffer_create  ===============
[23:54:05] [PASSED] ABGR8888 normal sizes
[23:54:05] [PASSED] ABGR8888 max sizes
[23:54:05] [PASSED] ABGR8888 pitch greater than min required
[23:54:05] [PASSED] ABGR8888 pitch less than min required
[23:54:05] [PASSED] ABGR8888 Invalid width
[23:54:05] [PASSED] ABGR8888 Invalid buffer handle
[23:54:05] [PASSED] No pixel format
[23:54:05] [PASSED] ABGR8888 Width 0
[23:54:05] [PASSED] ABGR8888 Height 0
[23:54:05] [PASSED] ABGR8888 Out of bound height * pitch combination
[23:54:05] [PASSED] ABGR8888 Large buffer offset
[23:54:05] [PASSED] ABGR8888 Buffer offset for inexistent plane
[23:54:05] [PASSED] ABGR8888 Invalid flag
[23:54:05] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[23:54:05] [PASSED] ABGR8888 Valid buffer modifier
[23:54:05] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[23:54:05] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[23:54:05] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[23:54:05] [PASSED] NV12 Normal sizes
[23:54:05] [PASSED] NV12 Max sizes
[23:54:05] [PASSED] NV12 Invalid pitch
[23:54:05] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[23:54:05] [PASSED] NV12 different  modifier per-plane
[23:54:05] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[23:54:05] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[23:54:05] [PASSED] NV12 Modifier for inexistent plane
[23:54:05] [PASSED] NV12 Handle for inexistent plane
[23:54:05] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[23:54:05] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[23:54:05] [PASSED] YVU420 Normal sizes
[23:54:05] [PASSED] YVU420 Max sizes
[23:54:05] [PASSED] YVU420 Invalid pitch
[23:54:05] [PASSED] YVU420 Different pitches
[23:54:05] [PASSED] YVU420 Different buffer offsets/pitches
[23:54:05] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[23:54:05] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[23:54:05] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[23:54:05] [PASSED] YVU420 Valid modifier
[23:54:05] [PASSED] YVU420 Different modifiers per plane
[23:54:05] [PASSED] YVU420 Modifier for inexistent plane
[23:54:05] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[23:54:05] [PASSED] X0L2 Normal sizes
[23:54:05] [PASSED] X0L2 Max sizes
[23:54:05] [PASSED] X0L2 Invalid pitch
[23:54:05] [PASSED] X0L2 Pitch greater than minimum required
[23:54:05] [PASSED] X0L2 Handle for inexistent plane
[23:54:05] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[23:54:05] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[23:54:05] [PASSED] X0L2 Valid modifier
[23:54:05] [PASSED] X0L2 Modifier for inexistent plane
[23:54:05] =========== [PASSED] drm_test_framebuffer_create ===========
[23:54:05] [PASSED] drm_test_framebuffer_free
[23:54:05] [PASSED] drm_test_framebuffer_init
[23:54:05] [PASSED] drm_test_framebuffer_init_bad_format
[23:54:05] [PASSED] drm_test_framebuffer_init_dev_mismatch
[23:54:05] [PASSED] drm_test_framebuffer_lookup
[23:54:05] [PASSED] drm_test_framebuffer_lookup_inexistent
[23:54:05] [PASSED] drm_test_framebuffer_modifiers_not_supported
[23:54:05] ================= [PASSED] drm_framebuffer =================
[23:54:05] ================ drm_gem_shmem (8 subtests) ================
[23:54:05] [PASSED] drm_gem_shmem_test_obj_create
[23:54:05] [PASSED] drm_gem_shmem_test_obj_create_private
[23:54:05] [PASSED] drm_gem_shmem_test_pin_pages
[23:54:05] [PASSED] drm_gem_shmem_test_vmap
[23:54:05] [PASSED] drm_gem_shmem_test_get_sg_table
[23:54:05] [PASSED] drm_gem_shmem_test_get_pages_sgt
[23:54:05] [PASSED] drm_gem_shmem_test_madvise
[23:54:05] [PASSED] drm_gem_shmem_test_purge
[23:54:05] ================== [PASSED] drm_gem_shmem ==================
[23:54:05] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[23:54:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[23:54:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[23:54:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[23:54:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[23:54:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[23:54:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[23:54:05] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[23:54:05] [PASSED] Automatic
[23:54:05] [PASSED] Full
[23:54:05] [PASSED] Limited 16:235
[23:54:05] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[23:54:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[23:54:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[23:54:05] [PASSED] drm_test_check_disable_connector
[23:54:05] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[23:54:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[23:54:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[23:54:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[23:54:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[23:54:05] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[23:54:05] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[23:54:05] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[23:54:05] [PASSED] drm_test_check_output_bpc_dvi
[23:54:05] [PASSED] drm_test_check_output_bpc_format_vic_1
[23:54:05] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[23:54:05] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[23:54:05] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[23:54:05] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[23:54:05] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[23:54:05] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[23:54:05] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[23:54:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[23:54:05] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[23:54:05] [PASSED] drm_test_check_broadcast_rgb_value
[23:54:05] [PASSED] drm_test_check_bpc_8_value
[23:54:05] [PASSED] drm_test_check_bpc_10_value
[23:54:05] [PASSED] drm_test_check_bpc_12_value
[23:54:05] [PASSED] drm_test_check_format_value
[23:54:05] [PASSED] drm_test_check_tmds_char_value
[23:54:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[23:54:05] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[23:54:05] [PASSED] drm_test_check_mode_valid
[23:54:05] [PASSED] drm_test_check_mode_valid_reject
[23:54:05] [PASSED] drm_test_check_mode_valid_reject_rate
[23:54:05] [PASSED] drm_test_check_mode_valid_reject_max_clock
[23:54:05] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[23:54:05] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[23:54:05] [PASSED] drm_test_check_infoframes
[23:54:05] [PASSED] drm_test_check_reject_avi_infoframe
[23:54:05] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[23:54:05] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[23:54:05] [PASSED] drm_test_check_reject_audio_infoframe
[23:54:05] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[23:54:05] ================= drm_managed (2 subtests) =================
[23:54:05] [PASSED] drm_test_managed_release_action
[23:54:05] [PASSED] drm_test_managed_run_action
[23:54:05] =================== [PASSED] drm_managed ===================
[23:54:05] =================== drm_mm (6 subtests) ====================
[23:54:05] [PASSED] drm_test_mm_init
[23:54:05] [PASSED] drm_test_mm_debug
[23:54:05] [PASSED] drm_test_mm_align32
[23:54:05] [PASSED] drm_test_mm_align64
[23:54:05] [PASSED] drm_test_mm_lowest
[23:54:05] [PASSED] drm_test_mm_highest
[23:54:05] ===================== [PASSED] drm_mm ======================
[23:54:05] ============= drm_modes_analog_tv (5 subtests) =============
[23:54:05] [PASSED] drm_test_modes_analog_tv_mono_576i
[23:54:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[23:54:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[23:54:05] [PASSED] drm_test_modes_analog_tv_pal_576i
[23:54:05] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[23:54:05] =============== [PASSED] drm_modes_analog_tv ===============
[23:54:05] ============== drm_plane_helper (2 subtests) ===============
[23:54:05] =============== drm_test_check_plane_state  ================
[23:54:05] [PASSED] clipping_simple
[23:54:05] [PASSED] clipping_rotate_reflect
[23:54:05] [PASSED] positioning_simple
[23:54:05] [PASSED] upscaling
[23:54:05] [PASSED] downscaling
[23:54:05] [PASSED] rounding1
[23:54:05] [PASSED] rounding2
[23:54:05] [PASSED] rounding3
[23:54:05] [PASSED] rounding4
[23:54:05] =========== [PASSED] drm_test_check_plane_state ============
[23:54:05] =========== drm_test_check_invalid_plane_state  ============
[23:54:05] [PASSED] positioning_invalid
[23:54:05] [PASSED] upscaling_invalid
[23:54:05] [PASSED] downscaling_invalid
[23:54:05] ======= [PASSED] drm_test_check_invalid_plane_state ========
[23:54:05] ================ [PASSED] drm_plane_helper =================
[23:54:05] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[23:54:05] ====== drm_test_connector_helper_tv_get_modes_check  =======
[23:54:05] [PASSED] None
[23:54:05] [PASSED] PAL
[23:54:05] [PASSED] NTSC
[23:54:05] [PASSED] Both, NTSC Default
[23:54:05] [PASSED] Both, PAL Default
[23:54:05] [PASSED] Both, NTSC Default, with PAL on command-line
[23:54:05] [PASSED] Both, PAL Default, with NTSC on command-line
[23:54:05] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[23:54:05] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[23:54:05] ================== drm_rect (9 subtests) ===================
[23:54:05] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[23:54:05] [PASSED] drm_test_rect_clip_scaled_not_clipped
[23:54:05] [PASSED] drm_test_rect_clip_scaled_clipped
[23:54:05] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[23:54:05] ================= drm_test_rect_intersect  =================
[23:54:05] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[23:54:05] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[23:54:05] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[23:54:05] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[23:54:05] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[23:54:05] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[23:54:05] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[23:54:05] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[23:54:05] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[23:54:05] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[23:54:05] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[23:54:05] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[23:54:05] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[23:54:05] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[23:54:05] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[23:54:05] ============= [PASSED] drm_test_rect_intersect =============
[23:54:05] ================ drm_test_rect_calc_hscale  ================
[23:54:05] [PASSED] normal use
[23:54:05] [PASSED] out of max range
[23:54:05] [PASSED] out of min range
[23:54:05] [PASSED] zero dst
[23:54:05] [PASSED] negative src
[23:54:05] [PASSED] negative dst
[23:54:05] ============ [PASSED] drm_test_rect_calc_hscale ============
[23:54:05] ================ drm_test_rect_calc_vscale  ================
[23:54:05] [PASSED] normal use
[23:54:05] [PASSED] out of max range
[23:54:05] [PASSED] out of min range
[23:54:05] [PASSED] zero dst
[23:54:05] [PASSED] negative src
[23:54:05] [PASSED] negative dst
[23:54:05] ============ [PASSED] drm_test_rect_calc_vscale ============
[23:54:05] ================== drm_test_rect_rotate  ===================
[23:54:05] [PASSED] reflect-x
[23:54:05] [PASSED] reflect-y
[23:54:05] [PASSED] rotate-0
[23:54:05] [PASSED] rotate-90
[23:54:05] [PASSED] rotate-180
[23:54:05] [PASSED] rotate-270
[23:54:05] ============== [PASSED] drm_test_rect_rotate ===============
[23:54:05] ================ drm_test_rect_rotate_inv  =================
[23:54:05] [PASSED] reflect-x
[23:54:05] [PASSED] reflect-y
[23:54:05] [PASSED] rotate-0
[23:54:05] [PASSED] rotate-90
[23:54:05] [PASSED] rotate-180
[23:54:05] [PASSED] rotate-270
[23:54:05] ============ [PASSED] drm_test_rect_rotate_inv =============
[23:54:05] ==================== [PASSED] drm_rect =====================
[23:54:05] ============ drm_sysfb_modeset_test (1 subtest) ============
[23:54:05] ============ drm_test_sysfb_build_fourcc_list  =============
[23:54:05] [PASSED] no native formats
[23:54:05] [PASSED] XRGB8888 as native format
[23:54:05] [PASSED] remove duplicates
[23:54:05] [PASSED] convert alpha formats
[23:54:05] [PASSED] random formats
[23:54:05] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[23:54:05] ============= [PASSED] drm_sysfb_modeset_test ==============
[23:54:05] ================== drm_fixp (2 subtests) ===================
[23:54:05] [PASSED] drm_test_int2fixp
[23:54:05] [PASSED] drm_test_sm2fixp
[23:54:05] ==================== [PASSED] drm_fixp =====================
[23:54:05] ============================================================
[23:54:05] Testing complete. Ran 621 tests: passed: 621
[23:54:05] Elapsed time: 26.309s total, 1.770s configuring, 24.409s building, 0.130s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[23:54:05] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[23:54:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[23:54:16] Starting KUnit Kernel (1/1)...
[23:54:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[23:54:16] ================= ttm_device (5 subtests) ==================
[23:54:16] [PASSED] ttm_device_init_basic
[23:54:16] [PASSED] ttm_device_init_multiple
[23:54:16] [PASSED] ttm_device_fini_basic
[23:54:16] [PASSED] ttm_device_init_no_vma_man
[23:54:16] ================== ttm_device_init_pools  ==================
[23:54:16] [PASSED] No DMA allocations, no DMA32 required
[23:54:16] [PASSED] DMA allocations, DMA32 required
[23:54:16] [PASSED] No DMA allocations, DMA32 required
[23:54:16] [PASSED] DMA allocations, no DMA32 required
[23:54:16] ============== [PASSED] ttm_device_init_pools ==============
[23:54:16] =================== [PASSED] ttm_device ====================
[23:54:16] ================== ttm_pool (8 subtests) ===================
[23:54:16] ================== ttm_pool_alloc_basic  ===================
[23:54:16] [PASSED] One page
[23:54:16] [PASSED] More than one page
[23:54:16] [PASSED] Above the allocation limit
[23:54:16] [PASSED] One page, with coherent DMA mappings enabled
[23:54:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:54:16] ============== [PASSED] ttm_pool_alloc_basic ===============
[23:54:16] ============== ttm_pool_alloc_basic_dma_addr  ==============
[23:54:16] [PASSED] One page
[23:54:16] [PASSED] More than one page
[23:54:16] [PASSED] Above the allocation limit
[23:54:16] [PASSED] One page, with coherent DMA mappings enabled
[23:54:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[23:54:16] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[23:54:16] [PASSED] ttm_pool_alloc_order_caching_match
[23:54:16] [PASSED] ttm_pool_alloc_caching_mismatch
[23:54:16] [PASSED] ttm_pool_alloc_order_mismatch
[23:54:16] [PASSED] ttm_pool_free_dma_alloc
[23:54:16] [PASSED] ttm_pool_free_no_dma_alloc
[23:54:16] [PASSED] ttm_pool_fini_basic
[23:54:16] ==================== [PASSED] ttm_pool =====================
[23:54:16] ================ ttm_resource (8 subtests) =================
[23:54:16] ================= ttm_resource_init_basic  =================
[23:54:16] [PASSED] Init resource in TTM_PL_SYSTEM
[23:54:16] [PASSED] Init resource in TTM_PL_VRAM
[23:54:16] [PASSED] Init resource in a private placement
[23:54:16] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[23:54:16] ============= [PASSED] ttm_resource_init_basic =============
[23:54:16] [PASSED] ttm_resource_init_pinned
[23:54:16] [PASSED] ttm_resource_fini_basic
[23:54:16] [PASSED] ttm_resource_manager_init_basic
[23:54:16] [PASSED] ttm_resource_manager_usage_basic
[23:54:16] [PASSED] ttm_resource_manager_set_used_basic
[23:54:16] [PASSED] ttm_sys_man_alloc_basic
[23:54:16] [PASSED] ttm_sys_man_free_basic
[23:54:16] ================== [PASSED] ttm_resource ===================
[23:54:16] =================== ttm_tt (15 subtests) ===================
[23:54:16] ==================== ttm_tt_init_basic  ====================
[23:54:16] [PASSED] Page-aligned size
[23:54:16] [PASSED] Extra pages requested
[23:54:16] ================ [PASSED] ttm_tt_init_basic ================
[23:54:16] [PASSED] ttm_tt_init_misaligned
[23:54:16] [PASSED] ttm_tt_fini_basic
[23:54:16] [PASSED] ttm_tt_fini_sg
[23:54:16] [PASSED] ttm_tt_fini_shmem
[23:54:16] [PASSED] ttm_tt_create_basic
[23:54:16] [PASSED] ttm_tt_create_invalid_bo_type
[23:54:16] [PASSED] ttm_tt_create_ttm_exists
[23:54:16] [PASSED] ttm_tt_create_failed
[23:54:16] [PASSED] ttm_tt_destroy_basic
[23:54:16] [PASSED] ttm_tt_populate_null_ttm
[23:54:16] [PASSED] ttm_tt_populate_populated_ttm
[23:54:16] [PASSED] ttm_tt_unpopulate_basic
[23:54:16] [PASSED] ttm_tt_unpopulate_empty_ttm
[23:54:16] [PASSED] ttm_tt_swapin_basic
[23:54:16] ===================== [PASSED] ttm_tt ======================
[23:54:16] =================== ttm_bo (14 subtests) ===================
[23:54:16] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[23:54:16] [PASSED] Cannot be interrupted and sleeps
[23:54:16] [PASSED] Cannot be interrupted, locks straight away
[23:54:16] [PASSED] Can be interrupted, sleeps
[23:54:16] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[23:54:16] [PASSED] ttm_bo_reserve_locked_no_sleep
[23:54:16] [PASSED] ttm_bo_reserve_no_wait_ticket
[23:54:16] [PASSED] ttm_bo_reserve_double_resv
[23:54:16] [PASSED] ttm_bo_reserve_interrupted
[23:54:16] [PASSED] ttm_bo_reserve_deadlock
[23:54:16] [PASSED] ttm_bo_unreserve_basic
[23:54:16] [PASSED] ttm_bo_unreserve_pinned
[23:54:16] [PASSED] ttm_bo_unreserve_bulk
[23:54:16] [PASSED] ttm_bo_fini_basic
[23:54:16] [PASSED] ttm_bo_fini_shared_resv
[23:54:16] [PASSED] ttm_bo_pin_basic
[23:54:16] [PASSED] ttm_bo_pin_unpin_resource
[23:54:16] [PASSED] ttm_bo_multiple_pin_one_unpin
[23:54:16] ===================== [PASSED] ttm_bo ======================
[23:54:16] ============== ttm_bo_validate (22 subtests) ===============
[23:54:16] ============== ttm_bo_init_reserved_sys_man  ===============
[23:54:16] [PASSED] Buffer object for userspace
[23:54:16] [PASSED] Kernel buffer object
[23:54:16] [PASSED] Shared buffer object
[23:54:16] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[23:54:16] ============== ttm_bo_init_reserved_mock_man  ==============
[23:54:16] [PASSED] Buffer object for userspace
[23:54:16] [PASSED] Kernel buffer object
[23:54:16] [PASSED] Shared buffer object
[23:54:16] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[23:54:16] [PASSED] ttm_bo_init_reserved_resv
[23:54:16] ================== ttm_bo_validate_basic  ==================
[23:54:16] [PASSED] Buffer object for userspace
[23:54:16] [PASSED] Kernel buffer object
[23:54:16] [PASSED] Shared buffer object
[23:54:16] ============== [PASSED] ttm_bo_validate_basic ==============
[23:54:16] [PASSED] ttm_bo_validate_invalid_placement
[23:54:16] ============= ttm_bo_validate_same_placement  ==============
[23:54:16] [PASSED] System manager
[23:54:16] [PASSED] VRAM manager
[23:54:16] ========= [PASSED] ttm_bo_validate_same_placement ==========
[23:54:16] [PASSED] ttm_bo_validate_failed_alloc
[23:54:16] [PASSED] ttm_bo_validate_pinned
[23:54:16] [PASSED] ttm_bo_validate_busy_placement
[23:54:16] ================ ttm_bo_validate_multihop  =================
[23:54:16] [PASSED] Buffer object for userspace
[23:54:16] [PASSED] Kernel buffer object
[23:54:16] [PASSED] Shared buffer object
[23:54:16] ============ [PASSED] ttm_bo_validate_multihop =============
[23:54:16] ========== ttm_bo_validate_no_placement_signaled  ==========
[23:54:16] [PASSED] Buffer object in system domain, no page vector
[23:54:16] [PASSED] Buffer object in system domain with an existing page vector
[23:54:16] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[23:54:16] ======== ttm_bo_validate_no_placement_not_signaled  ========
[23:54:16] [PASSED] Buffer object for userspace
[23:54:16] [PASSED] Kernel buffer object
[23:54:16] [PASSED] Shared buffer object
[23:54:16] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[23:54:16] [PASSED] ttm_bo_validate_move_fence_signaled
[23:54:16] ========= ttm_bo_validate_move_fence_not_signaled  =========
[23:54:16] [PASSED] Waits for GPU
[23:54:16] [PASSED] Tries to lock straight away
[23:54:16] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[23:54:16] [PASSED] ttm_bo_validate_swapout
[23:54:16] [PASSED] ttm_bo_validate_happy_evict
[23:54:16] [PASSED] ttm_bo_validate_all_pinned_evict
[23:54:16] [PASSED] ttm_bo_validate_allowed_only_evict
[23:54:16] [PASSED] ttm_bo_validate_deleted_evict
[23:54:16] [PASSED] ttm_bo_validate_busy_domain_evict
[23:54:16] [PASSED] ttm_bo_validate_evict_gutting
[23:54:16] [PASSED] ttm_bo_validate_recrusive_evict
[23:54:16] ================= [PASSED] ttm_bo_validate =================
[23:54:16] ============================================================
[23:54:16] Testing complete. Ran 102 tests: passed: 102
[23:54:16] Elapsed time: 11.600s total, 1.744s configuring, 9.641s building, 0.180s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Don't whitelist OA registers unconditionally

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 867 bytes --]

== Series Details ==

Series: Don't whitelist OA registers unconditionally
URL   : https://patchwork.freedesktop.org/series/166809/
State : success

== Summary ==

CI Bug Log - changes from xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8_BAT -> xe-pw-166809v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8 -> xe-pw-166809v1

  IGT_8918: 8918
  xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8: 94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8
  xe-pw-166809v1: 166809v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/index.html

[-- Attachment #2: Type: text/html, Size: 1420 bytes --]

✗ Xe.CI.FULL: failure for Don't whitelist OA registers unconditionally

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 20438 bytes --]

== Series Details ==

Series: Don't whitelist OA registers unconditionally
URL   : https://patchwork.freedesktop.org/series/166809/
State : failure

== Summary ==

CI Bug Log - changes from xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8_FULL -> xe-pw-166809v1_FULL
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with xe-pw-166809v1_FULL need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-166809v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-166809v1_FULL:

### IGT changes ###

#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-spr-indfb-draw-render:
    - shard-lnl:          [SKIP][1] ([Intel XE#7905]) -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-spr-indfb-draw-render.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-spr-indfb-draw-render.html

  
Known issues
------------

  Here are the changes found in xe-pw-166809v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2327]) +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#7059] / [Intel XE#7085])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#607] / [Intel XE#7361])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#1124])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-90.html

  * igt@kms_bw@linear-tiling-2-displays-target-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#367])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_bw@linear-tiling-2-displays-target-1920x1080p.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2652]) +8 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2887]) +2 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2252]) +2 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][11] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-random-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2320])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_cursor_crc@cursor-random-64x21.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][13] -> [FAIL][14] ([Intel XE#7571])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#6126] / [Intel XE#776])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ad-dp2-hdmi-a3:
    - shard-bmg:          [PASS][16] -> [FAIL][17] ([Intel XE#3321]) +1 other test fail
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank@ad-dp2-hdmi-a3.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ad-dp2-hdmi-a3.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#7178] / [Intel XE#7351])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#7179])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#4141]) +3 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2311]) +10 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-argb161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7061]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrshdr-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2313]) +11 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [PASS][24] -> [SKIP][25] ([Intel XE#7915]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-9/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-1/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#6911] / [Intel XE#7466])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_plane@pixel-format-yf-tiled-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7283])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#1489]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr@psr-no-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@kms_psr@psr-no-drrs.html

  * igt@kms_vblank@wait-busy-hang:
    - shard-bmg:          [PASS][30] -> [INCOMPLETE][31] ([Intel XE#1727] / [Intel XE#6819]) +1 other test incomplete
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-5/igt@kms_vblank@wait-busy-hang.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-2/igt@kms_vblank@wait-busy-hang.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][32] -> [FAIL][33] ([Intel XE#2142]) +1 other test fail
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-lnl-1/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_eudebug@basic-vm-access:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#7636]) +3 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@xe_eudebug@basic-vm-access.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][35] -> [INCOMPLETE][36] ([Intel XE#6321])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-1/igt@xe_evict@evict-mixed-many-threads-small.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_evict@evict-small-external-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#7140])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@xe_evict@evict-small-external-multi-queue.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2322] / [Intel XE#7372])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-bind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-imm:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#7136]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@xe_exec_fault_mode@many-execqueues-multi-queue-imm.html

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-dyn-priority:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#6874]) +5 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@xe_exec_multi_queue@max-queues-preempt-mode-dyn-priority.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#7138]) +2 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@xe_exec_threads@threads-multi-queue-mixed-userptr.html

  * igt@xe_multigpu_svm@mgpu-concurrent-access-basic:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#6964])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@xe_multigpu_svm@mgpu-concurrent-access-basic.html

  * igt@xe_non_msix@walker-interrupt-notification-non-msix:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#7622])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@xe_non_msix@walker-interrupt-notification-non-msix.html

  * igt@xe_pm@d3cold-i2c:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#5694] / [Intel XE#7370])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2284] / [Intel XE#7370])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-7/igt@xe_pm@s2idle-d3cold-basic-exec.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2:
    - shard-bmg:          [FAIL][46] -> [PASS][47] +1 other test pass
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-5/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-4/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp2:
    - shard-bmg:          [FAIL][48] ([Intel XE#3321]) -> [PASS][49] +1 other test pass
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-10/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp2.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp2.html

  * igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [SKIP][50] ([Intel XE#7915]) -> [PASS][51] +1 other test pass
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-8/igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-6/igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][52] ([Intel XE#6321]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-3/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-3/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  
#### Warnings ####

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][54] ([Intel XE#3544] / [Intel XE#7915] / [Intel XE#7916]) -> [SKIP][55] ([Intel XE#3544] / [Intel XE#7916])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-10/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [SKIP][56] ([Intel XE#7915]) -> [SKIP][57] ([Intel XE#7916]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-1/igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-3-xrgb16161616f.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-10/igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][58] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][59] ([Intel XE#2426] / [Intel XE#5848])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#6126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6126
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6819
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7622]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7622
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
  [Intel XE#7916]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7916


Build changes
-------------

  * Linux: xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8 -> xe-pw-166809v1

  IGT_8918: 8918
  xe-5087-94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8: 94e4b8dc66d191ccb11a59ae2c065b5b6f3565d8
  xe-pw-166809v1: 166809v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166809v1/index.html

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Re: [PATCH 0/9] Don't whitelist OA registers unconditionally

[Demi Marie Obenour]

[-- Attachment #1.1.1: Type: text/plain, Size: 1819 bytes --]

On 5/18/26 19:47, Ashutosh Dixit wrote:
> Whitelisting OA registers unconditionally is a security violation. In this
> series we resolve this issue as follows:
> 
> * Set the 'deny' bit (bit 30) for all OA registers, ensuring OA registers
>   are not whitelisted by default after probe/reset/restart
> * Reset the 'deny' bit when an OA stream is opened and certain conditions
>   are met, whitelisting OA registers only for the duration when OA streams
>   are open for a gt
> * Set the 'deny' bit again, when OA streams are closed
> * To manage this scheme, separate out OA whitelists from non-OA whitelists
>   (into separate save-restore lists)
> 
> Ashutosh Dixit (9):
>   drm/xe/rtp: Add RING_FORCE_TO_NONPRIV_DENY to OA whitelists
>   drm/xe/rtp: Maintain OA whitelists separately
>   drm/xe/rtp: Keep track of non-OA nonpriv slots
>   drm/xe/rtp: Generalize whitelist_apply_to_hwe
>   drm/xe/rtp: Save OA nonpriv registers to register save/restore lists
>   drm/xe/rtp: Toggle 'deny' bit to (de-)whitelist OA regs
>   drm/xe/rtp: (De-)whitelist OA registers for all hwe's for a gt
>   drm/xe/oa: (De-)whitelist OA registers on OA stream open/release
>   drm/xe/rtp: Ensure locking/ref counting for OA whitelists
> 
>  drivers/gpu/drm/xe/xe_gt_debugfs.c      |  4 +-
>  drivers/gpu/drm/xe/xe_hw_engine.c       |  2 +
>  drivers/gpu/drm/xe/xe_hw_engine_types.h |  8 +++
>  drivers/gpu/drm/xe/xe_oa.c              |  7 ++
>  drivers/gpu/drm/xe/xe_oa_types.h        |  3 +
>  drivers/gpu/drm/xe/xe_reg_whitelist.c   | 92 ++++++++++++++++++++++---
>  drivers/gpu/drm/xe/xe_reg_whitelist.h   |  4 ++
>  7 files changed, 111 insertions(+), 9 deletions(-)
> 

Does this (and any other potential security issues) need to be Cc: stable?
-- 
Sincerely,
Demi Marie Obenour (she/her/hers)

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