[Intel-gfx] [PATCH 1/6] drm/i915: Skip capturing errors from internal contexts

[Intel-gfx] [PATCH 1/6] drm/i915: Skip capturing errors from internal contexts

[Chris Wilson]

We don't want to report errors on the internal contexts to userspace,
suppressing their own, so treat them as simulated errors. These mostly
arise inside selftests and so are simulated anyway. For the rest, we can
rely on the normal debug channels in CI.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 594341e27a47..0f67bef83106 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1228,7 +1228,7 @@ static bool record_context(struct i915_gem_context_coredump *e,
 {
 	struct i915_gem_context *ctx;
 	struct task_struct *task;
-	bool capture;
+	bool simulated;
 
 	rcu_read_lock();
 	ctx = rcu_dereference(rq->context->gem_context);
@@ -1236,7 +1236,7 @@ static bool record_context(struct i915_gem_context_coredump *e,
 		ctx = NULL;
 	rcu_read_unlock();
 	if (!ctx)
-		return false;
+		return true;
 
 	rcu_read_lock();
 	task = pid_task(ctx->pid, PIDTYPE_PID);
@@ -1250,10 +1250,10 @@ static bool record_context(struct i915_gem_context_coredump *e,
 	e->guilty = atomic_read(&ctx->guilty_count);
 	e->active = atomic_read(&ctx->active_count);
 
-	capture = i915_gem_context_no_error_capture(ctx);
+	simulated = i915_gem_context_no_error_capture(ctx);
 
 	i915_gem_context_put(ctx);
-	return capture;
+	return simulated;
 }
 
 struct intel_engine_capture_vma {
-- 
2.25.0

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[Intel-gfx] [PATCH 2/6] drm/i915/gt: Reorganise gen8+ interrupt handler

[Chris Wilson]

We always use a deferred bottom-half (either tasklet or irq_work) for
processing the response to an interrupt which means we can recombine the
GT irq ack+handler into one. This simplicity is important in later
patches as we will need to handle and then ack multiple interrupt levels
before acking the GT and master interrupts.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_gt_irq.c | 70 +++++++++++---------------
 drivers/gpu/drm/i915/gt/intel_gt_irq.h |  3 +-
 drivers/gpu/drm/i915/i915_irq.c        | 10 +---
 3 files changed, 33 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f796bdf1ed30..71873a4cafc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -286,59 +286,49 @@ void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
 		gen7_parity_error_irq_handler(gt, gt_iir);
 }
 
-void gen8_gt_irq_ack(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
+void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
 {
 	void __iomem * const regs = gt->uncore->regs;
+	u32 iir;
 
 	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
-		gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
-		if (likely(gt_iir[0]))
-			raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
-	}
-
-	if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
-		gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
-		if (likely(gt_iir[1]))
-			raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
-	}
-
-	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
-		gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
-		if (likely(gt_iir[2]))
-			raw_reg_write(regs, GEN8_GT_IIR(2), gt_iir[2]);
-	}
-
-	if (master_ctl & GEN8_GT_VECS_IRQ) {
-		gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
-		if (likely(gt_iir[3]))
-			raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
-	}
-}
-
-void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
-{
-	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
-		cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
-			       gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
-		cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
-			       gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
+		iir = raw_reg_read(regs, GEN8_GT_IIR(0));
+		if (likely(iir)) {
+			cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
+				       iir >> GEN8_RCS_IRQ_SHIFT);
+			cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
+				       iir >> GEN8_BCS_IRQ_SHIFT);
+			raw_reg_write(regs, GEN8_GT_IIR(0), iir);
+		}
 	}
 
 	if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
-		cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0],
-			       gt_iir[1] >> GEN8_VCS0_IRQ_SHIFT);
-		cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1],
-			       gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
+		iir = raw_reg_read(regs, GEN8_GT_IIR(1));
+		if (likely(iir)) {
+			cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0],
+				       iir >> GEN8_VCS0_IRQ_SHIFT);
+			cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1],
+				       iir >> GEN8_VCS1_IRQ_SHIFT);
+			raw_reg_write(regs, GEN8_GT_IIR(1), iir);
+		}
 	}
 
 	if (master_ctl & GEN8_GT_VECS_IRQ) {
-		cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
-			       gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
+		iir = raw_reg_read(regs, GEN8_GT_IIR(3));
+		if (likely(iir)) {
+			cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
+				       iir >> GEN8_VECS_IRQ_SHIFT);
+			raw_reg_write(regs, GEN8_GT_IIR(3), iir);
+		}
 	}
 
 	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
-		gen6_rps_irq_handler(&gt->rps, gt_iir[2]);
-		guc_irq_handler(&gt->uc.guc, gt_iir[2] >> 16);
+		iir = raw_reg_read(regs, GEN8_GT_IIR(2));
+		if (likely(iir)) {
+			gen6_rps_irq_handler(&gt->rps, iir);
+			guc_irq_handler(&gt->uc.guc, iir >> 16);
+			raw_reg_write(regs, GEN8_GT_IIR(2), iir);
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
index 8f37593712c9..886c5cf408a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
@@ -36,9 +36,8 @@ void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask);
 
 void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
 
-void gen8_gt_irq_ack(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4]);
+void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl);
 void gen8_gt_irq_reset(struct intel_gt *gt);
-void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4]);
 void gen8_gt_irq_postinstall(struct intel_gt *gt);
 
 #endif /* INTEL_GT_IRQ_H */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 87a6662abc1b..e40dd226fde8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1614,7 +1614,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		u32 master_ctl, iir;
 		u32 pipe_stats[I915_MAX_PIPES] = {};
 		u32 hotplug_status = 0;
-		u32 gt_iir[4];
 		u32 ier = 0;
 
 		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
@@ -1642,7 +1641,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		ier = I915_READ(VLV_IER);
 		I915_WRITE(VLV_IER, 0);
 
-		gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir);
+		gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
 
 		if (iir & I915_DISPLAY_PORT_INTERRUPT)
 			hotplug_status = i9xx_hpd_irq_ack(dev_priv);
@@ -1666,8 +1665,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
 		I915_WRITE(VLV_IER, ier);
 		I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
 
-		gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
-
 		if (hotplug_status)
 			i9xx_hpd_irq_handler(dev_priv, hotplug_status);
 
@@ -2396,7 +2393,6 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	struct drm_i915_private *dev_priv = arg;
 	void __iomem * const regs = dev_priv->uncore.regs;
 	u32 master_ctl;
-	u32 gt_iir[4];
 
 	if (!intel_irqs_enabled(dev_priv))
 		return IRQ_NONE;
@@ -2408,7 +2404,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	}
 
 	/* Find, clear, then process each source of interrupt */
-	gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir);
+	gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
 
 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
 	if (master_ctl & ~GEN8_GT_IRQS) {
@@ -2419,8 +2415,6 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 
 	gen8_master_intr_enable(regs);
 
-	gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
-
 	return IRQ_HANDLED;
 }
 
-- 
2.25.0

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Re: [Intel-gfx] [PATCH 2/6] drm/i915/gt: Reorganise gen8+ interrupt handler

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> We always use a deferred bottom-half (either tasklet or irq_work) for
> processing the response to an interrupt which means we can recombine the
> GT irq ack+handler into one. This simplicity is important in later
> patches as we will need to handle and then ack multiple interrupt levels
> before acking the GT and master interrupts.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_irq.c | 70 +++++++++++---------------
>  drivers/gpu/drm/i915/gt/intel_gt_irq.h |  3 +-
>  drivers/gpu/drm/i915/i915_irq.c        | 10 +---
>  3 files changed, 33 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index f796bdf1ed30..71873a4cafc0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -286,59 +286,49 @@ void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
>  		gen7_parity_error_irq_handler(gt, gt_iir);
>  }
>  
> -void gen8_gt_irq_ack(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
> +void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
>  {
>  	void __iomem * const regs = gt->uncore->regs;
> +	u32 iir;
>  
>  	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> -		gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
> -		if (likely(gt_iir[0]))
> -			raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
> -	}
> -
> -	if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
> -		gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
> -		if (likely(gt_iir[1]))
> -			raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
> -	}
> -
> -	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> -		gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
> -		if (likely(gt_iir[2]))
> -			raw_reg_write(regs, GEN8_GT_IIR(2), gt_iir[2]);
> -	}
> -
> -	if (master_ctl & GEN8_GT_VECS_IRQ) {
> -		gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
> -		if (likely(gt_iir[3]))
> -			raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
> -	}
> -}
> -
> -void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
> -{
> -	if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> -		cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
> -			       gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
> -		cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
> -			       gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
> +		iir = raw_reg_read(regs, GEN8_GT_IIR(0));
> +		if (likely(iir)) {
> +			cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
> +				       iir >> GEN8_RCS_IRQ_SHIFT);
> +			cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
> +				       iir >> GEN8_BCS_IRQ_SHIFT);
> +			raw_reg_write(regs, GEN8_GT_IIR(0), iir);
> +		}
>  	}
>  
>  	if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
> -		cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0],
> -			       gt_iir[1] >> GEN8_VCS0_IRQ_SHIFT);
> -		cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1],
> -			       gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
> +		iir = raw_reg_read(regs, GEN8_GT_IIR(1));
> +		if (likely(iir)) {
> +			cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0],
> +				       iir >> GEN8_VCS0_IRQ_SHIFT);
> +			cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1],
> +				       iir >> GEN8_VCS1_IRQ_SHIFT);
> +			raw_reg_write(regs, GEN8_GT_IIR(1), iir);
> +		}
>  	}
>  
>  	if (master_ctl & GEN8_GT_VECS_IRQ) {
> -		cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
> -			       gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
> +		iir = raw_reg_read(regs, GEN8_GT_IIR(3));
> +		if (likely(iir)) {
> +			cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
> +				       iir >> GEN8_VECS_IRQ_SHIFT);
> +			raw_reg_write(regs, GEN8_GT_IIR(3), iir);
> +		}
>  	}
>  
>  	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> -		gen6_rps_irq_handler(&gt->rps, gt_iir[2]);
> -		guc_irq_handler(&gt->uc.guc, gt_iir[2] >> 16);
> +		iir = raw_reg_read(regs, GEN8_GT_IIR(2));
> +		if (likely(iir)) {
> +			gen6_rps_irq_handler(&gt->rps, iir);
> +			guc_irq_handler(&gt->uc.guc, iir >> 16);
> +			raw_reg_write(regs, GEN8_GT_IIR(2), iir);
> +		}
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> index 8f37593712c9..886c5cf408a2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> @@ -36,9 +36,8 @@ void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask);
>  
>  void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
>  
> -void gen8_gt_irq_ack(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4]);
> +void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl);
>  void gen8_gt_irq_reset(struct intel_gt *gt);
> -void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4]);
>  void gen8_gt_irq_postinstall(struct intel_gt *gt);
>  
>  #endif /* INTEL_GT_IRQ_H */
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 87a6662abc1b..e40dd226fde8 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1614,7 +1614,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  		u32 master_ctl, iir;
>  		u32 pipe_stats[I915_MAX_PIPES] = {};
>  		u32 hotplug_status = 0;
> -		u32 gt_iir[4];
>  		u32 ier = 0;
>  
>  		master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
> @@ -1642,7 +1641,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  		ier = I915_READ(VLV_IER);
>  		I915_WRITE(VLV_IER, 0);
>  
> -		gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir);
> +		gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
>  
>  		if (iir & I915_DISPLAY_PORT_INTERRUPT)
>  			hotplug_status = i9xx_hpd_irq_ack(dev_priv);
> @@ -1666,8 +1665,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>  		I915_WRITE(VLV_IER, ier);
>  		I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
>  
> -		gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
> -
>  		if (hotplug_status)
>  			i9xx_hpd_irq_handler(dev_priv, hotplug_status);
>  
> @@ -2396,7 +2393,6 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  	struct drm_i915_private *dev_priv = arg;
>  	void __iomem * const regs = dev_priv->uncore.regs;
>  	u32 master_ctl;
> -	u32 gt_iir[4];
>  
>  	if (!intel_irqs_enabled(dev_priv))
>  		return IRQ_NONE;
> @@ -2408,7 +2404,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  	}
>  
>  	/* Find, clear, then process each source of interrupt */

/* Find, process and then clear each source of interrupt */

or with removal of the comment,
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> -	gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir);
> +	gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
>  
>  	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
>  	if (master_ctl & ~GEN8_GT_IRQS) {
> @@ -2419,8 +2415,6 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>  
>  	gen8_master_intr_enable(regs);
>  
> -	gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
> -
>  	return IRQ_HANDLED;
>  }
>  
> -- 
> 2.25.0
>
> _______________________________________________
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 2/6] drm/i915/gt: Reorganise gen8+ interrupt handler

[Chris Wilson]

Quoting Mika Kuoppala (2020-01-28 12:20:46)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > We always use a deferred bottom-half (either tasklet or irq_work) for
> > processing the response to an interrupt which means we can recombine the
> > GT irq ack+handler into one. This simplicity is important in later
> > patches as we will need to handle and then ack multiple interrupt levels
> > before acking the GT and master interrupts.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gt_irq.c | 70 +++++++++++---------------
> >  drivers/gpu/drm/i915/gt/intel_gt_irq.h |  3 +-
> >  drivers/gpu/drm/i915/i915_irq.c        | 10 +---
> >  3 files changed, 33 insertions(+), 50 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > index f796bdf1ed30..71873a4cafc0 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > @@ -286,59 +286,49 @@ void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
> >               gen7_parity_error_irq_handler(gt, gt_iir);
> >  }
> >  
> > -void gen8_gt_irq_ack(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
> > +void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
> >  {
> >       void __iomem * const regs = gt->uncore->regs;
> > +     u32 iir;
> >  
> >       if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> > -             gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
> > -             if (likely(gt_iir[0]))
> > -                     raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
> > -     }
> > -
> > -     if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
> > -             gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
> > -             if (likely(gt_iir[1]))
> > -                     raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
> > -     }
> > -
> > -     if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> > -             gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
> > -             if (likely(gt_iir[2]))
> > -                     raw_reg_write(regs, GEN8_GT_IIR(2), gt_iir[2]);
> > -     }
> > -
> > -     if (master_ctl & GEN8_GT_VECS_IRQ) {
> > -             gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
> > -             if (likely(gt_iir[3]))
> > -                     raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
> > -     }
> > -}
> > -
> > -void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
> > -{
> > -     if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
> > -             cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
> > -                            gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
> > -             cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
> > -                            gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
> > +             iir = raw_reg_read(regs, GEN8_GT_IIR(0));
> > +             if (likely(iir)) {
> > +                     cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
> > +                                    iir >> GEN8_RCS_IRQ_SHIFT);
> > +                     cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
> > +                                    iir >> GEN8_BCS_IRQ_SHIFT);
> > +                     raw_reg_write(regs, GEN8_GT_IIR(0), iir);
> > +             }
> >       }
> >  
> >       if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
> > -             cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0],
> > -                            gt_iir[1] >> GEN8_VCS0_IRQ_SHIFT);
> > -             cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1],
> > -                            gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
> > +             iir = raw_reg_read(regs, GEN8_GT_IIR(1));
> > +             if (likely(iir)) {
> > +                     cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0],
> > +                                    iir >> GEN8_VCS0_IRQ_SHIFT);
> > +                     cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1],
> > +                                    iir >> GEN8_VCS1_IRQ_SHIFT);
> > +                     raw_reg_write(regs, GEN8_GT_IIR(1), iir);
> > +             }
> >       }
> >  
> >       if (master_ctl & GEN8_GT_VECS_IRQ) {
> > -             cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
> > -                            gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
> > +             iir = raw_reg_read(regs, GEN8_GT_IIR(3));
> > +             if (likely(iir)) {
> > +                     cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
> > +                                    iir >> GEN8_VECS_IRQ_SHIFT);
> > +                     raw_reg_write(regs, GEN8_GT_IIR(3), iir);
> > +             }
> >       }
> >  
> >       if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> > -             gen6_rps_irq_handler(&gt->rps, gt_iir[2]);
> > -             guc_irq_handler(&gt->uc.guc, gt_iir[2] >> 16);
> > +             iir = raw_reg_read(regs, GEN8_GT_IIR(2));
> > +             if (likely(iir)) {
> > +                     gen6_rps_irq_handler(&gt->rps, iir);
> > +                     guc_irq_handler(&gt->uc.guc, iir >> 16);
> > +                     raw_reg_write(regs, GEN8_GT_IIR(2), iir);
> > +             }
> >       }
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> > index 8f37593712c9..886c5cf408a2 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
> > @@ -36,9 +36,8 @@ void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask);
> >  
> >  void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
> >  
> > -void gen8_gt_irq_ack(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4]);
> > +void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl);
> >  void gen8_gt_irq_reset(struct intel_gt *gt);
> > -void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4]);
> >  void gen8_gt_irq_postinstall(struct intel_gt *gt);
> >  
> >  #endif /* INTEL_GT_IRQ_H */
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 87a6662abc1b..e40dd226fde8 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -1614,7 +1614,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> >               u32 master_ctl, iir;
> >               u32 pipe_stats[I915_MAX_PIPES] = {};
> >               u32 hotplug_status = 0;
> > -             u32 gt_iir[4];
> >               u32 ier = 0;
> >  
> >               master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
> > @@ -1642,7 +1641,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> >               ier = I915_READ(VLV_IER);
> >               I915_WRITE(VLV_IER, 0);
> >  
> > -             gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir);
> > +             gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
> >  
> >               if (iir & I915_DISPLAY_PORT_INTERRUPT)
> >                       hotplug_status = i9xx_hpd_irq_ack(dev_priv);
> > @@ -1666,8 +1665,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> >               I915_WRITE(VLV_IER, ier);
> >               I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> >  
> > -             gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
> > -
> >               if (hotplug_status)
> >                       i9xx_hpd_irq_handler(dev_priv, hotplug_status);
> >  
> > @@ -2396,7 +2393,6 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
> >       struct drm_i915_private *dev_priv = arg;
> >       void __iomem * const regs = dev_priv->uncore.regs;
> >       u32 master_ctl;
> > -     u32 gt_iir[4];
> >  
> >       if (!intel_irqs_enabled(dev_priv))
> >               return IRQ_NONE;
> > @@ -2408,7 +2404,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
> >       }
> >  
> >       /* Find, clear, then process each source of interrupt */
> 
> /* Find, process and then clear each source of interrupt */

The order is still ack / process, and that is quite important for
allowing interrupt delivery as we process. It's just that we use
bottom-halves rather than a local deferral.

	/* Find, clear, then process (via bottom-halves) each source of interrupt */
-Chris
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Re: [Intel-gfx] [PATCH 2/6] drm/i915/gt: Reorganise gen8+ interrupt handler

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Mika Kuoppala (2020-01-28 12:20:46)
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>> 
>> > We always use a deferred bottom-half (either tasklet or irq_work) for
>> > processing the response to an interrupt which means we can recombine the
>> > GT irq ack+handler into one. This simplicity is important in later
>> > patches as we will need to handle and then ack multiple interrupt levels
>> > before acking the GT and master interrupts.
>> >
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> > ---
>> >  drivers/gpu/drm/i915/gt/intel_gt_irq.c | 70 +++++++++++---------------
>> >  drivers/gpu/drm/i915/gt/intel_gt_irq.h |  3 +-
>> >  drivers/gpu/drm/i915/i915_irq.c        | 10 +---
>> >  3 files changed, 33 insertions(+), 50 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > index f796bdf1ed30..71873a4cafc0 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > @@ -286,59 +286,49 @@ void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
>> >               gen7_parity_error_irq_handler(gt, gt_iir);
>> >  }
>> >  
>> > -void gen8_gt_irq_ack(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
>> > +void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
>> >  {
>> >       void __iomem * const regs = gt->uncore->regs;
>> > +     u32 iir;
>> >  
>> >       if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
>> > -             gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
>> > -             if (likely(gt_iir[0]))
>> > -                     raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
>> > -     }
>> > -
>> > -     if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
>> > -             gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
>> > -             if (likely(gt_iir[1]))
>> > -                     raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
>> > -     }
>> > -
>> > -     if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
>> > -             gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
>> > -             if (likely(gt_iir[2]))
>> > -                     raw_reg_write(regs, GEN8_GT_IIR(2), gt_iir[2]);
>> > -     }
>> > -
>> > -     if (master_ctl & GEN8_GT_VECS_IRQ) {
>> > -             gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
>> > -             if (likely(gt_iir[3]))
>> > -                     raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
>> > -     }
>> > -}
>> > -
>> > -void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
>> > -{
>> > -     if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
>> > -             cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
>> > -                            gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
>> > -             cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
>> > -                            gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
>> > +             iir = raw_reg_read(regs, GEN8_GT_IIR(0));
>> > +             if (likely(iir)) {
>> > +                     cs_irq_handler(gt->engine_class[RENDER_CLASS][0],
>> > +                                    iir >> GEN8_RCS_IRQ_SHIFT);
>> > +                     cs_irq_handler(gt->engine_class[COPY_ENGINE_CLASS][0],
>> > +                                    iir >> GEN8_BCS_IRQ_SHIFT);
>> > +                     raw_reg_write(regs, GEN8_GT_IIR(0), iir);
>> > +             }
>> >       }
>> >  
>> >       if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
>> > -             cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0],
>> > -                            gt_iir[1] >> GEN8_VCS0_IRQ_SHIFT);
>> > -             cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1],
>> > -                            gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
>> > +             iir = raw_reg_read(regs, GEN8_GT_IIR(1));
>> > +             if (likely(iir)) {
>> > +                     cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][0],
>> > +                                    iir >> GEN8_VCS0_IRQ_SHIFT);
>> > +                     cs_irq_handler(gt->engine_class[VIDEO_DECODE_CLASS][1],
>> > +                                    iir >> GEN8_VCS1_IRQ_SHIFT);
>> > +                     raw_reg_write(regs, GEN8_GT_IIR(1), iir);
>> > +             }
>> >       }
>> >  
>> >       if (master_ctl & GEN8_GT_VECS_IRQ) {
>> > -             cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
>> > -                            gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
>> > +             iir = raw_reg_read(regs, GEN8_GT_IIR(3));
>> > +             if (likely(iir)) {
>> > +                     cs_irq_handler(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0],
>> > +                                    iir >> GEN8_VECS_IRQ_SHIFT);
>> > +                     raw_reg_write(regs, GEN8_GT_IIR(3), iir);
>> > +             }
>> >       }
>> >  
>> >       if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
>> > -             gen6_rps_irq_handler(&gt->rps, gt_iir[2]);
>> > -             guc_irq_handler(&gt->uc.guc, gt_iir[2] >> 16);
>> > +             iir = raw_reg_read(regs, GEN8_GT_IIR(2));
>> > +             if (likely(iir)) {
>> > +                     gen6_rps_irq_handler(&gt->rps, iir);
>> > +                     guc_irq_handler(&gt->uc.guc, iir >> 16);
>> > +                     raw_reg_write(regs, GEN8_GT_IIR(2), iir);
>> > +             }
>> >       }
>> >  }
>> >  
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
>> > index 8f37593712c9..886c5cf408a2 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h
>> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h
>> > @@ -36,9 +36,8 @@ void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask);
>> >  
>> >  void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir);
>> >  
>> > -void gen8_gt_irq_ack(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4]);
>> > +void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl);
>> >  void gen8_gt_irq_reset(struct intel_gt *gt);
>> > -void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4]);
>> >  void gen8_gt_irq_postinstall(struct intel_gt *gt);
>> >  
>> >  #endif /* INTEL_GT_IRQ_H */
>> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> > index 87a6662abc1b..e40dd226fde8 100644
>> > --- a/drivers/gpu/drm/i915/i915_irq.c
>> > +++ b/drivers/gpu/drm/i915/i915_irq.c
>> > @@ -1614,7 +1614,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>> >               u32 master_ctl, iir;
>> >               u32 pipe_stats[I915_MAX_PIPES] = {};
>> >               u32 hotplug_status = 0;
>> > -             u32 gt_iir[4];
>> >               u32 ier = 0;
>> >  
>> >               master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
>> > @@ -1642,7 +1641,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>> >               ier = I915_READ(VLV_IER);
>> >               I915_WRITE(VLV_IER, 0);
>> >  
>> > -             gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir);
>> > +             gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
>> >  
>> >               if (iir & I915_DISPLAY_PORT_INTERRUPT)
>> >                       hotplug_status = i9xx_hpd_irq_ack(dev_priv);
>> > @@ -1666,8 +1665,6 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
>> >               I915_WRITE(VLV_IER, ier);
>> >               I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
>> >  
>> > -             gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
>> > -
>> >               if (hotplug_status)
>> >                       i9xx_hpd_irq_handler(dev_priv, hotplug_status);
>> >  
>> > @@ -2396,7 +2393,6 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>> >       struct drm_i915_private *dev_priv = arg;
>> >       void __iomem * const regs = dev_priv->uncore.regs;
>> >       u32 master_ctl;
>> > -     u32 gt_iir[4];
>> >  
>> >       if (!intel_irqs_enabled(dev_priv))
>> >               return IRQ_NONE;
>> > @@ -2408,7 +2404,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
>> >       }
>> >  
>> >       /* Find, clear, then process each source of interrupt */
>> 
>> /* Find, process and then clear each source of interrupt */
>
> The order is still ack / process, and that is quite important for
> allowing interrupt delivery as we process. It's just that we use
> bottom-halves rather than a local deferral.
>
> 	/* Find, clear, then process (via bottom-halves) each source of interrupt */

True, I parsed the process on activating the bottom-halves.
Clearly it is not a very interesting part of the _process_.

Patch is,
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

In it's original form.
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[Intel-gfx] [PATCH 3/6] drm/i915/gt: Tidy repetition in declaring gen8+ interrupts

[Chris Wilson]

We use the same interrupt mask for each engine, so define it once in a
local and reuse.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_gt_irq.c | 22 ++++++----------------
 1 file changed, 6 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 71873a4cafc0..7278b10e1a03 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -344,25 +344,15 @@ void gen8_gt_irq_reset(struct intel_gt *gt)
 
 void gen8_gt_irq_postinstall(struct intel_gt *gt)
 {
-	struct intel_uncore *uncore = gt->uncore;
-
 	/* These are interrupts we'll toggle with the ring mask register */
-	u32 gt_interrupts[] = {
-		(GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
-		 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
-		 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
-		 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT),
-
-		(GT_RENDER_USER_INTERRUPT << GEN8_VCS0_IRQ_SHIFT |
-		 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS0_IRQ_SHIFT |
-		 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
-		 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT),
-
+	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+	const u32 gt_interrupts[] = {
+		irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
+		irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
 		0,
-
-		(GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
-		 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)
+		irqs << GEN8_VECS_IRQ_SHIFT,
 	};
+	struct intel_uncore *uncore = gt->uncore;
 
 	gt->pm_ier = 0x0;
 	gt->pm_imr = ~gt->pm_ier;
-- 
2.25.0

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Re: [Intel-gfx] [PATCH 3/6] drm/i915/gt: Tidy repetition in declaring gen8+ interrupts

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> We use the same interrupt mask for each engine, so define it once in a
> local and reuse.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_gt_irq.c | 22 ++++++----------------
>  1 file changed, 6 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 71873a4cafc0..7278b10e1a03 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -344,25 +344,15 @@ void gen8_gt_irq_reset(struct intel_gt *gt)
>  
>  void gen8_gt_irq_postinstall(struct intel_gt *gt)
>  {
> -	struct intel_uncore *uncore = gt->uncore;
> -
>  	/* These are interrupts we'll toggle with the ring mask register */
> -	u32 gt_interrupts[] = {
> -		(GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
> -		 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
> -		 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
> -		 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT),
> -
> -		(GT_RENDER_USER_INTERRUPT << GEN8_VCS0_IRQ_SHIFT |
> -		 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS0_IRQ_SHIFT |
> -		 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
> -		 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT),
> -
> +	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
> +	const u32 gt_interrupts[] = {
> +		irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
> +		irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
>  		0,
> -
> -		(GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
> -		 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)
> +		irqs << GEN8_VECS_IRQ_SHIFT,
>  	};
> +	struct intel_uncore *uncore = gt->uncore;
>  
>  	gt->pm_ier = 0x0;
>  	gt->pm_imr = ~gt->pm_ier;
> -- 
> 2.25.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] [PATCH 4/6] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore

[Chris Wilson]

If we find ourselves waiting on a MI_SEMAPHORE_WAIT, either within the
user batch or in our own preamble, the engine raises a
GT_WAIT_ON_SEMAPHORE interrupt. We can unmask that interrupt and so
respond to a semaphore wait by yielding the timeslice, if we have
another context to yield to!

The only real complication is that the interrupt is only generated for
the start of the semaphore wait, and is asynchronous to our
process_csb() -- that is, we may not have registered the timeslice before
we see the interrupt. To ensure we don't miss a potential semaphore
blocking forward progress (e.g. selftests/live_timeslice_preempt) we mark
the interrupt and apply it to the next timeslice regardless of whether it
was active at the time.

v2: We use semaphores in preempt-to-busy, within the timeslicing
implementation itself! Ergo, when we do insert a preemption due to an
expired timeslice, the new context may start with the missed semaphore
flagged by the retired context and be yielded, ad infinitum. To avoid
this, read the context id at the time of the semaphore interrupt and
only yield if that context is still active.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |  6 ++++
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  9 +++++
 drivers/gpu/drm/i915/gt/intel_gt_irq.c       | 17 +++++++--
 drivers/gpu/drm/i915/gt/intel_lrc.c          | 36 ++++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h              |  5 +++
 5 files changed, 65 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9b965d1f811d..841fe1a4b0a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1277,6 +1277,12 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
 
 	if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
 		drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
+	if (HAS_EXECLISTS(dev_priv)) {
+		drm_printf(m, "\tEL_CCID:    0x%08x\n",
+			   ENGINE_READ(engine, EXECLIST_CCID));
+		drm_printf(m, "\tEL_STATUS:  0x%08x\n",
+			   ENGINE_READ(engine, EXECLIST_STATUS));
+	}
 	drm_printf(m, "\tRING_START: 0x%08x\n",
 		   ENGINE_READ(engine, RING_START));
 	drm_printf(m, "\tRING_HEAD:  0x%08x\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 92be41a6903c..58725024ffa4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -156,6 +156,15 @@ struct intel_engine_execlists {
 	 */
 	struct i915_priolist default_priolist;
 
+	/**
+	 * @yield: CCID at the time of the last semaphore-wait interrupt.
+	 *
+	 * Instead of leaving a semaphore busy-spinning on an engine, we would
+	 * like to switch to another ready context, i.e. yielding the semaphore
+	 * timeslice.
+	 */
+	u32 yield;
+
 	/**
 	 * @no_priolist: priority lists disabled
 	 */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 7278b10e1a03..cf8c71eb6d16 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -24,6 +24,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
 {
 	bool tasklet = false;
 
+	if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
+		WRITE_ONCE(engine->execlists.yield,
+			   ENGINE_READ_FW(engine, EXECLIST_CCID));
+		if (del_timer(&engine->execlists.timer))
+			tasklet = true;
+	}
+
 	if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
 		tasklet = true;
 
@@ -210,7 +217,10 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
 
 void gen11_gt_irq_postinstall(struct intel_gt *gt)
 {
-	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+	const u32 irqs =
+		GT_RENDER_USER_INTERRUPT |
+		GT_CONTEXT_SWITCH_INTERRUPT |
+		GT_WAIT_SEMAPHORE_INTERRUPT;
 	struct intel_uncore *uncore = gt->uncore;
 	const u32 dmask = irqs << 16 | irqs;
 	const u32 smask = irqs << 16;
@@ -345,7 +355,10 @@ void gen8_gt_irq_reset(struct intel_gt *gt)
 void gen8_gt_irq_postinstall(struct intel_gt *gt)
 {
 	/* These are interrupts we'll toggle with the ring mask register */
-	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+	const u32 irqs =
+		GT_RENDER_USER_INTERRUPT |
+		GT_CONTEXT_SWITCH_INTERRUPT |
+		GT_WAIT_SEMAPHORE_INTERRUPT;
 	const u32 gt_interrupts[] = {
 		irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
 		irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index cf6c43bd540a..20b8a10bb8cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1661,7 +1661,8 @@ static void defer_active(struct intel_engine_cs *engine)
 }
 
 static bool
-need_timeslice(struct intel_engine_cs *engine, const struct i915_request *rq)
+need_timeslice(const struct intel_engine_cs *engine,
+	       const struct i915_request *rq)
 {
 	int hint;
 
@@ -1677,6 +1678,27 @@ need_timeslice(struct intel_engine_cs *engine, const struct i915_request *rq)
 	return hint >= effective_prio(rq);
 }
 
+static bool
+timeslice_expired(const struct intel_engine_cs *engine,
+		  const struct i915_request *rq)
+{
+	const struct intel_engine_execlists *el = &engine->execlists;
+
+	return (timer_expired(&el->timer) ||
+		/*
+		 * Once bitten, forever smitten!
+		 *
+		 * If the active context ever busy-waited on a semaphore,
+		 * it will be treated as a hog until the end of its timeslice.
+		 * The HW only sends an interrupt on the first miss, and we
+		 * do know if that semaphore has been signaled, or even if it
+		 * is now stuck on another semaphore. Play safe, yield if it
+		 * might be stuck -- it will be given a fresh timeslice in
+		 * the near future.
+		 */
+		upper_32_bits(rq->context->lrc_desc) == READ_ONCE(el->yield));
+}
+
 static int
 switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq)
 {
@@ -1692,8 +1714,7 @@ timeslice(const struct intel_engine_cs *engine)
 	return READ_ONCE(engine->props.timeslice_duration_ms);
 }
 
-static unsigned long
-active_timeslice(const struct intel_engine_cs *engine)
+static unsigned long active_timeslice(const struct intel_engine_cs *engine)
 {
 	const struct i915_request *rq = *engine->execlists.active;
 
@@ -1844,13 +1865,14 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 			last->context->lrc_desc |= CTX_DESC_FORCE_RESTORE;
 			last = NULL;
 		} else if (need_timeslice(engine, last) &&
-			   timer_expired(&engine->execlists.timer)) {
+			   timeslice_expired(engine, last)) {
 			ENGINE_TRACE(engine,
-				     "expired last=%llx:%lld, prio=%d, hint=%d\n",
+				     "expired last=%llx:%lld, prio=%d, hint=%d, yield?=%s\n",
 				     last->fence.context,
 				     last->fence.seqno,
 				     last->sched.attr.priority,
-				     execlists->queue_priority_hint);
+				     execlists->queue_priority_hint,
+				     yesno(upper_32_bits(last->context->lrc_desc) == READ_ONCE(execlists->yield)));
 
 			ring_set_paused(engine, 1);
 			defer_active(engine);
@@ -2110,6 +2132,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 		}
 		clear_ports(port + 1, last_port - port);
 
+		WRITE_ONCE(execlists->yield, -1);
 		execlists_submit_ports(engine);
 		set_preempt_timeout(engine);
 	} else {
@@ -4290,6 +4313,7 @@ logical_ring_default_irqs(struct intel_engine_cs *engine)
 
 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
 	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
+	engine->irq_keep_mask |= GT_WAIT_SEMAPHORE_INTERRUPT << shift;
 }
 
 static void rcs_submission_override(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b93c4c18f05c..535ce7e0dc94 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3085,6 +3085,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
 #define GT_BSD_USER_INTERRUPT			(1 << 12)
 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1	(1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
+#define GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11) /* bdw+ */
 #define GT_CONTEXT_SWITCH_INTERRUPT		(1 <<  8)
 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
@@ -4036,6 +4037,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   CCID_EN			BIT(0)
 #define   CCID_EXTENDED_STATE_RESTORE	BIT(2)
 #define   CCID_EXTENDED_STATE_SAVE	BIT(3)
+
+#define EXECLIST_STATUS(base)	_MMIO((base) + 0x234)
+#define EXECLIST_CCID(base)	_MMIO((base) + 0x238)
+
 /*
  * Notes on SNB/IVB/VLV context size:
  * - Power context is saved elsewhere (LLC or stolen)
-- 
2.25.0

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[Intel-gfx] [PATCH 5/6] drm/i915/gt: Hook up CS_MASTER_ERROR_INTERRUPT

[Chris Wilson]

Now that we have offline error capture and can reset an engine from
inside an atomic context while also preserving the GPU state for
post-mortem analysis, it is time to handle error interrupts thrown by
the command parser.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |   8 +-
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  10 ++
 drivers/gpu/drm/i915/gt/intel_gt.c           |   5 +
 drivers/gpu/drm/i915/gt/intel_gt_irq.c       |  19 ++-
 drivers/gpu/drm/i915/gt/intel_lrc.c          |  54 ++++--
 drivers/gpu/drm/i915/gt/selftest_lrc.c       | 166 +++++++++++++++++--
 drivers/gpu/drm/i915/i915_gpu_error.c        |   2 +
 drivers/gpu/drm/i915/i915_gpu_error.h        |   1 +
 drivers/gpu/drm/i915/i915_reg.h              |   5 +-
 9 files changed, 237 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 841fe1a4b0a5..4a2693fb5f8d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1299,8 +1299,14 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
 	}
 
 	if (INTEL_GEN(dev_priv) >= 6) {
-		drm_printf(m, "\tRING_IMR: %08x\n",
+		drm_printf(m, "\tRING_IMR:   0x%08x\n",
 			   ENGINE_READ(engine, RING_IMR));
+		drm_printf(m, "\tRING_ESR:   0x%08x\n",
+			   ENGINE_READ(engine, RING_ESR));
+		drm_printf(m, "\tRING_EMR:   0x%08x\n",
+			   ENGINE_READ(engine, RING_EMR));
+		drm_printf(m, "\tRING_EIR:   0x%08x\n",
+			   ENGINE_READ(engine, RING_EIR));
 	}
 
 	addr = intel_engine_get_active_head(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 58725024ffa4..c7ea986878c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -165,6 +165,16 @@ struct intel_engine_execlists {
 	 */
 	u32 yield;
 
+	/**
+	 * @error_interrupt: CS Master EIR
+	 *
+	 * The CS generates an interrupt when it detects an error. We capture
+	 * the first error interrupt, record the EIR and schedule the tasklet.
+	 * In the tasklet, we process the pending CS events to ensure we have
+	 * the guilty request, and then reset the engine.
+	 */
+	u32 error_interrupt;
+
 	/**
 	 * @no_priolist: priority lists disabled
 	 */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 88b6c904607c..143268083135 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -455,6 +455,11 @@ static int __engines_record_defaults(struct intel_gt *gt)
 		if (!rq)
 			continue;
 
+		if (rq->fence.error) {
+			err = -EIO;
+			goto out;
+		}
+
 		GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags));
 		state = rq->context->state;
 		if (!state)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index cf8c71eb6d16..68557a263009 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -24,6 +24,21 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
 {
 	bool tasklet = false;
 
+	if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
+		u32 eir;
+
+		eir = ENGINE_READ(engine, RING_EIR);
+		ENGINE_TRACE(engine, "CS error: %x\n", eir);
+
+		/* Disable the error interrupt until after the reset */
+		if (likely(eir)) {
+			ENGINE_WRITE(engine, RING_EMR, ~0u);
+			ENGINE_WRITE(engine, RING_EIR, eir);
+			engine->execlists.error_interrupt = eir;
+			tasklet = true;
+		}
+	}
+
 	if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
 		WRITE_ONCE(engine->execlists.yield,
 			   ENGINE_READ_FW(engine, EXECLIST_CCID));
@@ -218,6 +233,7 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
 void gen11_gt_irq_postinstall(struct intel_gt *gt)
 {
 	const u32 irqs =
+		GT_CS_MASTER_ERROR_INTERRUPT |
 		GT_RENDER_USER_INTERRUPT |
 		GT_CONTEXT_SWITCH_INTERRUPT |
 		GT_WAIT_SEMAPHORE_INTERRUPT;
@@ -289,7 +305,7 @@ void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
 
 	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
 		      GT_BSD_CS_ERROR_INTERRUPT |
-		      GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
+		      GT_CS_MASTER_ERROR_INTERRUPT))
 		DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
 
 	if (gt_iir & GT_PARITY_ERROR(gt->i915))
@@ -356,6 +372,7 @@ void gen8_gt_irq_postinstall(struct intel_gt *gt)
 {
 	/* These are interrupts we'll toggle with the ring mask register */
 	const u32 irqs =
+		GT_CS_MASTER_ERROR_INTERRUPT |
 		GT_RENDER_USER_INTERRUPT |
 		GT_CONTEXT_SWITCH_INTERRUPT |
 		GT_WAIT_SEMAPHORE_INTERRUPT;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 20b8a10bb8cb..e5deff9e49a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2636,13 +2636,13 @@ static bool execlists_capture(struct intel_engine_cs *engine)
 	if (!cap)
 		return true;
 
+	spin_lock_irq(&engine->active.lock);
 	cap->rq = execlists_active(&engine->execlists);
-	GEM_BUG_ON(!cap->rq);
-
-	rcu_read_lock();
-	cap->rq = active_request(cap->rq->context->timeline, cap->rq);
-	cap->rq = i915_request_get_rcu(cap->rq);
-	rcu_read_unlock();
+	if (cap->rq) {
+		cap->rq = active_request(cap->rq->context->timeline, cap->rq);
+		cap->rq = i915_request_get_rcu(cap->rq);
+	}
+	spin_unlock_irq(&engine->active.lock);
 	if (!cap->rq)
 		goto err_free;
 
@@ -2681,27 +2681,25 @@ static bool execlists_capture(struct intel_engine_cs *engine)
 	return false;
 }
 
-static noinline void preempt_reset(struct intel_engine_cs *engine)
+static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
 {
 	const unsigned int bit = I915_RESET_ENGINE + engine->id;
 	unsigned long *lock = &engine->gt->reset.flags;
 
-	if (i915_modparams.reset < 3)
+	if (!intel_has_reset_engine(engine->gt))
 		return;
 
 	if (test_and_set_bit(bit, lock))
 		return;
 
+	ENGINE_TRACE(engine, "reset for %s\n", msg);
+
 	/* Mark this tasklet as disabled to avoid waiting for it to complete */
 	tasklet_disable_nosync(&engine->execlists.tasklet);
 
-	ENGINE_TRACE(engine, "preempt timeout %lu+%ums\n",
-		     READ_ONCE(engine->props.preempt_timeout_ms),
-		     jiffies_to_msecs(jiffies - engine->execlists.preempt.expires));
-
 	ring_set_paused(engine, 1); /* Freeze the current request in place */
 	if (execlists_capture(engine))
-		intel_engine_reset(engine, "preemption time out");
+		intel_engine_reset(engine, msg);
 	else
 		ring_set_paused(engine, 0);
 
@@ -2732,6 +2730,10 @@ static void execlists_submission_tasklet(unsigned long data)
 	bool timeout = preempt_timeout(engine);
 
 	process_csb(engine);
+
+	if (unlikely(engine->execlists.error_interrupt))
+		execlists_reset(engine, "CS error");
+
 	if (!READ_ONCE(engine->execlists.pending[0]) || timeout) {
 		unsigned long flags;
 
@@ -2740,8 +2742,8 @@ static void execlists_submission_tasklet(unsigned long data)
 		spin_unlock_irqrestore(&engine->active.lock, flags);
 
 		/* Recheck after serialising with direct-submission */
-		if (timeout && preempt_timeout(engine))
-			preempt_reset(engine);
+		if (unlikely(timeout && preempt_timeout(engine)))
+			execlists_reset(engine, "preemption time out");
 	}
 }
 
@@ -3366,6 +3368,25 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 	return ret;
 }
 
+static void enable_error_interrupt(struct intel_engine_cs *engine)
+{
+	u32 status;
+
+	engine->execlists.error_interrupt = 0;
+	ENGINE_WRITE(engine, RING_EMR, ~0u);
+	ENGINE_WRITE(engine, RING_EIR, ~0u); /* clear all existing errors */
+
+	status = ENGINE_READ(engine, RING_ESR);
+	if (unlikely(status)) {
+		dev_err(engine->i915->drm.dev,
+			"engine '%s' resumed still in error: %08x\n",
+			engine->name, status);
+		__intel_gt_reset(engine->gt, engine->mask);
+	}
+
+	ENGINE_WRITE(engine, RING_EMR, ~REG_BIT(0));
+}
+
 static void enable_execlists(struct intel_engine_cs *engine)
 {
 	u32 mode;
@@ -3387,6 +3408,8 @@ static void enable_execlists(struct intel_engine_cs *engine)
 			i915_ggtt_offset(engine->status_page.vma));
 	ENGINE_POSTING_READ(engine, RING_HWS_PGA);
 
+	enable_error_interrupt(engine);
+
 	engine->context_tag = 0;
 }
 
@@ -4314,6 +4337,7 @@ logical_ring_default_irqs(struct intel_engine_cs *engine)
 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
 	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
 	engine->irq_keep_mask |= GT_WAIT_SEMAPHORE_INTERRUPT << shift;
+	engine->irq_keep_mask |= GT_CS_MASTER_ERROR_INTERRUPT << shift;
 }
 
 static void rcs_submission_override(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 65718ca2326e..2622c305c6fe 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -68,6 +68,21 @@ static void engine_heartbeat_enable(struct intel_engine_cs *engine,
 	engine->props.heartbeat_interval_ms = saved;
 }
 
+static int wait_for_submit(struct intel_engine_cs *engine,
+			   struct i915_request *rq,
+			   unsigned long timeout)
+{
+	timeout += jiffies;
+	do {
+		cond_resched();
+		intel_engine_flush_submission(engine);
+		if (i915_request_is_active(rq))
+			return 0;
+	} while (time_before(jiffies, timeout));
+
+	return -ETIME;
+}
+
 static int live_sanitycheck(void *arg)
 {
 	struct intel_gt *gt = arg;
@@ -386,6 +401,141 @@ static int live_hold_reset(void *arg)
 	return err;
 }
 
+static const char *error_repr(int err)
+{
+	return err ? "bad" : "good";
+}
+
+static int live_error_interrupt(void *arg)
+{
+	static const struct error_phase {
+		enum { GOOD = 0, BAD = -EIO } error[2];
+	} phases[] = {
+		{ { BAD,  GOOD } },
+		{ { BAD,  BAD  } },
+		{ { BAD,  GOOD } },
+		{ { GOOD, GOOD } }, /* sentinel */
+	};
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+
+	/*
+	 * We hook up the CS_MASTER_ERROR_INTERRUPT to have forewarning
+	 * of invalid commands in user batches that will cause a GPU hang.
+	 * This is a faster mechanism than using hangcheck/heartbeats, but
+	 * only detects problems the HW knows about -- it will not warn when
+	 * we kill the HW!
+	 *
+	 * To verify our detection and reset, we throw some invalid commands
+	 * at the HW and wait for the interrupt.
+	 */
+
+	if (!intel_has_reset_engine(gt))
+		return 0;
+
+	for_each_engine(engine, gt, id) {
+		const struct error_phase *p;
+		unsigned long heartbeat;
+
+		engine_heartbeat_disable(engine, &heartbeat);
+
+		for (p = phases; p->error[0] != GOOD; p++) {
+			struct i915_request *client[ARRAY_SIZE(phases->error)];
+			int err = 0, i;
+			u32 *cs;
+
+			memset(client, 0, sizeof(*client));
+			for (i = 0; i < ARRAY_SIZE(client); i++) {
+				struct intel_context *ce;
+				struct i915_request *rq;
+
+				ce = intel_context_create(engine);
+				if (IS_ERR(ce)) {
+					err = PTR_ERR(ce);
+					goto out;
+				}
+
+				rq = intel_context_create_request(ce);
+				intel_context_put(ce);
+				if (IS_ERR(rq)) {
+					err = PTR_ERR(rq);
+					goto out;
+				}
+
+				if (rq->engine->emit_init_breadcrumb) {
+					err = rq->engine->emit_init_breadcrumb(rq);
+					if (err) {
+						i915_request_add(rq);
+						goto out;
+					}
+				}
+
+				cs = intel_ring_begin(rq, 2);
+				if (IS_ERR(cs)) {
+					i915_request_add(rq);
+					err = PTR_ERR(cs);
+					goto out;
+				}
+
+				if (p->error[i]) {
+					*cs++ = 0xdeadbeef;
+					*cs++ = 0xdeadbeef;
+				} else {
+					*cs++ = MI_NOOP;
+					*cs++ = MI_NOOP;
+				}
+
+				client[i] = i915_request_get(rq);
+				i915_request_add(rq);
+			}
+
+			err = wait_for_submit(engine, client[0], HZ / 2);
+			if (err) {
+				pr_err("%s: first request did not start within time!\n",
+				       engine->name);
+				err = -ETIME;
+				goto out;
+			}
+
+			for (i = 0; i < ARRAY_SIZE(client); i++) {
+				if (i915_request_wait(client[i], 0, HZ / 5) < 0) {
+					pr_err("%s: %s request still executing!\n",
+					       engine->name,
+					       error_repr(p->error[i]));
+					err = -ETIME;
+					goto out;
+				}
+
+				if (client[i]->fence.error != p->error[i]) {
+					pr_err("%s: %s request completed with wrong error code: %d\n",
+					       engine->name,
+					       error_repr(p->error[i]),
+					       client[i]->fence.error);
+					err = -EINVAL;
+					goto out;
+				}
+			}
+
+out:
+			for (i = 0; i < ARRAY_SIZE(client); i++)
+				if (client[i])
+					i915_request_put(client[i]);
+			if (err) {
+				pr_err("%s: failed at phase[%ld] { %d, %d }\n",
+				       engine->name, p - phases,
+				       p->error[0], p->error[1]);
+				intel_gt_set_wedged(gt);
+				return err;
+			}
+		}
+
+		engine_heartbeat_enable(engine, heartbeat);
+	}
+
+	return 0;
+}
+
 static int
 emit_semaphore_chain(struct i915_request *rq, struct i915_vma *vma, int idx)
 {
@@ -628,21 +778,6 @@ static struct i915_request *nop_request(struct intel_engine_cs *engine)
 	return rq;
 }
 
-static int wait_for_submit(struct intel_engine_cs *engine,
-			   struct i915_request *rq,
-			   unsigned long timeout)
-{
-	timeout += jiffies;
-	do {
-		cond_resched();
-		intel_engine_flush_submission(engine);
-		if (i915_request_is_active(rq))
-			return 0;
-	} while (time_before(jiffies, timeout));
-
-	return -ETIME;
-}
-
 static long timeslice_threshold(const struct intel_engine_cs *engine)
 {
 	return 2 * msecs_to_jiffies_timeout(timeslice(engine)) + 1;
@@ -3572,6 +3707,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
 		SUBTEST(live_unlite_switch),
 		SUBTEST(live_unlite_preempt),
 		SUBTEST(live_hold_reset),
+		SUBTEST(live_error_interrupt),
 		SUBTEST(live_timeslice_preempt),
 		SUBTEST(live_timeslice_queue),
 		SUBTEST(live_busywait_preempt),
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0f67bef83106..dcab4723b17d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -515,6 +515,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
 		   (u32)(ee->acthd>>32), (u32)ee->acthd);
 	err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 	err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
+	err_printf(m, "  ESR:   0x%08x\n", ee->esr);
 
 	error_print_instdone(m, ee);
 
@@ -1102,6 +1103,7 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
 	}
 
 	if (INTEL_GEN(i915) >= 4) {
+		ee->esr = ENGINE_READ(engine, RING_ESR);
 		ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
 		ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
 		ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index e4a6afed3bbf..b35bc9edd733 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -75,6 +75,7 @@ struct intel_engine_coredump {
 	u32 hws;
 	u32 ipeir;
 	u32 ipehr;
+	u32 esr;
 	u32 bbstate;
 	u32 instpm;
 	u32 instps;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 535ce7e0dc94..e5cff51343af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2639,6 +2639,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   GEN11_MCR_SUBSLICE_MASK	GEN11_MCR_SUBSLICE(0x7)
 #define RING_IPEIR(base)	_MMIO((base) + 0x64)
 #define RING_IPEHR(base)	_MMIO((base) + 0x68)
+#define RING_EIR(base)		_MMIO((base) + 0xb0)
+#define RING_EMR(base)		_MMIO((base) + 0xb4)
+#define RING_ESR(base)		_MMIO((base) + 0xb8)
 /*
  * On GEN4, only the render ring INSTDONE exists and has a different
  * layout than the GEN7+ version.
@@ -3089,7 +3092,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GT_CONTEXT_SWITCH_INTERRUPT		(1 <<  8)
 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT	(1 <<  5) /* !snb */
 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	(1 <<  4)
-#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT	(1 <<  3)
+#define GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
 #define GT_RENDER_SYNC_STATUS_INTERRUPT		(1 <<  2)
 #define GT_RENDER_DEBUG_INTERRUPT		(1 <<  1)
 #define GT_RENDER_USER_INTERRUPT		(1 <<  0)
-- 
2.25.0

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[Intel-gfx] [PATCH 6/6] drm/i915/gt: Lift set-wedged engine dumping out of user paths

[Chris Wilson]

The user (e.g. gem_eio) can manipulate the driver into wedging itself,
allowing the user to trigger voluminous logging of inconsequential
details. If we lift the dump to direct calls to intel_gt_set_wedged(),
out of the intel_reset failure handling, we keep the detail logging for
what we expect are true HW or test failures without being tricked.

Reported-by: Tomi Sarvela <tomi.p.sarvela@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_reset.c | 30 +++++++++++++++++++--------
 1 file changed, 21 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index beee0cf89bce..423a02506b2d 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -800,13 +800,6 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
 	if (test_bit(I915_WEDGED, &gt->reset.flags))
 		return;
 
-	if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
-		struct drm_printer p = drm_debug_printer(__func__);
-
-		for_each_engine(engine, gt, id)
-			intel_engine_dump(engine, &p, "%s\n", engine->name);
-	}
-
 	GT_TRACE(gt, "start\n");
 
 	/*
@@ -845,10 +838,29 @@ void intel_gt_set_wedged(struct intel_gt *gt)
 {
 	intel_wakeref_t wakeref;
 
+	if (test_bit(I915_WEDGED, &gt->reset.flags))
+		return;
+
+	wakeref = intel_runtime_pm_get(gt->uncore->rpm);
 	mutex_lock(&gt->reset.mutex);
-	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
-		__intel_gt_set_wedged(gt);
+
+	if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
+		struct drm_printer p = drm_debug_printer(__func__);
+		struct intel_engine_cs *engine;
+		enum intel_engine_id id;
+
+		for_each_engine(engine, gt, id) {
+			if (intel_engine_is_idle(engine))
+				continue;
+
+			intel_engine_dump(engine, &p, "%s\n", engine->name);
+		}
+	}
+
+	__intel_gt_set_wedged(gt);
+
 	mutex_unlock(&gt->reset.mutex);
+	intel_runtime_pm_put(gt->uncore->rpm, wakeref);
 }
 
 static bool __intel_gt_unset_wedged(struct intel_gt *gt)
-- 
2.25.0

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Re: [Intel-gfx] [PATCH 6/6] drm/i915/gt: Lift set-wedged engine dumping out of user paths

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> The user (e.g. gem_eio) can manipulate the driver into wedging itself,
> allowing the user to trigger voluminous logging of inconsequential
> details. If we lift the dump to direct calls to intel_gt_set_wedged(),
> out of the intel_reset failure handling, we keep the detail logging for
> what we expect are true HW or test failures without being tricked.
>
> Reported-by: Tomi Sarvela <tomi.p.sarvela@intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_reset.c | 30 +++++++++++++++++++--------
>  1 file changed, 21 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index beee0cf89bce..423a02506b2d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -800,13 +800,6 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
>  	if (test_bit(I915_WEDGED, &gt->reset.flags))
>  		return;
>  
> -	if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
> -		struct drm_printer p = drm_debug_printer(__func__);
> -
> -		for_each_engine(engine, gt, id)
> -			intel_engine_dump(engine, &p, "%s\n", engine->name);
> -	}
> -
>  	GT_TRACE(gt, "start\n");
>  
>  	/*
> @@ -845,10 +838,29 @@ void intel_gt_set_wedged(struct intel_gt *gt)
>  {
>  	intel_wakeref_t wakeref;
>  
> +	if (test_bit(I915_WEDGED, &gt->reset.flags))
> +		return;
> +
> +	wakeref = intel_runtime_pm_get(gt->uncore->rpm);
>  	mutex_lock(&gt->reset.mutex);
> -	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> -		__intel_gt_set_wedged(gt);
> +
> +	if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {

As you inspect each engine separately the precursory idle check
seems superfluous.

-Mika

> +		struct drm_printer p = drm_debug_printer(__func__);
> +		struct intel_engine_cs *engine;
> +		enum intel_engine_id id;
> +
> +		for_each_engine(engine, gt, id) {
> +			if (intel_engine_is_idle(engine))
> +				continue;
> +
> +			intel_engine_dump(engine, &p, "%s\n", engine->name);
> +		}
> +	}
> +
> +	__intel_gt_set_wedged(gt);
> +
>  	mutex_unlock(&gt->reset.mutex);
> +	intel_runtime_pm_put(gt->uncore->rpm, wakeref);
>  }
>  
>  static bool __intel_gt_unset_wedged(struct intel_gt *gt)
> -- 
> 2.25.0
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Re: [Intel-gfx] [PATCH 6/6] drm/i915/gt: Lift set-wedged engine dumping out of user paths

[Chris Wilson]

Quoting Mika Kuoppala (2020-01-28 12:34:42)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > The user (e.g. gem_eio) can manipulate the driver into wedging itself,
> > allowing the user to trigger voluminous logging of inconsequential
> > details. If we lift the dump to direct calls to intel_gt_set_wedged(),
> > out of the intel_reset failure handling, we keep the detail logging for
> > what we expect are true HW or test failures without being tricked.
> >
> > Reported-by: Tomi Sarvela <tomi.p.sarvela@intel.com>
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_reset.c | 30 +++++++++++++++++++--------
> >  1 file changed, 21 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> > index beee0cf89bce..423a02506b2d 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > @@ -800,13 +800,6 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
> >       if (test_bit(I915_WEDGED, &gt->reset.flags))
> >               return;
> >  
> > -     if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
> > -             struct drm_printer p = drm_debug_printer(__func__);
> > -
> > -             for_each_engine(engine, gt, id)
> > -                     intel_engine_dump(engine, &p, "%s\n", engine->name);
> > -     }
> > -
> >       GT_TRACE(gt, "start\n");
> >  
> >       /*
> > @@ -845,10 +838,29 @@ void intel_gt_set_wedged(struct intel_gt *gt)
> >  {
> >       intel_wakeref_t wakeref;
> >  
> > +     if (test_bit(I915_WEDGED, &gt->reset.flags))
> > +             return;
> > +
> > +     wakeref = intel_runtime_pm_get(gt->uncore->rpm);
> >       mutex_lock(&gt->reset.mutex);
> > -     with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> > -             __intel_gt_set_wedged(gt);
> > +
> > +     if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
> 
> As you inspect each engine separately the precursory idle check
> seems superfluous.

Picky. We may throw some other debug in between :)
-Chris
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Re: [Intel-gfx] [PATCH 6/6] drm/i915/gt: Lift set-wedged engine dumping out of user paths

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Mika Kuoppala (2020-01-28 12:34:42)
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>> 
>> > The user (e.g. gem_eio) can manipulate the driver into wedging itself,
>> > allowing the user to trigger voluminous logging of inconsequential
>> > details. If we lift the dump to direct calls to intel_gt_set_wedged(),
>> > out of the intel_reset failure handling, we keep the detail logging for
>> > what we expect are true HW or test failures without being tricked.
>> >
>> > Reported-by: Tomi Sarvela <tomi.p.sarvela@intel.com>
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> > Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/gt/intel_reset.c | 30 +++++++++++++++++++--------
>> >  1 file changed, 21 insertions(+), 9 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>> > index beee0cf89bce..423a02506b2d 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>> > @@ -800,13 +800,6 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
>> >       if (test_bit(I915_WEDGED, &gt->reset.flags))
>> >               return;
>> >  
>> > -     if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
>> > -             struct drm_printer p = drm_debug_printer(__func__);
>> > -
>> > -             for_each_engine(engine, gt, id)
>> > -                     intel_engine_dump(engine, &p, "%s\n", engine->name);
>> > -     }
>> > -
>> >       GT_TRACE(gt, "start\n");
>> >  
>> >       /*
>> > @@ -845,10 +838,29 @@ void intel_gt_set_wedged(struct intel_gt *gt)
>> >  {
>> >       intel_wakeref_t wakeref;
>> >  
>> > +     if (test_bit(I915_WEDGED, &gt->reset.flags))
>> > +             return;
>> > +
>> > +     wakeref = intel_runtime_pm_get(gt->uncore->rpm);
>> >       mutex_lock(&gt->reset.mutex);
>> > -     with_intel_runtime_pm(gt->uncore->rpm, wakeref)
>> > -             __intel_gt_set_wedged(gt);
>> > +
>> > +     if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
>> 
>> As you inspect each engine separately the precursory idle check
>> seems superfluous.
>
> Picky. We may throw some other debug in between :)

Not picky. Just my tinfoil hat too tight.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> -Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Skip capturing errors from internal contexts

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Skip capturing errors from internal contexts
URL   : https://patchwork.freedesktop.org/series/72639/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5176f847f2a0 drm/i915: Skip capturing errors from internal contexts
5c4b9c7eca9e drm/i915/gt: Reorganise gen8+ interrupt handler
5b77c1593e67 drm/i915/gt: Tidy repetition in declaring gen8+ interrupts
1c4461c839c0 drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
-:176: WARNING:LONG_LINE: line over 100 characters
#176: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1875:
+				     yesno(upper_32_bits(last->context->lrc_desc) == READ_ONCE(execlists->yield)));

total: 0 errors, 1 warnings, 0 checks, 155 lines checked
e99cb72106a0 drm/i915/gt: Hook up CS_MASTER_ERROR_INTERRUPT
da5f1d218ee1 drm/i915/gt: Lift set-wedged engine dumping out of user paths

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Skip capturing errors from internal contexts

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Skip capturing errors from internal contexts
URL   : https://patchwork.freedesktop.org/series/72639/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16288
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/index.html

Known issues
------------

  Here are the changes found in Patchwork_16288 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-j1900:       [PASS][1] -> [INCOMPLETE][2] ([i915#45])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-j1900/igt@gem_close_race@basic-threads.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/fi-byt-j1900/igt@gem_close_race@basic-threads.html

  * igt@i915_selftest@live_execlists:
    - fi-icl-y:           [PASS][3] -> [INCOMPLETE][4] ([i915#140])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-y/igt@i915_selftest@live_execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/fi-icl-y/igt@i915_selftest@live_execlists.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770:        [DMESG-FAIL][5] ([i915#553] / [i915#725]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/fi-hsw-4770/igt@i915_selftest@live_blt.html

  
#### Warnings ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-icl-u2:          [DMESG-WARN][7] ([IGT#4] / [i915#263]) -> [FAIL][8] ([i915#217])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  
  [IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
  [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
  [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
  [i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
  [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
  [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725


Participating hosts (46 -> 35)
------------------------------

  Additional (3): fi-cfl-8109u fi-ivb-3770 fi-skl-6600u 
  Missing    (14): fi-ilk-m540 fi-kbl-7560u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-icl-u3 fi-bsw-kefka fi-skl-lmem fi-blb-e6850 fi-byt-clapper fi-bdw-samus fi-snb-2600 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7827 -> Patchwork_16288

  CI-20190529: 20190529
  CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16288: da5f1d218ee1d45fecdd7d3f95d004277529bfe9 @ git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_16288/build_32bit.log

  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/gt/intel_lrc.o
In file included from ./include/linux/printk.h:7:0,
                 from ./include/linux/kernel.h:15,
                 from ./include/linux/interrupt.h:6,
                 from drivers/gpu/drm/i915/gt/intel_lrc.c:134:
drivers/gpu/drm/i915/gt/selftest_lrc.c: In function ‘live_error_interrupt’:
./include/linux/kern_levels.h:5:18: error: format ‘%ld’ expects argument of type ‘long int’, but argument 3 has type ‘int’ [-Werror=format=]
 #define KERN_SOH "\001"  /* ASCII Start Of Header */
                  ^
./include/linux/kern_levels.h:11:18: note: in expansion of macro ‘KERN_SOH’
 #define KERN_ERR KERN_SOH "3" /* error conditions */
                  ^~~~~~~~
./include/linux/printk.h:304:9: note: in expansion of macro ‘KERN_ERR’
  printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
         ^~~~~~~~
drivers/gpu/drm/i915/gt/selftest_lrc.c:525:5: note: in expansion of macro ‘pr_err’
     pr_err("%s: failed at phase[%ld] { %d, %d }\n",
     ^~~~~~
In file included from drivers/gpu/drm/i915/gt/intel_lrc.c:5285:0:
drivers/gpu/drm/i915/gt/selftest_lrc.c:525:35: note: format string is defined here
     pr_err("%s: failed at phase[%ld] { %d, %d }\n",
                                 ~~^
                                 %d
cc1: all warnings being treated as errors
scripts/Makefile.build:265: recipe for target 'drivers/gpu/drm/i915/gt/intel_lrc.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_lrc.o] Error 1
scripts/Makefile.build:503: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:503: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:503: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1693: recipe for target 'drivers' failed
make: *** [drivers] Error 2


== Linux commits ==

da5f1d218ee1 drm/i915/gt: Lift set-wedged engine dumping out of user paths
e99cb72106a0 drm/i915/gt: Hook up CS_MASTER_ERROR_INTERRUPT
1c4461c839c0 drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
5b77c1593e67 drm/i915/gt: Tidy repetition in declaring gen8+ interrupts
5c4b9c7eca9e drm/i915/gt: Reorganise gen8+ interrupt handler
5176f847f2a0 drm/i915: Skip capturing errors from internal contexts

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/index.html
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[Intel-gfx] ✗ Fi.CI.BUILD: warning for series starting with [1/6] drm/i915: Skip capturing errors from internal contexts

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Skip capturing errors from internal contexts
URL   : https://patchwork.freedesktop.org/series/72639/
State : warning

== Summary ==

CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/gt/intel_lrc.o
In file included from ./include/linux/printk.h:7:0,
                 from ./include/linux/kernel.h:15,
                 from ./include/linux/interrupt.h:6,
                 from drivers/gpu/drm/i915/gt/intel_lrc.c:134:
drivers/gpu/drm/i915/gt/selftest_lrc.c: In function ‘live_error_interrupt’:
./include/linux/kern_levels.h:5:18: error: format ‘%ld’ expects argument of type ‘long int’, but argument 3 has type ‘int’ [-Werror=format=]
 #define KERN_SOH "\001"  /* ASCII Start Of Header */
                  ^
./include/linux/kern_levels.h:11:18: note: in expansion of macro ‘KERN_SOH’
 #define KERN_ERR KERN_SOH "3" /* error conditions */
                  ^~~~~~~~
./include/linux/printk.h:304:9: note: in expansion of macro ‘KERN_ERR’
  printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
         ^~~~~~~~
drivers/gpu/drm/i915/gt/selftest_lrc.c:525:5: note: in expansion of macro ‘pr_err’
     pr_err("%s: failed at phase[%ld] { %d, %d }\n",
     ^~~~~~
In file included from drivers/gpu/drm/i915/gt/intel_lrc.c:5285:0:
drivers/gpu/drm/i915/gt/selftest_lrc.c:525:35: note: format string is defined here
     pr_err("%s: failed at phase[%ld] { %d, %d }\n",
                                 ~~^
                                 %d
cc1: all warnings being treated as errors
scripts/Makefile.build:265: recipe for target 'drivers/gpu/drm/i915/gt/intel_lrc.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_lrc.o] Error 1
scripts/Makefile.build:503: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:503: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:503: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1693: recipe for target 'drivers' failed
make: *** [drivers] Error 2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/build_32bit.log
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Re: [Intel-gfx] [PATCH 1/6] drm/i915: Skip capturing errors from internal contexts

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> We don't want to report errors on the internal contexts to userspace,
> suppressing their own, so treat them as simulated errors. These mostly
> arise inside selftests and so are simulated anyway. For the rest, we can
> rely on the normal debug channels in CI.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gpu_error.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 594341e27a47..0f67bef83106 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1228,7 +1228,7 @@ static bool record_context(struct i915_gem_context_coredump *e,
>  {
>  	struct i915_gem_context *ctx;
>  	struct task_struct *task;
> -	bool capture;
> +	bool simulated;
>  
>  	rcu_read_lock();
>  	ctx = rcu_dereference(rq->context->gem_context);
> @@ -1236,7 +1236,7 @@ static bool record_context(struct i915_gem_context_coredump *e,
>  		ctx = NULL;
>  	rcu_read_unlock();
>  	if (!ctx)
> -		return false;
> +		return true;
>  
>  	rcu_read_lock();
>  	task = pid_task(ctx->pid, PIDTYPE_PID);
> @@ -1250,10 +1250,10 @@ static bool record_context(struct i915_gem_context_coredump *e,
>  	e->guilty = atomic_read(&ctx->guilty_count);
>  	e->active = atomic_read(&ctx->active_count);
>  
> -	capture = i915_gem_context_no_error_capture(ctx);
> +	simulated = i915_gem_context_no_error_capture(ctx);
>  
>  	i915_gem_context_put(ctx);
> -	return capture;
> +	return simulated;
>  }
>  
>  struct intel_engine_capture_vma {
> -- 
> 2.25.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915: Skip capturing errors from internal contexts

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Skip capturing errors from internal contexts
URL   : https://patchwork.freedesktop.org/series/72639/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7827_full -> Patchwork_16288_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_16288_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#112080]) +9 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb1/igt@gem_busy@busy-vcs1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb6/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@vcs1-clean:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb4/igt@gem_ctx_isolation@vcs1-clean.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb3/igt@gem_ctx_isolation@vcs1-clean.html

  * igt@gem_eio@in-flight-contexts-1us:
    - shard-snb:          [PASS][5] -> [FAIL][6] ([i915#490])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-snb1/igt@gem_eio@in-flight-contexts-1us.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-snb1/igt@gem_eio@in-flight-contexts-1us.html

  * igt@gem_eio@kms:
    - shard-snb:          [PASS][7] -> [INCOMPLETE][8] ([i915#82])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-snb1/igt@gem_eio@kms.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-snb4/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#110854])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb1/igt@gem_exec_balancer@smoke.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb6/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#112146]) +5 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_schedule@preempt-queue-bsd1:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#109276]) +18 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb3/igt@gem_exec_schedule@preempt-queue-bsd1.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-hsw:          [PASS][15] -> [FAIL][16] ([i915#694])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-hsw2/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-hsw2/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-apl:          [PASS][17] -> [FAIL][18] ([i915#644])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-apl4/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-apl4/igt@gem_ppgtt@flink-and-close-vma-leak.html
    - shard-skl:          [PASS][19] -> [FAIL][20] ([i915#644])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl7/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-skl5/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-skl:          [PASS][21] -> [INCOMPLETE][22] ([i915#151] / [i915#69])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl5/igt@i915_pm_rpm@system-suspend.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-skl3/igt@i915_pm_rpm@system-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#108145]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_setmode@basic:
    - shard-glk:          [PASS][29] -> [FAIL][30] ([i915#31])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-glk6/igt@kms_setmode@basic.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-glk5/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][31] -> [DMESG-WARN][32] ([i915#180]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-a-wait-idle-hang:
    - shard-hsw:          [PASS][33] -> [DMESG-WARN][34] ([i915#44]) +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-hsw4/igt@kms_vblank@pipe-a-wait-idle-hang.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-hsw5/igt@kms_vblank@pipe-a-wait-idle-hang.html

  * igt@kms_vblank@pipe-b-accuracy-idle:
    - shard-glk:          [PASS][35] -> [FAIL][36] ([i915#43])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-glk5/igt@kms_vblank@pipe-b-accuracy-idle.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-glk4/igt@kms_vblank@pipe-b-accuracy-idle.html

  * igt@kms_vblank@pipe-b-query-forked-busy-hang:
    - shard-snb:          [PASS][37] -> [SKIP][38] ([fdo#109271]) +3 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-snb1/igt@kms_vblank@pipe-b-query-forked-busy-hang.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-snb2/igt@kms_vblank@pipe-b-query-forked-busy-hang.html

  * igt@prime_mmap_coherency@write:
    - shard-hsw:          [PASS][39] -> [FAIL][40] ([i915#914])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-hsw5/igt@prime_mmap_coherency@write.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-hsw2/igt@prime_mmap_coherency@write.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@vcs1-queued:
    - shard-iclb:         [SKIP][41] ([fdo#109276] / [fdo#112080]) -> [PASS][42] +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb7/igt@gem_ctx_persistence@vcs1-queued.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_eio@in-flight-suspend:
    - shard-skl:          [INCOMPLETE][43] ([i915#69]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl5/igt@gem_eio@in-flight-suspend.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-skl3/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_parallel@vcs1-fds:
    - shard-iclb:         [SKIP][45] ([fdo#112080]) -> [PASS][46] +9 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb3/igt@gem_exec_parallel@vcs1-fds.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb4/igt@gem_exec_parallel@vcs1-fds.html

  * igt@gem_exec_schedule@pi-distinct-iova-bsd:
    - shard-iclb:         [SKIP][47] ([i915#677]) -> [PASS][48] +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb4/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb8/igt@gem_exec_schedule@pi-distinct-iova-bsd.html

  * igt@gem_exec_schedule@wide-bsd:
    - shard-iclb:         [SKIP][49] ([fdo#112146]) -> [PASS][50] +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb6/igt@gem_exec_schedule@wide-bsd.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-kbl4/igt@gem_exec_suspend@basic-s3.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-kbl4/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [DMESG-WARN][53] ([i915#180]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-apl8/igt@gem_softpin@noreloc-s3.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-apl3/igt@gem_softpin@noreloc-s3.html

  * igt@i915_pm_dc@dc5-dpms:
    - shard-iclb:         [FAIL][55] ([i915#447]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb2/igt@i915_pm_dc@dc5-dpms.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-skl:          [INCOMPLETE][57] ([i915#300]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [INCOMPLETE][59] ([i915#221]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-skl1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][61] ([fdo#108145]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_setmode@basic:
    - shard-hsw:          [FAIL][63] ([i915#31]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-hsw8/igt@kms_setmode@basic.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-hsw1/igt@kms_setmode@basic.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][65] ([fdo#109276]) -> [PASS][66] +20 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb3/igt@prime_busy@hang-bsd2.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb4/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [SKIP][67] ([fdo#109276] / [fdo#112080]) -> [FAIL][68] ([IGT#28]) +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_tiled_blits@interruptible:
    - shard-hsw:          [FAIL][69] ([i915#818]) -> [FAIL][70] ([i915#694])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-hsw7/igt@gem_tiled_blits@interruptible.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-hsw4/igt@gem_tiled_blits@interruptible.html

  * igt@gem_tiled_blits@normal:
    - shard-hsw:          [FAIL][71] ([i915#694]) -> [FAIL][72] ([i915#818])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-hsw4/igt@gem_tiled_blits@normal.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-hsw1/igt@gem_tiled_blits@normal.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglb:         [FAIL][73] ([i915#454]) -> [SKIP][74] ([i915#468])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-tglb6/igt@i915_pm_dc@dc6-dpms.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_selftest@live_blt:
    - shard-hsw:          [DMESG-FAIL][75] ([i915#553] / [i915#725]) -> [DMESG-FAIL][76] ([i915#725])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-hsw1/igt@i915_selftest@live_blt.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/shard-hsw7/igt@i915_selftest@live_blt.html

  
  [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
  [i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
  [i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#490]: https://gitlab.freedesktop.org/drm/intel/issues/490
  [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
  [i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#914]: https://gitlab.freedesktop.org/drm/intel/issues/914


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7827 -> Patchwork_16288

  CI-20190529: 20190529
  CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16288: da5f1d218ee1d45fecdd7d3f95d004277529bfe9 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16288/index.html
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