From: Matthew Auld <matthew.auld@intel.com>
To: Matthew Brost <matthew.brost@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [PATCH v4 6/7] drm/xe/tlb: also update seqno_recv during reset
Date: Thu, 6 Jul 2023 11:02:32 +0100 [thread overview]
Message-ID: <87b50115-60b6-d755-8a26-c2db3d8ea8d7@intel.com> (raw)
In-Reply-To: <ZKY9lG6LMZfugBmd@DUT025-TGLU.fm.intel.com>
On 06/07/2023 05:05, Matthew Brost wrote:
> On Wed, Jul 05, 2023 at 05:06:09PM +0100, Matthew Auld wrote:
>> We might have various kworkers waiting for TLB flushes to complete which
>> are not tracked with an explicit TLB fence, however at this stage that
>> will never happen since the CT is already disabled, so make sure we
>> signal them here under the assumption that we have completed a full GT
>> reset.
>>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Matthew Brost <matthew.brost@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
>> index b38da572d268..51789ec9ad57 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
>> @@ -89,10 +89,26 @@ invalidation_fence_signal(struct xe_gt_tlb_invalidation_fence *fence)
>> void xe_gt_tlb_invalidation_reset(struct xe_gt *gt)
>> {
>> struct xe_gt_tlb_invalidation_fence *fence, *next;
>> + struct xe_guc *guc = >->uc.guc;
>>
>> + /*
>> + * CT channel is already disabled at this point. No new TLB requests can
>> + * appear.
>> + */
>> +
>> + mutex_lock(>->uc.guc.ct.lock);
>> cancel_delayed_work(>->tlb_invalidation.fence_tdr);
>> + /*
>> + * We might have various kworkers waiting for TLB flushes to complete
>> + * which are not tracked with an explicit TLB fence, however at this
>> + * stage that will never happen since the CT is already disabled, so
>> + * make sure we signal them here under the assumption that we have
>> + * completed a full GT reset.
>> + */
>> + gt->tlb_invalidation.seqno_recv = gt->tlb_invalidation.seqno;
>> + smp_wmb();
>
> The smp_wmb() probably isn't needed, this my mistake and have this wrong
> in a places in the code. Barriers are not my strong point though so
> maybe double check on this.
I think we usually need some kind of barrier on the reader side also, so
here this would likely be at the start of tlb_invalidation_seqno_past()
or so, which is called by wait_event_timeout().
But reading[1] under the section "SLEEP AND WAKE-UP FUNCTIONS" it looks
like wait_event_timeout() and wake_up() will already have the correct
barriers for us wrt writing seqno_recv before the wake_up() and reading
it from wait_event_timeout(). I can try to type a patch.
[1] https://www.kernel.org/doc/Documentation/memory-barriers.txt
>
> Otherwise LGTM.
>
> With that:
> Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Thanks.
>
>> + wake_up_all(&guc->ct.wq);
>>
>> - mutex_lock(>->uc.guc.ct.lock);
>> list_for_each_entry_safe(fence, next,
>> >->tlb_invalidation.pending_fences, link)
>> invalidation_fence_signal(fence);
>> --
>> 2.41.0
>>
next prev parent reply other threads:[~2023-07-06 10:02 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-05 16:06 [Intel-xe] [PATCH v4 0/7] Try to handle TLB invalidations from CT fast-path Matthew Auld
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 1/7] drm/xe: hold mem_access.ref for " Matthew Auld
2023-07-06 3:51 ` Matthew Brost
2023-07-06 8:29 ` Matthew Auld
2023-07-06 14:50 ` Matthew Brost
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 2/7] drm/xe/ct: hold fast_lock when reserving space for g2h Matthew Auld
2023-07-06 3:43 ` Matthew Brost
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 3/7] drm/xe/tlb: increment next seqno after successful CT send Matthew Auld
2023-07-06 3:59 ` Matthew Brost
2023-07-06 9:42 ` Matthew Auld
2023-07-06 15:15 ` Matthew Brost
2023-07-06 15:22 ` Matthew Auld
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 4/7] drm/xe/ct: serialise fast_lock during CT disable Matthew Auld
2023-07-06 4:00 ` Matthew Brost
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 5/7] drm/xe/gt: tweak placement for signalling TLB fences after GT reset Matthew Auld
2023-07-06 4:01 ` Matthew Brost
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 6/7] drm/xe/tlb: also update seqno_recv during reset Matthew Auld
2023-07-06 4:05 ` Matthew Brost
2023-07-06 10:02 ` Matthew Auld [this message]
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 7/7] drm/xe: handle TLB invalidations from CT fast-path Matthew Auld
2023-07-06 4:14 ` Matthew Brost
2023-07-05 16:10 ` [Intel-xe] ✓ CI.Patch_applied: success for Try to handle TLB invalidations from CT fast-path (rev2) Patchwork
2023-07-05 16:11 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-07-05 16:12 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-07-05 16:16 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-07-05 16:16 ` [Intel-xe] ✓ CI.Hooks: " Patchwork
2023-07-05 16:17 ` [Intel-xe] ✓ CI.checksparse: " Patchwork
2023-07-05 17:02 ` [Intel-xe] ○ CI.BAT: info " Patchwork
2023-07-06 15:23 ` [Intel-xe] [PATCH v4 0/7] Try to handle TLB invalidations from CT fast-path Souza, Jose
2023-07-06 15:48 ` Matthew Auld
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