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From: Matthew Brost <matthew.brost@intel.com>
To: Matthew Auld <matthew.auld@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [PATCH v4 5/7] drm/xe/gt: tweak placement for signalling TLB fences after GT reset
Date: Thu, 6 Jul 2023 04:01:30 +0000	[thread overview]
Message-ID: <ZKY8mvEtFdEaPBei@DUT025-TGLU.fm.intel.com> (raw)
In-Reply-To: <20230705160602.237213-14-matthew.auld@intel.com>

On Wed, Jul 05, 2023 at 05:06:08PM +0100, Matthew Auld wrote:
> Assumption here is that submission is disabled along with CT, and full
> GT reset will also nuke TLBs, so should be safe to signal all in-flight
> TLB fences, but only after the actual reset so move the placement
> slightly.
> 
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>

Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> Cc: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_gt.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index bc76678a8276..a21d44bfe9e8 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -519,7 +519,6 @@ static int gt_reset(struct xe_gt *gt)
>  
>  	xe_uc_stop_prepare(&gt->uc);
>  	xe_gt_pagefault_reset(gt);
> -	xe_gt_tlb_invalidation_reset(gt);
>  
>  	err = xe_uc_stop(&gt->uc);
>  	if (err)
> @@ -529,6 +528,8 @@ static int gt_reset(struct xe_gt *gt)
>  	if (err)
>  		goto err_out;
>  
> +	xe_gt_tlb_invalidation_reset(gt);
> +
>  	err = do_gt_restart(gt);
>  	if (err)
>  		goto err_out;
> -- 
> 2.41.0
> 

  reply	other threads:[~2023-07-06  4:04 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-05 16:06 [Intel-xe] [PATCH v4 0/7] Try to handle TLB invalidations from CT fast-path Matthew Auld
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 1/7] drm/xe: hold mem_access.ref for " Matthew Auld
2023-07-06  3:51   ` Matthew Brost
2023-07-06  8:29     ` Matthew Auld
2023-07-06 14:50       ` Matthew Brost
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 2/7] drm/xe/ct: hold fast_lock when reserving space for g2h Matthew Auld
2023-07-06  3:43   ` Matthew Brost
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 3/7] drm/xe/tlb: increment next seqno after successful CT send Matthew Auld
2023-07-06  3:59   ` Matthew Brost
2023-07-06  9:42     ` Matthew Auld
2023-07-06 15:15       ` Matthew Brost
2023-07-06 15:22         ` Matthew Auld
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 4/7] drm/xe/ct: serialise fast_lock during CT disable Matthew Auld
2023-07-06  4:00   ` Matthew Brost
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 5/7] drm/xe/gt: tweak placement for signalling TLB fences after GT reset Matthew Auld
2023-07-06  4:01   ` Matthew Brost [this message]
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 6/7] drm/xe/tlb: also update seqno_recv during reset Matthew Auld
2023-07-06  4:05   ` Matthew Brost
2023-07-06 10:02     ` Matthew Auld
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 7/7] drm/xe: handle TLB invalidations from CT fast-path Matthew Auld
2023-07-06  4:14   ` Matthew Brost
2023-07-05 16:10 ` [Intel-xe] ✓ CI.Patch_applied: success for Try to handle TLB invalidations from CT fast-path (rev2) Patchwork
2023-07-05 16:11 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-07-05 16:12 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-07-05 16:16 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-07-05 16:16 ` [Intel-xe] ✓ CI.Hooks: " Patchwork
2023-07-05 16:17 ` [Intel-xe] ✓ CI.checksparse: " Patchwork
2023-07-05 17:02 ` [Intel-xe] ○ CI.BAT: info " Patchwork
2023-07-06 15:23 ` [Intel-xe] [PATCH v4 0/7] Try to handle TLB invalidations from CT fast-path Souza, Jose
2023-07-06 15:48   ` Matthew Auld

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