From: "Souza, Jose" <jose.souza@intel.com>
To: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
"Auld, Matthew" <matthew.auld@intel.com>
Subject: Re: [Intel-xe] [PATCH v4 0/7] Try to handle TLB invalidations from CT fast-path
Date: Thu, 6 Jul 2023 15:23:47 +0000 [thread overview]
Message-ID: <e968685ecd7bfc330dde20b885f826549e6c6e51.camel@intel.com> (raw)
In-Reply-To: <20230705160602.237213-9-matthew.auld@intel.com>
On Wed, 2023-07-05 at 17:06 +0100, Matthew Auld wrote:
> In various test cases and workloads that put the system under a heavy load, we
> can sometimes see errors with missed TLB invalidations. If we handle the TLB
> completions directly from IRQ we can see a big improvement.
>
> v4:
> - Various tweaks. Big thing is to make sure we grab the fast_lock for the g2h
> reservation when doing the CT send, which closes one big race with the CT
> fast-path.
>
Looks like the __g2h_release_space() warning are now fixed for good now.
But got one 'TLB invalidation fence timeout' while starting Xorg once on a TGL, not able to reproduce again... https://pastebin.com/UFqQ4G7Y
next prev parent reply other threads:[~2023-07-06 15:23 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-05 16:06 [Intel-xe] [PATCH v4 0/7] Try to handle TLB invalidations from CT fast-path Matthew Auld
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 1/7] drm/xe: hold mem_access.ref for " Matthew Auld
2023-07-06 3:51 ` Matthew Brost
2023-07-06 8:29 ` Matthew Auld
2023-07-06 14:50 ` Matthew Brost
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 2/7] drm/xe/ct: hold fast_lock when reserving space for g2h Matthew Auld
2023-07-06 3:43 ` Matthew Brost
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 3/7] drm/xe/tlb: increment next seqno after successful CT send Matthew Auld
2023-07-06 3:59 ` Matthew Brost
2023-07-06 9:42 ` Matthew Auld
2023-07-06 15:15 ` Matthew Brost
2023-07-06 15:22 ` Matthew Auld
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 4/7] drm/xe/ct: serialise fast_lock during CT disable Matthew Auld
2023-07-06 4:00 ` Matthew Brost
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 5/7] drm/xe/gt: tweak placement for signalling TLB fences after GT reset Matthew Auld
2023-07-06 4:01 ` Matthew Brost
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 6/7] drm/xe/tlb: also update seqno_recv during reset Matthew Auld
2023-07-06 4:05 ` Matthew Brost
2023-07-06 10:02 ` Matthew Auld
2023-07-05 16:06 ` [Intel-xe] [PATCH v4 7/7] drm/xe: handle TLB invalidations from CT fast-path Matthew Auld
2023-07-06 4:14 ` Matthew Brost
2023-07-05 16:10 ` [Intel-xe] ✓ CI.Patch_applied: success for Try to handle TLB invalidations from CT fast-path (rev2) Patchwork
2023-07-05 16:11 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-07-05 16:12 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-07-05 16:16 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-07-05 16:16 ` [Intel-xe] ✓ CI.Hooks: " Patchwork
2023-07-05 16:17 ` [Intel-xe] ✓ CI.checksparse: " Patchwork
2023-07-05 17:02 ` [Intel-xe] ○ CI.BAT: info " Patchwork
2023-07-06 15:23 ` Souza, Jose [this message]
2023-07-06 15:48 ` [Intel-xe] [PATCH v4 0/7] Try to handle TLB invalidations from CT fast-path Matthew Auld
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