Re: [Patch 5/5] multiple ring buffer support, fix a irq enable logic for BSD

Re: [Patch 5/5] multiple ring buffer support, fix a irq enable logic for BSD

[Zou, Nanhai]

>>-----Original Message-----
>>From: Anholt, Eric
>>Sent: 2010年4月13日 2:29
>>To: Zou, Nanhai; intel-gfx@lists.freedesktop.org
>>Subject: Re: [Intel-gfx] [Patch 5/5] multiple ring buffer support, fix a irq
>>enable logic for BSD
>>
>>On Wed, 7 Apr 2010 14:28:39 +0800, "Zou, Nanhai" <nanhai.zou@intel.com> wrote:
>>> Fix the BSD ring related IRQ logic on Ironlake.
>>> Without this patch, we sometimes see IRQ lost
>>> When playing H.264 content.
>>
>>This patch looks crazy.  Why do we need to do this?  How did you come up
>>with it?  What prevents races between IIR clear and IER or IMR enable (if
>>that's what the IIR clear is about).
>>

Yes, it looks a little strange. 
However HW spec from VCG do says IIR should be cleared before enable and disable interrupt.
We thought this patch fixed the interrupt lost issue seen when playing movie. But now we found it just make the issue much harder to reproduce, so ignore this patch until we found a real fix.

Thanks
Zou Nanhai


>>Also, this would impact render ring, not just BSD ring, right?
>>
>>> Signed-off-by: Wang Zhenyu <zhenyu.z.wang@intel.com>
>>> Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c
>>b/drivers/gpu/drm/i915/i915_irq.c
>>> index 22c8f66..0da9716 100644
>>> --- a/drivers/gpu/drm/i915/i915_irq.c
>>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>>> @@ -67,6 +67,11 @@ void
>>>  ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
>>>  {
>>>  	if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
>>> +		I915_WRITE(GTIIR, mask);
>>> +		(void) I915_READ(GTIIR);
>>> +		dev_priv->gt_irq_enable_reg |= mask;
>>> +		I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
>>> +		(void) I915_READ(GTIER);
>>>  		dev_priv->gt_irq_mask_reg &= ~mask;
>>>  		I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
>>>  		(void) I915_READ(GTIMR);
>>> @@ -77,9 +82,15 @@ void
>>>  ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
>>>  {
>>>  	if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
>>> +		dev_priv->gt_irq_enable_reg &= ~mask;
>>> +		I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
>>> +		(void) I915_READ(GTIER);
>>>  		dev_priv->gt_irq_mask_reg |= mask;
>>>  		I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
>>>  		(void) I915_READ(GTIMR);
>>> +		I915_WRITE(GTIIR, mask);
>>> +		(void) I915_READ(GTIIR);
>>> +
>>>  	}
>>>  }
>>>
>>> @@ -1283,7 +1294,7 @@ static int ironlake_irq_postinstall(struct drm_device
>>*dev)
>>>  	/* enable kind of interrupts always enabled */
>>>  	u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
>>>  			   DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
>>> -	u32 render_mask = GT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
>>> +	u32 render_mask = 0; /* enable nothing initially */
>>>  	u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
>>>  			   SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
>>>
>>Attachment: bsd_irq.patch (application/octet-stream)
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Patch 5/5] multiple ring buffer support, fix a irq enable logic for BSD

[Eric Anholt]

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On Mon, 19 Apr 2010 09:34:42 +0800, "Zou, Nanhai" <nanhai.zou@intel.com> wrote:
> >>-----Original Message-----
> >>From: Anholt, Eric
> >>Sent: 2010年4月13日 2:29
> >>To: Zou, Nanhai; intel-gfx@lists.freedesktop.org
> >>Subject: Re: [Intel-gfx] [Patch 5/5] multiple ring buffer support, fix a irq
> >>enable logic for BSD
> >>
> >>On Wed, 7 Apr 2010 14:28:39 +0800, "Zou, Nanhai" <nanhai.zou@intel.com> wrote:
> >>> Fix the BSD ring related IRQ logic on Ironlake.
> >>> Without this patch, we sometimes see IRQ lost
> >>> When playing H.264 content.
> >>
> >>This patch looks crazy.  Why do we need to do this?  How did you come up
> >>with it?  What prevents races between IIR clear and IER or IMR enable (if
> >>that's what the IIR clear is about).
> >>
> 
> Yes, it looks a little strange. 
> However HW spec from VCG do says IIR should be cleared before enable and disable interrupt.
> We thought this patch fixed the interrupt lost issue seen when playing movie. But now we found it just make the issue much harder to reproduce, so ignore this patch until we found a real fix.

Before enable, sure, that makes sense -- otherwise you'd trigger an
interrupt right away when you know you don't need it.  But we do
unmasking, not enabling.

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Re: [Patch 5/5] multiple ring buffer support, fix a irq enable logic for BSD

[Zou, Nanhai]

Hi Eric,
	I found the reason, 
Although user interrupt in BSD ring and Render ring has different represent
bit in GTIMR, they should share 1 usr_irq_lock, 
otherwise race condition may happen when 2 requests from different rings were submitted at the same time.
I have change the patches and cleanup write space issue and retarget to latest 
drm-intel-next 

please review

Thanks
Zou Nan hai


>>-----Original Message-----
>>From: Anholt, Eric
>>Sent: 2010年4月20日 1:25
>>To: Zou, Nanhai; intel-gfx@lists.freedesktop.org
>>Subject: Re: [Intel-gfx] [Patch 5/5] multiple ring buffer support, fix a irq
>>enable logic for BSD
>>
>>On Mon, 19 Apr 2010 09:34:42 +0800, "Zou, Nanhai" <nanhai.zou@intel.com> wrote:
>>> >>-----Original Message-----
>>> >>From: Anholt, Eric
>>> >>Sent: 2010年4月13日 2:29
>>> >>To: Zou, Nanhai; intel-gfx@lists.freedesktop.org
>>> >>Subject: Re: [Intel-gfx] [Patch 5/5] multiple ring buffer support, fix a
>>irq
>>> >>enable logic for BSD
>>> >>
>>> >>On Wed, 7 Apr 2010 14:28:39 +0800, "Zou, Nanhai" <nanhai.zou@intel.com>
>>wrote:
>>> >>> Fix the BSD ring related IRQ logic on Ironlake.
>>> >>> Without this patch, we sometimes see IRQ lost
>>> >>> When playing H.264 content.
>>> >>
>>> >>This patch looks crazy.  Why do we need to do this?  How did you come up
>>> >>with it?  What prevents races between IIR clear and IER or IMR enable (if
>>> >>that's what the IIR clear is about).
>>> >>
>>>
>>> Yes, it looks a little strange.
>>> However HW spec from VCG do says IIR should be cleared before enable and
>>disable interrupt.
>>> We thought this patch fixed the interrupt lost issue seen when playing movie.
>>But now we found it just make the issue much harder to reproduce, so ignore
>>this patch until we found a real fix.
>>
>>Before enable, sure, that makes sense -- otherwise you'd trigger an
>>interrupt right away when you know you don't need it.  But we do
>>unmasking, not enabling.
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