[linux-dovetail][PATCH 0/3] Add TSC function supports and MFD driver for TGPIO

[linux-dovetail][PATCH 0/3] Add TSC function supports and MFD driver for TGPIO

[Zqiang]

The following modifications are mainly to add TSC function for TGPIO
and add intel-ehl-gpio driver divides and initializes the PSE TGPIO
resources.

Christopher Hall (1):
  x86/tsc: Add TSC support functions to support ART driven Time-Aware
    GPIO

D, Lakshmi Sowjanya (1):
  ptp: tgpio: PSE TGPIO crosststamp, counttstamp

Raymond Tan (1):
  mfd: intel-ehl-gpio: Introduce MFD framework to PSE GPIO/TGPIO

 arch/x86/include/asm/tsc.h   |   8 ++
 arch/x86/kernel/tsc.c        | 168 +++++++++++++++++++++++-
 drivers/mfd/Kconfig          |  12 ++
 drivers/mfd/Makefile         |   1 +
 drivers/mfd/intel-ehl-gpio.c | 248 +++++++++++++++++++++++++++++++++++
 5 files changed, 435 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mfd/intel-ehl-gpio.c

-- 
2.25.1

[linux-dovetail][PATCH 1/3] x86/tsc: Add TSC support functions to support ART driven Time-Aware GPIO

[Zqiang]

From: Christopher Hall <christopher.s.hall@intel.com>

The PMC Time-Aware GPIO (TGPIO) logic is driven by ART. Several support
functions are required to translate ART to/from nanoseconds units which
is required by the PHC clock interface. A function is also added to get
the current value of ART/TSC using get_cycles() (RDTSC). This avoids
multiple MMIO reads required to retrieve ART.

Note that rather than ART nanoseconds, TSC nanoseconds are used. These are
related by TSC = ART * CPUID[15H].EBX/CPUID[15H].EAX + K. The value of
K is the distinction between between the ART and TSC nanoseconds.

The advantage of using TSC nanoseconds to represent the device clock
because it can easily be calculated in user-space using only CPUID[15H].
The value of ART in general can't be since K isn't necessarily known to
the application.

Signed-off-by: Christopher Hall <christopher.s.hall@intel.com>
Signed-off-by: Zqiang <qiang1.zhang@intel.com>
---
 arch/x86/include/asm/tsc.h |   6 ++
 arch/x86/kernel/tsc.c      | 116 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 120 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 01a300a9700b..721caa09a14d 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -30,6 +30,12 @@ static inline cycles_t get_cycles(void)
 
 extern struct system_counterval_t convert_art_to_tsc(u64 art);
 extern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns);
+extern struct timespec64 get_tsc_ns_now(struct system_counterval_t
+					*system_counter);
+extern u64 convert_tsc_ns_to_art(struct timespec64 *tsc_ns);
+extern u64 convert_tsc_ns_to_art_duration(struct timespec64 *tsc_ns);
+extern struct timespec64 convert_art_to_tsc_ns(u64 art);
+extern struct timespec64 convert_art_to_tsc_ns_duration(u64 art);
 
 extern void tsc_early_init(void);
 extern void tsc_init(void);
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 9eae730d8b44..c4b48323c4bf 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1260,7 +1260,7 @@ int unsynchronized_tsc(void)
 /*
  * Convert ART to TSC given numerator/denominator found in detect_art()
  */
-struct system_counterval_t convert_art_to_tsc(u64 art)
+static struct system_counterval_t _convert_art_to_tsc(u64 art, bool dur)
 {
 	u64 tmp, res, rem;
 
@@ -1270,13 +1270,125 @@ struct system_counterval_t convert_art_to_tsc(u64 art)
 	tmp = rem * art_to_tsc_numerator;
 
 	do_div(tmp, art_to_tsc_denominator);
-	res += tmp + art_to_tsc_offset;
+	res += tmp;
+	if (!dur)
+		res += art_to_tsc_offset;
 
 	return (struct system_counterval_t) {.cs = art_related_clocksource,
 			.cycles = res};
 }
+
+struct system_counterval_t convert_art_to_tsc(u64 art)
+{
+	return _convert_art_to_tsc(art, false);
+}
 EXPORT_SYMBOL(convert_art_to_tsc);
 
+static
+struct timespec64 get_tsc_ns(struct system_counterval_t *system_counter)
+{
+	u64 tmp, res, rem;
+	u64 cycles;
+
+	cycles = system_counter->cycles;
+	rem = do_div(cycles, tsc_khz);
+
+	res = cycles * USEC_PER_SEC;
+	tmp = rem * USEC_PER_SEC;
+
+	rem = do_div(tmp, tsc_khz);
+	tmp += rem > tsc_khz >> 2 ? 1 : 0;
+	res += tmp;
+
+	rem = do_div(res, NSEC_PER_SEC);
+
+	return (struct timespec64) {.tv_sec = res, .tv_nsec = rem};
+}
+
+struct timespec64 get_tsc_ns_now(struct system_counterval_t *system_counter)
+{
+	struct system_counterval_t counterval;
+
+	if (system_counter == NULL)
+		system_counter = &counterval;
+
+	system_counter->cycles = clocksource_tsc.read(NULL);
+	system_counter->cs = art_related_clocksource;
+
+	return get_tsc_ns(system_counter);
+}
+EXPORT_SYMBOL(get_tsc_ns_now);
+
+struct timespec64 convert_art_to_tsc_ns(u64 art)
+{
+	struct system_counterval_t counterval;
+
+	counterval = _convert_art_to_tsc(art, false);
+
+	return get_tsc_ns(&counterval);
+}
+EXPORT_SYMBOL(convert_art_to_tsc_ns);
+
+struct timespec64 convert_art_to_tsc_ns_duration(u64 art)
+{
+	struct system_counterval_t counterval;
+
+	counterval = _convert_art_to_tsc(art, true);
+
+	return get_tsc_ns(&counterval);
+}
+EXPORT_SYMBOL(convert_art_to_tsc_ns_duration);
+
+static u64 convert_tsc_ns_to_tsc(struct timespec64 *tsc_ns)
+{
+	u64 tmp, res, rem;
+	u64 cycles;
+
+	cycles = timespec64_to_ns(tsc_ns);
+
+	rem = do_div(cycles, USEC_PER_SEC);
+
+	res = cycles * tsc_khz;
+	tmp = rem * tsc_khz;
+
+	do_div(tmp, USEC_PER_SEC);
+
+	return res + tmp;
+}
+
+
+static u64 _convert_tsc_ns_to_art(struct timespec64 *tsc_ns, bool dur)
+{
+	u64 tmp, res, rem;
+	u64 cycles;
+
+	cycles = convert_tsc_ns_to_tsc(tsc_ns);
+	if (!dur)
+		cycles -= art_to_tsc_offset;
+
+	rem = do_div(cycles, art_to_tsc_numerator);
+
+	res = cycles * art_to_tsc_denominator;
+	tmp = rem * art_to_tsc_denominator;
+
+	rem = do_div(tmp, art_to_tsc_numerator);
+	tmp += rem > art_to_tsc_numerator >> 2 ? 1 : 0;
+
+	return res + tmp;
+}
+
+u64 convert_tsc_ns_to_art(struct timespec64 *tsc_ns)
+{
+	return _convert_tsc_ns_to_art(tsc_ns, false);
+}
+EXPORT_SYMBOL(convert_tsc_ns_to_art);
+
+u64 convert_tsc_ns_to_art_duration(struct timespec64 *tsc_ns)
+{
+	return _convert_tsc_ns_to_art(tsc_ns, true);
+}
+EXPORT_SYMBOL(convert_tsc_ns_to_art_duration);
+
 /**
  * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC.
  * @art_ns: ART (Always Running Timer) in unit of nanoseconds
-- 
2.25.1

[linux-dovetail][PATCH 2/3] ptp: tgpio: PSE TGPIO crosststamp, counttstamp

[Zqiang]

From: "D, Lakshmi Sowjanya" <lakshmi.sowjanya.d@intel.com>

Driver gets the art time from get_art() function for PSE TGPIO crosststamp.
Counttstamp implementation for PSE TGPIO.

Signed-off-by: D, Lakshmi Sowjanya <lakshmi.sowjanya.d@intel.com>
Signed-off-by: Zqiang <qiang1.zhang@intel.com>
---
 arch/x86/include/asm/tsc.h |  2 ++
 arch/x86/kernel/tsc.c      | 52 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 721caa09a14d..a480a76b47c3 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -32,6 +32,8 @@ extern struct system_counterval_t convert_art_to_tsc(u64 art);
 extern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns);
 extern struct timespec64 get_tsc_ns_now(struct system_counterval_t
 					*system_counter);
+extern int convert_tsc_to_art(const struct system_counterval_t *tsc, u64 *art);
+extern u64 read_art(void);
 extern u64 convert_tsc_ns_to_art(struct timespec64 *tsc_ns);
 extern u64 convert_tsc_ns_to_art_duration(struct timespec64 *tsc_ns);
 extern struct timespec64 convert_art_to_tsc_ns(u64 art);
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index c4b48323c4bf..0afbdbf5d394 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1257,6 +1257,58 @@ int unsynchronized_tsc(void)
 	return 0;
 }
 
+/**
+ * convert_tsc_to_art() - Returns ART value associated with system counter
+ *
+ * Converts input TSC to the corresponding ART value using conversion
+ * factors discovered by detect_art()
+ *
+ * Return:
+ * u64 ART value
+ */
+int convert_tsc_to_art(
+        const struct system_counterval_t *system_counter, u64 *art)
+{
+	u64 tmp, res, rem;
+
+	if (system_counter->cs != art_related_clocksource)
+		return -EINVAL;
+
+	res = system_counter->cycles - art_to_tsc_offset;
+	rem = do_div(res, art_to_tsc_numerator);
+
+	*art = res * art_to_tsc_denominator;
+	tmp = rem * art_to_tsc_denominator;
+
+	do_div(tmp, art_to_tsc_numerator);
+	*art += tmp;
+
+	return 0;
+}
+EXPORT_SYMBOL(convert_tsc_to_art);
+
+/**
+ * read_art() - Returns current ART value
+ *
+ * Converts the current TSC to the current ART value using conversion
+ * factors discovered by detect_art()
+ *
+ * Return:
+ * u64 ART value
+ */
+u64 read_art(void)
+{
+	struct system_counterval_t tsc;
+	u64 art = 0;
+
+	tsc.cs = art_related_clocksource;
+	tsc.cycles = read_tsc(NULL);
+	convert_tsc_to_art(&tsc, &art);
+
+	return art;
+}
+EXPORT_SYMBOL(read_art);
+
 /*
  * Convert ART to TSC given numerator/denominator found in detect_art()
  */
-- 
2.25.1

[linux-dovetail][PATCH 3/3] mfd: intel-ehl-gpio: Introduce MFD framework to PSE GPIO/TGPIO

[Zqiang]

From: Raymond Tan <raymond.tan@intel.com>

In Elkhart Lake, the PSE GPIO and TGPIO shares the PCI device,
albeit being accessed at different MMIO BAR offset. Thus, to properly
register device drivers and enable support of both functionalities,
we choose Linux MFD framework.

1) intel-ehl-gpio - probe base on the PCI device, and split the resources
2) ptp-intel-tgpio-plat - platform driver which will register support of
PSE TGPIO (20 pins max per device)

Note: BIOS configuration is required to properly assign the pin-mux.
Note: PSE TGPIO driver is based on Balbi Felipe's original driver.
Note: PSE GPIO driver is based on Pandith N's original driver.

Signed-off-by: N Pandith <pandith.n@intel.com>
Signed-off-by: Raymond Tan <raymond.tan@intel.com>
Signed-off-by: Zqiang <qiang1.zhang@intel.com>
---
 drivers/mfd/Kconfig          |  12 ++
 drivers/mfd/Makefile         |   1 +
 drivers/mfd/intel-ehl-gpio.c | 248 +++++++++++++++++++++++++++++++++++
 3 files changed, 261 insertions(+)
 create mode 100644 drivers/mfd/intel-ehl-gpio.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index b8847ae04d93..c36b35100ead 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -2168,5 +2168,17 @@ config MFD_INTEL_M10_BMC
 	  additional drivers must be enabled in order to use the functionality
 	  of the device.
 
+config MFD_INTEL_EHL_PSE_GPIO
+	tristate "Intel Elkhart Lake PSE GPIO MFD"
+	depends on PCI
+	depends on X86
+	select MFD_CORE
+	help
+	  This MFD provides support for GPIO and TGPIO that exist only
+	  in a signle PCI device.
+
+	  IT splits the 2 IO devices to their
+	  respective drivers.
+
 endmenu
 endif
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 1780019d2474..5f7912391237 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -267,3 +267,4 @@ obj-$(CONFIG_MFD_KHADAS_MCU) 	+= khadas-mcu.o
 obj-$(CONFIG_SGI_MFD_IOC3)	+= ioc3.o
 obj-$(CONFIG_MFD_SIMPLE_MFD_I2C)	+= simple-mfd-i2c.o
 obj-$(CONFIG_MFD_INTEL_M10_BMC)   += intel-m10-bmc.o
+obj-$(CONFIG_MFD_INTEL_EHL_PSE_GPIO)    += intel-ehl-gpio.o
diff --git a/drivers/mfd/intel-ehl-gpio.c b/drivers/mfd/intel-ehl-gpio.c
new file mode 100644
index 000000000000..9db5601ab39c
--- /dev/null
+++ b/drivers/mfd/intel-ehl-gpio.c
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Multi-Functional Driver driver for Elkhart Lake
+ * Programmable Service Engine (PSE) GPIO & TGPIO Functions
+ *
+ * Copyright(c) 2020 Intel Corporation.
+ *
+ * Intel Elkhart Lake PSE has 2 PCI devices which exposes 2 different
+ * functions of GPIO and Timed-GPIO based on the BIOS configurations
+ * and exposes the programmability through different offset from the
+ * MMIO BAR of the PCI device.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/device.h>
+#include <linux/mfd/core.h>
+#include <linux/pm_runtime.h>
+
+#define PSE_GPIO_OFFSET		0x0000
+#define PSE_TGPIO_OFFSET	0x1000
+#define PSE_PRIV_OFFSET		0x2000
+#define PSE_GPIO_SIZE		0x134
+#define PSE_TGPIO_SIZE		0x6B0
+#define PSE_PRIV_SIZE		0x8
+
+#define PSE_GPIO_D0I3C		1000
+#define PSE_GPIO_CGSR		1004
+#define PSE_GPIO_D0I3_CIP	BIT(0)
+#define PSE_GPIO_D0I3_IR	BIT(1)
+#define PSE_GPIO_D0I3_EN	BIT(2)
+#define PSE_GPIO_D0I3_RR	BIT(3)
+#define PSE_GPIO_CGSR_CG	BIT(16)
+
+static struct resource intel_ehl_pse_gpio_resources[] = {
+	DEFINE_RES_MEM(PSE_GPIO_OFFSET, PSE_GPIO_SIZE),
+	DEFINE_RES_IRQ(0),
+};
+
+static struct resource intel_ehl_pse_tgpio_resources[] = {
+	DEFINE_RES_MEM(PSE_TGPIO_OFFSET, PSE_TGPIO_SIZE),
+	DEFINE_RES_IRQ(1),
+};
+
+struct intel_ehl_pse_gpio_data {
+	struct resource *mem;
+	int irq;
+	struct device *dev;
+	void __iomem *priv;
+};
+
+struct intel_ehl_pse_gpio_priv {
+	const struct intel_ehl_pse_gpio_data *info; // array for gpio & tgpio
+
+	struct mfd_cell *cell; // array for gpio & tgpio
+};
+
+static struct mfd_cell intel_ehl_pse_gpio_mfd_devs[] = {
+	{
+		.name = "gpio-ehl-pse",
+		.num_resources = ARRAY_SIZE(intel_ehl_pse_gpio_resources),
+		.resources = intel_ehl_pse_gpio_resources,
+		.ignore_resource_conflicts = true,
+	},
+	{
+		.name = "intel-ehl-tgpio",
+		.num_resources = ARRAY_SIZE(intel_ehl_pse_tgpio_resources),
+		.resources = intel_ehl_pse_tgpio_resources,
+		.ignore_resource_conflicts = true,
+	},
+};
+
+
+static int intel_ehl_pse_gpio_mfd_probe(struct pci_dev *pci,
+					const struct pci_device_id *id)
+{
+	int ret;
+	struct intel_ehl_pse_gpio_data *pdata;
+
+	pdata = devm_kzalloc(&pci->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	ret = pcim_enable_device(pci);
+	if (ret)
+		return ret;
+
+	pci_set_master(pci);
+
+	ret = pci_alloc_irq_vectors(pci, 2, 2, PCI_IRQ_ALL_TYPES);
+	if (ret < 0)
+		return ret;
+
+	pdata->irq = pci_irq_vector(pci, 0);
+	pdata->mem = &pci->resource[0];
+
+	pdata->priv = devm_ioremap(&pci->dev, pdata->mem->start +
+			PSE_PRIV_OFFSET, PSE_PRIV_SIZE);
+	if (!pdata->priv)
+		return -ENOMEM;
+
+	pci_set_drvdata(pci, pdata);
+
+	ret = mfd_add_devices(&pci->dev, PLATFORM_DEVID_AUTO,
+			intel_ehl_pse_gpio_mfd_devs,
+			ARRAY_SIZE(intel_ehl_pse_gpio_mfd_devs),
+			pdata->mem, pdata->irq, NULL);
+
+	pm_runtime_set_autosuspend_delay(&pci->dev, 1000);
+	pm_runtime_use_autosuspend(&pci->dev);
+	pm_runtime_put_autosuspend(&pci->dev);
+	pm_runtime_allow(&pci->dev);
+
+	return 0;
+}
+
+static void intel_ehl_pse_gpio_mfd_remove(struct pci_dev *pci)
+{
+	pm_runtime_forbid(&pci->dev);
+	pm_runtime_get_noresume(&pci->dev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int intel_ehl_pse_gpio_mfd_suspend(struct device *dev)
+{
+	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
+	struct intel_ehl_pse_gpio_data	*pdata = pci_get_drvdata(pdev);
+	u32 d0i3c_reg, cgsr_reg = 0;
+
+	d0i3c_reg = readl(pdata->priv + PSE_GPIO_D0I3C);
+	cgsr_reg = readl(pdata->priv + PSE_GPIO_CGSR);
+
+	/* enable D0i3 BIT(2) & disable interrupt BIT(1)*/
+	d0i3c_reg |= PSE_GPIO_D0I3_EN;
+	d0i3c_reg &= ~PSE_GPIO_D0I3_IR;
+
+	/* enable clock gating BIT(16)*/
+	cgsr_reg |= PSE_GPIO_CGSR_CG;
+
+	writel(d0i3c_reg, pdata->priv + PSE_GPIO_D0I3C);
+	writel(cgsr_reg, pdata->priv + PSE_GPIO_CGSR);
+
+	return 0;
+}
+
+static int intel_ehl_pse_gpio_mfd_resume(struct device *dev)
+{
+	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
+	struct intel_ehl_pse_gpio_data	*pdata = pci_get_drvdata(pdev);
+	struct timespec64 *ts;
+	u32 d0i3c_reg, cgsr_reg = 0;
+
+	ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL);
+
+	d0i3c_reg = readl(pdata->priv + PSE_GPIO_D0I3C);
+	cgsr_reg = readl(pdata->priv + PSE_GPIO_CGSR);
+
+	/* disable D0i3 BIT(2) & disable interrupt BIT(1)*/
+	d0i3c_reg &= ~(PSE_GPIO_D0I3_IR | PSE_GPIO_D0I3_EN);
+
+	/* disable clock gating BIT(16)*/
+	cgsr_reg &= ~PSE_GPIO_CGSR_CG;
+
+	writel(d0i3c_reg, pdata->priv + PSE_GPIO_D0I3C);
+	writel(cgsr_reg, pdata->priv + PSE_GPIO_CGSR);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_PM
+static int intel_ehl_pse_gpio_mfd_runtime_suspend(struct device *dev)
+{
+	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
+	struct intel_ehl_pse_gpio_data	*pdata = pci_get_drvdata(pdev);
+	u32 d0i3c_reg, cgsr_reg = 0;
+
+	d0i3c_reg = readl(pdata->priv + PSE_GPIO_D0I3C);
+	cgsr_reg = readl(pdata->priv + PSE_GPIO_CGSR);
+
+	/* enable D0i3 BIT(2) & disable interrupt BIT(1)*/
+	d0i3c_reg |= PSE_GPIO_D0I3_EN;
+	d0i3c_reg &= ~PSE_GPIO_D0I3_IR;
+
+	/* enable clock gating BIT(16)*/
+	cgsr_reg |= PSE_GPIO_CGSR_CG;
+
+	writel(d0i3c_reg, pdata->priv + PSE_GPIO_D0I3C);
+	writel(cgsr_reg, pdata->priv + PSE_GPIO_CGSR);
+
+	return 0;
+}
+
+static int intel_ehl_pse_gpio_mfd_runtime_resume(struct device *dev)
+{
+	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
+	struct intel_ehl_pse_gpio_data	*pdata = pci_get_drvdata(pdev);
+	struct timespec64 *ts;
+	u32 d0i3c_reg, cgsr_reg = 0;
+
+	ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL);
+
+	d0i3c_reg = readl(pdata->priv + PSE_GPIO_D0I3C);
+	cgsr_reg = readl(pdata->priv + PSE_GPIO_CGSR);
+
+	/* disable D0i3 BIT(2) & disable interrupt BIT(1)*/
+	d0i3c_reg &= ~(PSE_GPIO_D0I3_IR | PSE_GPIO_D0I3_EN);
+
+	/* disable clock gating BIT(16)*/
+	cgsr_reg &= ~PSE_GPIO_CGSR_CG;
+
+	writel(d0i3c_reg, pdata->priv + PSE_GPIO_D0I3C);
+	writel(cgsr_reg, pdata->priv + PSE_GPIO_CGSR);
+
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops intel_ehl_pse_gpio_mfd_pm_ops = {
+	SET_RUNTIME_PM_OPS(intel_ehl_pse_gpio_mfd_runtime_suspend,
+			intel_ehl_pse_gpio_mfd_runtime_resume, NULL)
+	SET_SYSTEM_SLEEP_PM_OPS(intel_ehl_pse_gpio_mfd_suspend,
+			intel_ehl_pse_gpio_mfd_resume)
+};
+
+static const struct pci_device_id intel_ehl_pse_gpio_mfd_ids[] = {
+	{ PCI_VDEVICE(INTEL, 0x4b88), },
+	{ PCI_VDEVICE(INTEL, 0x4b89), },
+	{ },
+};
+MODULE_DEVICE_TABLE(pci, intel_ehl_pse_gpio_mfd_ids);
+
+static struct pci_driver intel_ehl_pse_gpio_mfd_driver = {
+	.name		= "intel_ehl_pse_gpio_mfd",
+	.id_table	= intel_ehl_pse_gpio_mfd_ids,
+	.probe		= intel_ehl_pse_gpio_mfd_probe,
+	.remove		= intel_ehl_pse_gpio_mfd_remove,
+	.driver = {
+		.pm = &intel_ehl_pse_gpio_mfd_pm_ops,
+	},
+};
+
+module_pci_driver(intel_ehl_pse_gpio_mfd_driver);
+
+MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
+MODULE_DESCRIPTION("Intel MFD Driver for Elkhart Lake PSE TGPIO/GPIO");
+MODULE_LICENSE("GPL v2");
-- 
2.25.1

Re: [linux-dovetail][PATCH 0/3] Add TSC function supports and MFD driver for TGPIO

[Bezdeka, Florian]

On Tue, 2022-05-17 at 09:53 +0800, Zqiang via Xenomai wrote:
> The following modifications are mainly to add TSC function for TGPIO
> and add intel-ehl-gpio driver divides and initializes the PSE TGPIO
> resources.
> 
> Christopher Hall (1):
>   x86/tsc: Add TSC support functions to support ART driven Time-Aware
>     GPIO
> 
> D, Lakshmi Sowjanya (1):
>   ptp: tgpio: PSE TGPIO crosststamp, counttstamp
> 
> Raymond Tan (1):
>   mfd: intel-ehl-gpio: Introduce MFD framework to PSE GPIO/TGPIO

I haven't looked at the details yet and I missed the Community meeting
today where this topic might have been discussed.

I'm asking myself if the dovetail tree is the right tree to take those
patches. Have these patches already been sent to upstream / Linux? If
so, we should fetch them within the next rebase cycle, right?

If not: I feel we shouldn't apply them here and follow the "upstream
first" approach.

Best regards,
Florian

> 
>  arch/x86/include/asm/tsc.h   |   8 ++
>  arch/x86/kernel/tsc.c        | 168 +++++++++++++++++++++++-
>  drivers/mfd/Kconfig          |  12 ++
>  drivers/mfd/Makefile         |   1 +
>  drivers/mfd/intel-ehl-gpio.c | 248 +++++++++++++++++++++++++++++++++++
>  5 files changed, 435 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/mfd/intel-ehl-gpio.c
> 

Re: [linux-dovetail][PATCH 0/3] Add TSC function supports and MFD driver for TGPIO

[Jan Kiszka]

On 18.05.22 19:45, Bezdeka, Florian (T CED SES-DE) wrote:
> On Tue, 2022-05-17 at 09:53 +0800, Zqiang via Xenomai wrote:
>> The following modifications are mainly to add TSC function for TGPIO
>> and add intel-ehl-gpio driver divides and initializes the PSE TGPIO
>> resources.
>>
>> Christopher Hall (1):
>>   x86/tsc: Add TSC support functions to support ART driven Time-Aware
>>     GPIO
>>
>> D, Lakshmi Sowjanya (1):
>>   ptp: tgpio: PSE TGPIO crosststamp, counttstamp
>>
>> Raymond Tan (1):
>>   mfd: intel-ehl-gpio: Introduce MFD framework to PSE GPIO/TGPIO
> 
> I haven't looked at the details yet and I missed the Community meeting
> today where this topic might have been discussed.
> 
> I'm asking myself if the dovetail tree is the right tree to take those
> patches. Have these patches already been sent to upstream / Linux? If
> so, we should fetch them within the next rebase cycle, right?
> 
> If not: I feel we shouldn't apply them here and follow the "upstream
> first" approach.

Yup, those should be confirmed upstream first. I'm not seeing them in
Linus' tree yet, or anything related. I thought EHL upstreaming was
completed by now?

Once they are confirmed, backporting accepted patches to certain stable
trees is much safer than having to change APIs again once that feature
hits upstream later.

Jan

-- 
Siemens AG, Technology
Competence Center Embedded Linux

Re: [linux-dovetail][PATCH 0/3] Add TSC function supports and MFD driver for TGPIO

[Philippe Gerum]

"Bezdeka, Florian" <florian.bezdeka@siemens.com> writes:

> On Tue, 2022-05-17 at 09:53 +0800, Zqiang via Xenomai wrote:
>> The following modifications are mainly to add TSC function for TGPIO
>> and add intel-ehl-gpio driver divides and initializes the PSE TGPIO
>> resources.
>> 
>> Christopher Hall (1):
>>   x86/tsc: Add TSC support functions to support ART driven Time-Aware
>>     GPIO
>> 
>> D, Lakshmi Sowjanya (1):
>>   ptp: tgpio: PSE TGPIO crosststamp, counttstamp
>> 
>> Raymond Tan (1):
>>   mfd: intel-ehl-gpio: Introduce MFD framework to PSE GPIO/TGPIO
>
> I haven't looked at the details yet and I missed the Community meeting
> today where this topic might have been discussed.
>
> I'm asking myself if the dovetail tree is the right tree to take those
> patches. Have these patches already been sent to upstream / Linux? If
> so, we should fetch them within the next rebase cycle, right?
>
> If not: I feel we shouldn't apply them here and follow the "upstream
> first" approach.
>

Agreed.

-- 
Philippe.