[Intel-gfx] [PATCH] drm/i915: Fix indirect context size calculation

[Intel-gfx] [PATCH] drm/i915: Fix indirect context size calculation

[Mika Kuoppala]

Hardware needs cacheline count for indirect context size.
Count of zero means that the feature is disabled.
If we only divide size with cacheline bytes, we get
one cacheline short of execution.

Divide by rounding up to a cacheline size so that
hardware executes everything intended.

Bspec: 11739
Fixes: 17ee950df38b ("drm/i915/gen8: Add infrastructure to initialize WA batch buffers")
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6fbad5e2343f..acbb36ad17ff 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4739,7 +4739,8 @@ static void init_wa_bb_reg_state(u32 * const regs,
 
 		regs[pos_bb_per_ctx + 2] =
 			(ggtt_offset + wa_ctx->indirect_ctx.offset) |
-			(wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
+			DIV_ROUND_UP(wa_ctx->indirect_ctx.size,
+				     CACHELINE_BYTES);
 
 		regs[pos_bb_per_ctx + 4] =
 			intel_lr_indirect_ctx_offset(engine) << 6;
-- 
2.17.1

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Re: [Intel-gfx] [PATCH] drm/i915: Fix indirect context size calculation

[Mika Kuoppala]

Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:

> Hardware needs cacheline count for indirect context size.
> Count of zero means that the feature is disabled.
> If we only divide size with cacheline bytes, we get
> one cacheline short of execution.
>
> Divide by rounding up to a cacheline size so that
> hardware executes everything intended.
>
> Bspec: 11739
> Fixes: 17ee950df38b ("drm/i915/gen8: Add infrastructure to initialize WA batch buffers")
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 6fbad5e2343f..acbb36ad17ff 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -4739,7 +4739,8 @@ static void init_wa_bb_reg_state(u32 * const regs,
>  
>  		regs[pos_bb_per_ctx + 2] =
>  			(ggtt_offset + wa_ctx->indirect_ctx.offset) |
> -			(wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
> +			DIV_ROUND_UP(wa_ctx->indirect_ctx.size,
> +				     CACHELINE_BYTES);

The aligment to cacheline is checked on the emitting phase.

This patch can be ignored.
-Mika


>  
>  		regs[pos_bb_per_ctx + 4] =
>  			intel_lr_indirect_ctx_offset(engine) << 6;
> -- 
> 2.17.1
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Re: [Intel-gfx] [PATCH] drm/i915: Fix indirect context size calculation

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-14 13:20:00)
> Hardware needs cacheline count for indirect context size.
> Count of zero means that the feature is disabled.
> If we only divide size with cacheline bytes, we get
> one cacheline short of execution.

I thought we only emitted cacheline chunks by design?

I see us checking for
GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES)))
so what's the reason? I expect that's in the next patch.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Fix indirect context size calculation

[Chris Wilson]

Quoting Mika Kuoppala (2020-04-14 14:51:32)
> Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:
> 
> > Hardware needs cacheline count for indirect context size.
> > Count of zero means that the feature is disabled.
> > If we only divide size with cacheline bytes, we get
> > one cacheline short of execution.
> >
> > Divide by rounding up to a cacheline size so that
> > hardware executes everything intended.
> >
> > Bspec: 11739
> > Fixes: 17ee950df38b ("drm/i915/gen8: Add infrastructure to initialize WA batch buffers")
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index 6fbad5e2343f..acbb36ad17ff 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -4739,7 +4739,8 @@ static void init_wa_bb_reg_state(u32 * const regs,
> >  
> >               regs[pos_bb_per_ctx + 2] =
> >                       (ggtt_offset + wa_ctx->indirect_ctx.offset) |
> > -                     (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
> > +                     DIV_ROUND_UP(wa_ctx->indirect_ctx.size,
> > +                                  CACHELINE_BYTES);
> 
> The aligment to cacheline is checked on the emitting phase.

My headache is screwing with my latency. I see I am superfluous and
should just call it a day.
-Chris
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Fix indirect context size calculation

[Patchwork]

== Series Details ==

Series: drm/i915: Fix indirect context size calculation
URL   : https://patchwork.freedesktop.org/series/75916/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix indirect context size calculation

[Patchwork]

== Series Details ==

Series: drm/i915: Fix indirect context size calculation
URL   : https://patchwork.freedesktop.org/series/75916/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8298 -> Patchwork_17294
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17294/index.html

Known issues
------------

  Here are the changes found in Patchwork_17294 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_chamelium@dp-crc-fast:
    - fi-icl-u2:          [PASS][1] -> [FAIL][2] ([i915#262])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8298/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17294/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html

  
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262


Participating hosts (48 -> 43)
------------------------------

  Missing    (5): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8298 -> Patchwork_17294

  CI-20190529: 20190529
  CI_DRM_8298: 17f82f0c2857d0b442adbdb62eb44b61d0f5b775 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5589: 31962324ac86f029e2841e56e97c42cf9d572956 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17294: 098eb3c86877f4db93ddb01876f0e4479c3782d9 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

098eb3c86877 drm/i915: Fix indirect context size calculation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17294/index.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix indirect context size calculation

[Patchwork]

== Series Details ==

Series: drm/i915: Fix indirect context size calculation
URL   : https://patchwork.freedesktop.org/series/75916/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17294_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_17294_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_17294_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  


Changes
-------

  No changes found


Participating hosts (10 -> 2)
------------------------------

  ERROR: It appears as if the changes made in Patchwork_17294_full prevented too many machines from booting.

  Missing    (8): shard-skl shard-tglb shard-iclb shard-apl shard-glk shard-hsw shard-kbl shard-snb 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5589 -> None
  * Linux: CI_DRM_8298 -> Patchwork_17294

  CI-20190529: 20190529
  CI_DRM_8298: 17f82f0c2857d0b442adbdb62eb44b61d0f5b775 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5589: 31962324ac86f029e2841e56e97c42cf9d572956 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17294: 098eb3c86877f4db93ddb01876f0e4479c3782d9 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17294/index.html
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