From: Thomas Gleixner <tglx@linutronix.de>
To: Samuel Holland <samuel.holland@sifive.com>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Anup Patel <apatel@ventanamicro.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>
Subject: Re: [PATCH v1 0/9] Fix Allwinner D1 boot regression
Date: Thu, 15 Aug 2024 16:11:14 +0200 [thread overview]
Message-ID: <87h6blnaf1.ffs@tglx> (raw)
In-Reply-To: <686d61c4-e7ac-4dca-a7fd-decdd72e84d9@sifive.com>
On Thu, Aug 15 2024 at 08:32, Samuel Holland wrote:
> On 2024-08-15 8:16 AM, Thomas Gleixner wrote:
>> Yes. So the riscv timer is not working on this thing or it stops
>> somehow.
>
> That's correct. With the (firmware) devicetree that Emil is using, the OpenSBI
> firmware does not have a timer device, so it does not expose the (optional[1])
> SBI time extension, and sbi_set_timer() does nothing.
Sigh. Does RISCV really have to repeat all mistakes which have been made
by x86, ARM and others before? It's known for decades that the kernel
relies on a working timer...
> I wrote a patch (not submitted) to skip registering riscv_clock_event when the
> SBI time extension is unavailable, but this doesn't fully solve the issue
> either, because then we have no clockevent at all when
> check_unaligned_access_all_cpus() is called.
check_unaligned_access_all_cpus() is irrelevant.
> How early in the boot process are we "required" to have a functional clockevent?
> Do we need to refactor check_unaligned_access_all_cpus() so it works on systems
> where the only clockevent is provided by a platform device?
Right after init/main::late_time_init() everything can depend on a
working timer and on jiffies increasing.
I'm actually surprised that the boot process gets that far. That's just
by pure luck, really.
Thanks,
tglx
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WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: Samuel Holland <samuel.holland@sifive.com>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Anup Patel <apatel@ventanamicro.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>
Subject: Re: [PATCH v1 0/9] Fix Allwinner D1 boot regression
Date: Thu, 15 Aug 2024 16:11:14 +0200 [thread overview]
Message-ID: <87h6blnaf1.ffs@tglx> (raw)
In-Reply-To: <686d61c4-e7ac-4dca-a7fd-decdd72e84d9@sifive.com>
On Thu, Aug 15 2024 at 08:32, Samuel Holland wrote:
> On 2024-08-15 8:16 AM, Thomas Gleixner wrote:
>> Yes. So the riscv timer is not working on this thing or it stops
>> somehow.
>
> That's correct. With the (firmware) devicetree that Emil is using, the OpenSBI
> firmware does not have a timer device, so it does not expose the (optional[1])
> SBI time extension, and sbi_set_timer() does nothing.
Sigh. Does RISCV really have to repeat all mistakes which have been made
by x86, ARM and others before? It's known for decades that the kernel
relies on a working timer...
> I wrote a patch (not submitted) to skip registering riscv_clock_event when the
> SBI time extension is unavailable, but this doesn't fully solve the issue
> either, because then we have no clockevent at all when
> check_unaligned_access_all_cpus() is called.
check_unaligned_access_all_cpus() is irrelevant.
> How early in the boot process are we "required" to have a functional clockevent?
> Do we need to refactor check_unaligned_access_all_cpus() so it works on systems
> where the only clockevent is provided by a platform device?
Right after init/main::late_time_init() everything can depend on a
working timer and on jiffies increasing.
I'm actually surprised that the boot process gets that far. That's just
by pure luck, really.
Thanks,
tglx
next prev parent reply other threads:[~2024-08-15 14:11 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-14 14:56 [PATCH v1 0/9] Fix Allwinner D1 boot regression Emil Renner Berthing
2024-08-14 14:56 ` Emil Renner Berthing
2024-08-14 14:56 ` [PATCH v1 1/9] Revert "irqchip/sifive-plic: Chain to parent IRQ after handlers are ready" Emil Renner Berthing
2024-08-14 14:56 ` Emil Renner Berthing
2024-08-14 14:56 ` [PATCH v1 2/9] Revert "irqchip/sifive-plic: Avoid explicit cpumask allocation on stack" Emil Renner Berthing
2024-08-14 14:56 ` Emil Renner Berthing
2024-08-14 14:56 ` [PATCH v1 3/9] Revert "irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore" Emil Renner Berthing
2024-08-14 14:56 ` Emil Renner Berthing
2024-08-14 14:56 ` [PATCH v1 4/9] Revert "irqchip/sifive-plic: Parse number of interrupts and contexts early in plic_probe()" Emil Renner Berthing
2024-08-14 14:56 ` Emil Renner Berthing
2024-08-14 14:56 ` [PATCH v1 5/9] Revert "irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failure" Emil Renner Berthing
2024-08-14 14:56 ` Emil Renner Berthing
2024-08-14 14:56 ` [PATCH v1 6/9] Revert "irqchip/sifive-plic: Use riscv_get_intc_hwnode() to get parent fwnode" Emil Renner Berthing
2024-08-14 14:56 ` Emil Renner Berthing
2024-08-14 14:56 ` [PATCH v1 7/9] Revert "irqchip/sifive-plic: Use devm_xyz() for managed allocation" Emil Renner Berthing
2024-08-14 14:56 ` Emil Renner Berthing
2024-08-14 14:56 ` [PATCH v1 8/9] Revert "irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz()" Emil Renner Berthing
2024-08-14 14:56 ` Emil Renner Berthing
2024-08-14 14:56 ` [PATCH v1 9/9] Revert "irqchip/sifive-plic: Convert PLIC driver into a platform driver" Emil Renner Berthing
2024-08-14 14:56 ` Emil Renner Berthing
2024-08-14 17:30 ` [PATCH v1 0/9] Fix Allwinner D1 boot regression Thomas Gleixner
2024-08-14 17:30 ` Thomas Gleixner
2024-08-15 10:29 ` Emil Renner Berthing
2024-08-15 10:29 ` Emil Renner Berthing
2024-08-15 11:44 ` Thomas Gleixner
2024-08-15 11:44 ` Thomas Gleixner
2024-08-15 12:04 ` Emil Renner Berthing
2024-08-15 12:04 ` Emil Renner Berthing
2024-08-15 12:14 ` Emil Renner Berthing
2024-08-15 12:14 ` Emil Renner Berthing
2024-08-15 13:16 ` Thomas Gleixner
2024-08-15 13:16 ` Thomas Gleixner
2024-08-15 13:32 ` Samuel Holland
2024-08-15 13:32 ` Samuel Holland
2024-08-15 14:11 ` Thomas Gleixner [this message]
2024-08-15 14:11 ` Thomas Gleixner
2024-08-15 14:16 ` Anup Patel
2024-08-15 14:16 ` Anup Patel
2024-08-15 14:41 ` Samuel Holland
2024-08-15 14:41 ` Samuel Holland
2024-08-15 15:07 ` Emil Renner Berthing
2024-08-15 15:07 ` Emil Renner Berthing
2024-08-15 15:59 ` Samuel Holland
2024-08-15 15:59 ` Samuel Holland
2024-08-15 17:51 ` Palmer Dabbelt
2024-08-15 17:51 ` Palmer Dabbelt
2024-08-15 18:04 ` Thomas Gleixner
2024-08-15 18:04 ` Thomas Gleixner
2024-08-16 6:13 ` Icenowy Zheng
2024-08-16 6:13 ` Icenowy Zheng
2024-08-15 15:14 ` Thomas Gleixner
2024-08-15 15:14 ` Thomas Gleixner
2024-08-15 14:30 ` Anup Patel
2024-08-15 14:30 ` Anup Patel
2024-08-15 15:03 ` Samuel Holland
2024-08-15 15:03 ` Samuel Holland
2024-08-15 15:53 ` Anup Patel
2024-08-15 15:53 ` Anup Patel
2024-08-16 6:09 ` Icenowy Zheng
2024-08-16 6:09 ` Icenowy Zheng
2024-08-15 13:35 ` Emil Renner Berthing
2024-08-15 13:35 ` Emil Renner Berthing
2024-08-15 17:51 ` Palmer Dabbelt
2024-08-15 17:51 ` Palmer Dabbelt
2024-08-15 18:10 ` Thomas Gleixner
2024-08-15 18:10 ` Thomas Gleixner
2024-08-15 23:04 ` Palmer Dabbelt
2024-08-15 23:04 ` Palmer Dabbelt
2024-08-16 6:15 ` Icenowy Zheng
2024-08-16 6:15 ` Icenowy Zheng
2024-08-18 14:47 ` Palmer Dabbelt
2024-08-18 14:47 ` Palmer Dabbelt
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