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From: Kalle Valo <kvalo@codeaurora.org>
To: Brian Norris <briannorris@chromium.org>
Cc: "Michał Kazior" <kazikcz@gmail.com>,
	linux-wireless <linux-wireless@vger.kernel.org>,
	ath10k@lists.infradead.org, "Wen Gong" <wgong@codeaurora.org>
Subject: Re: [PATCH] ath10k: support PCIe enter L1 state
Date: Fri, 08 Mar 2019 11:42:29 +0200	[thread overview]
Message-ID: <87h8cd8zy2.fsf@kamboji.qca.qualcomm.com> (raw)
In-Reply-To: <CA+ASDXO8NujrORVLZMPbDy916cnzOvx_Bp8Vr-VvkbBwJvB97A@mail.gmail.com> (Brian Norris's message of "Fri, 8 Feb 2019 09:05:11 -0800")

Brian Norris <briannorris@chromium.org> writes:

> On Fri, Feb 8, 2019 at 5:42 AM Kalle Valo <kvalo@codeaurora.org> wrote:
>> No replies from anyone (including Wen) for 3 months about testing this
>> patch on anything else than QCA6174. So I'll drop this now, please
>> resubmit once test coverage is better.
>
> I know this isn't exactly what you're asking for, but FWIW we've been
> using this since late November on all our QCA6174 products. No issues
> seen as far as I know, and we have seen some power savings.

Thanks for the feedback, this is very good to know. I also would like to
apply this but not before we have some testing feedback from AP chipsets
like QCA988X or QCA9984. Wen, are you planning to test those and
resubmit?

-- 
Kalle Valo

_______________________________________________
ath10k mailing list
ath10k@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/ath10k

WARNING: multiple messages have this Message-ID (diff)
From: Kalle Valo <kvalo@codeaurora.org>
To: Brian Norris <briannorris@chromium.org>
Cc: "Michał Kazior" <kazikcz@gmail.com>,
	linux-wireless <linux-wireless@vger.kernel.org>,
	ath10k@lists.infradead.org, "Wen Gong" <wgong@codeaurora.org>
Subject: Re: [PATCH] ath10k: support PCIe enter L1 state
Date: Fri, 08 Mar 2019 11:42:29 +0200	[thread overview]
Message-ID: <87h8cd8zy2.fsf@kamboji.qca.qualcomm.com> (raw)
In-Reply-To: <CA+ASDXO8NujrORVLZMPbDy916cnzOvx_Bp8Vr-VvkbBwJvB97A@mail.gmail.com> (Brian Norris's message of "Fri, 8 Feb 2019 09:05:11 -0800")

Brian Norris <briannorris@chromium.org> writes:

> On Fri, Feb 8, 2019 at 5:42 AM Kalle Valo <kvalo@codeaurora.org> wrote:
>> No replies from anyone (including Wen) for 3 months about testing this
>> patch on anything else than QCA6174. So I'll drop this now, please
>> resubmit once test coverage is better.
>
> I know this isn't exactly what you're asking for, but FWIW we've been
> using this since late November on all our QCA6174 products. No issues
> seen as far as I know, and we have seen some power savings.

Thanks for the feedback, this is very good to know. I also would like to
apply this but not before we have some testing feedback from AP chipsets
like QCA988X or QCA9984. Wen, are you planning to test those and
resubmit?

-- 
Kalle Valo

  reply	other threads:[~2019-03-08  9:42 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-14  2:50 [PATCH] ath10k: support PCIe enter L1 state Wen Gong
2018-11-14  2:50 ` Wen Gong
2018-11-15  0:28 ` Brian Norris
2018-11-15  0:28   ` Brian Norris
2018-11-15  6:38   ` Wen Gong
2018-11-15  6:38     ` Wen Gong
2018-11-15 18:43     ` Brian Norris
2018-11-15 18:43       ` Brian Norris
2018-11-16  7:00       ` Kalle Valo
2018-11-16  7:00         ` Kalle Valo
2018-11-16  7:56         ` Michał Kazior
2018-11-16  7:56           ` Michał Kazior
2019-02-08 13:42           ` Kalle Valo
2019-02-08 13:42             ` Kalle Valo
2019-02-08 17:05             ` Brian Norris
2019-02-08 17:05               ` Brian Norris
2019-03-08  9:42               ` Kalle Valo [this message]
2019-03-08  9:42                 ` Kalle Valo
2019-12-02 18:48                 ` Brian Norris
2019-12-02 18:48                   ` Brian Norris
2020-02-13 11:15                   ` Kalle Valo
2020-02-13 11:15                     ` Kalle Valo

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