Re: [Qemu-arm] [PATCH v1 02/12] target/arm: Add ARM_FEATURE_V8_1_SIMD

["Alex Bennée" <alex.bennee@linaro.org>]

Richard Henderson <richard.henderson@linaro.org> writes:

"...and enable it for the 'any' CPUs used by linux-user"?

Otherwise:

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.h     | 1 +
>  linux-user/elfload.c | 9 +++++++++
>  target/arm/cpu.c     | 1 +
>  target/arm/cpu64.c   | 1 +
>  4 files changed, 12 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 69cb49acc3..c5c9cef834 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1312,6 +1312,7 @@ enum arm_features {
>      ARM_FEATURE_VBAR, /* has cp15 VBAR */
>      ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
>      ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */
> +    ARM_FEATURE_V8_1_SIMD, /* has ARMv8.1-SIMD */
>  };
>
>  static inline int arm_feature(CPUARMState *env, int feature)
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 79062882ba..003d9420b7 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -512,6 +512,14 @@ enum {
>      ARM_HWCAP_A64_SHA1          = 1 << 5,
>      ARM_HWCAP_A64_SHA2          = 1 << 6,
>      ARM_HWCAP_A64_CRC32         = 1 << 7,
> +    ARM_HWCAP_A64_ATOMICS       = 1 << 8,
> +    ARM_HWCAP_A64_FPHP          = 1 << 9,
> +    ARM_HWCAP_A64_ASIMDHP       = 1 << 10,
> +    ARM_HWCAP_A64_CPUID         = 1 << 11,
> +    ARM_HWCAP_A64_ASIMDRDM      = 1 << 12,
> +    ARM_HWCAP_A64_JSCVT         = 1 << 13,
> +    ARM_HWCAP_A64_FCMA          = 1 << 14,
> +    ARM_HWCAP_A64_LRCPC         = 1 << 15,
>  };
>
>  #define ELF_HWCAP get_elf_hwcap()
> @@ -532,6 +540,7 @@ static uint32_t get_elf_hwcap(void)
>      GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1);
>      GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2);
>      GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32);
> +    GET_FEATURE(ARM_FEATURE_V8_1_SIMD, ARM_HWCAP_A64_ASIMDRDM);
>  #undef GET_FEATURE
>
>      return hwcaps;
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 4300de66e2..276c996e9f 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1603,6 +1603,7 @@ static void arm_any_initfn(Object *obj)
>      set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
>      set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
>      set_feature(&cpu->env, ARM_FEATURE_CRC);
> +    set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD);
>      cpu->midr = 0xffffffff;
>  }
>  #endif
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 670c07ab6e..b05c904ad2 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -226,6 +226,7 @@ static void aarch64_any_initfn(Object *obj)
>      set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
>      set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
>      set_feature(&cpu->env, ARM_FEATURE_CRC);
> +    set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD);
>      cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
>      cpu->dcz_blocksize = 7; /*  512 bytes */
>  }


--
Alex Bennée