From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org
Subject: Re: [Qemu-arm] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns
Date: Mon, 13 Nov 2017 17:16:57 +0000 [thread overview]
Message-ID: <87mv3q9jzq.fsf@linaro.org> (raw)
In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> This patch set depends on v3 of native-vector-registers;
> for ease of review the whole tree is at
>
> git://github.com/rth7680/qemu.git tgt-arm-cplx
>
> I have successfully tested all insns for AArch64 via RISU.
> I have successfully tested everything but VCMLA for AArch32.
>
> The insn that doesn't match up is
>
> fef3c848 vcmla.f32 q14, <illegal reg q1.5>, d8[0], #270
>
> for which FoundationModel is *not* signalling illegal insn.
> I'm not really sure what it is doing -- perhaps treating the
> insn as a coprocessor 8 nop? I'll have to investigate further.
>
> In the meantime, it's surely time for a round 1 review.
OK I'm done with round 1 review, I skipped past the later complex
instructions as I don't have access to the 8.3 ARM ARM yet (although the
instructions are in the ASL HTML dumps).
>
>
> r~
>
>
> Richard Henderson (12):
> HACK: use objdump disas
> target/arm: Add ARM_FEATURE_V8_1_SIMD
> target/arm: Decode aa64 armv8.1 scalar three same extra
> target/arm: Decode aa64 armv8.1 three same extra
> target/arm: Decode aa64 armv8.1 scalar/vector x indexed element
> target/arm: Decode aa32 armv8.1 three same
> target/arm: Decode aa32 armv8.1 two reg and a scalar
> target/arm: Add ARM_FEATURE_V8_FCMA
> target/arm: Decode aa64 armv8.3 fcadd
> target/arm: Decode aa64 armv8.3 fcmla
> target/arm: Decode aa32 armv8.3 3-same
> target/arm: Decode aa32 armv8.3 2-reg-index
>
> target/arm/cpu.h | 2 +
> target/arm/helper.h | 26 ++++
> disas.c | 2 +-
> linux-user/elfload.c | 10 ++
> target/arm/advsimd_helper.c | 331 +++++++++++++++++++++++++++++++++++++++++
> target/arm/cpu.c | 2 +
> target/arm/cpu64.c | 2 +
> target/arm/translate-a64.c | 350 +++++++++++++++++++++++++++++++++++++++-----
> target/arm/translate.c | 241 +++++++++++++++++++++++++++---
> target/arm/Makefile.objs | 2 +-
> 10 files changed, 912 insertions(+), 56 deletions(-)
> create mode 100644 target/arm/advsimd_helper.c
--
Alex Bennée
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns
Date: Mon, 13 Nov 2017 17:16:57 +0000 [thread overview]
Message-ID: <87mv3q9jzq.fsf@linaro.org> (raw)
In-Reply-To: <20171004184325.24157-1-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> This patch set depends on v3 of native-vector-registers;
> for ease of review the whole tree is at
>
> git://github.com/rth7680/qemu.git tgt-arm-cplx
>
> I have successfully tested all insns for AArch64 via RISU.
> I have successfully tested everything but VCMLA for AArch32.
>
> The insn that doesn't match up is
>
> fef3c848 vcmla.f32 q14, <illegal reg q1.5>, d8[0], #270
>
> for which FoundationModel is *not* signalling illegal insn.
> I'm not really sure what it is doing -- perhaps treating the
> insn as a coprocessor 8 nop? I'll have to investigate further.
>
> In the meantime, it's surely time for a round 1 review.
OK I'm done with round 1 review, I skipped past the later complex
instructions as I don't have access to the 8.3 ARM ARM yet (although the
instructions are in the ASL HTML dumps).
>
>
> r~
>
>
> Richard Henderson (12):
> HACK: use objdump disas
> target/arm: Add ARM_FEATURE_V8_1_SIMD
> target/arm: Decode aa64 armv8.1 scalar three same extra
> target/arm: Decode aa64 armv8.1 three same extra
> target/arm: Decode aa64 armv8.1 scalar/vector x indexed element
> target/arm: Decode aa32 armv8.1 three same
> target/arm: Decode aa32 armv8.1 two reg and a scalar
> target/arm: Add ARM_FEATURE_V8_FCMA
> target/arm: Decode aa64 armv8.3 fcadd
> target/arm: Decode aa64 armv8.3 fcmla
> target/arm: Decode aa32 armv8.3 3-same
> target/arm: Decode aa32 armv8.3 2-reg-index
>
> target/arm/cpu.h | 2 +
> target/arm/helper.h | 26 ++++
> disas.c | 2 +-
> linux-user/elfload.c | 10 ++
> target/arm/advsimd_helper.c | 331 +++++++++++++++++++++++++++++++++++++++++
> target/arm/cpu.c | 2 +
> target/arm/cpu64.c | 2 +
> target/arm/translate-a64.c | 350 +++++++++++++++++++++++++++++++++++++++-----
> target/arm/translate.c | 241 +++++++++++++++++++++++++++---
> target/arm/Makefile.objs | 2 +-
> 10 files changed, 912 insertions(+), 56 deletions(-)
> create mode 100644 target/arm/advsimd_helper.c
--
Alex Bennée
next prev parent reply other threads:[~2017-11-13 17:16 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-04 18:43 [Qemu-arm] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns Richard Henderson
2017-10-04 18:43 ` [Qemu-devel] " Richard Henderson
2017-10-04 18:43 ` [Qemu-arm] [PATCH v1 01/12] HACK: use objdump disas Richard Henderson
2017-10-04 18:43 ` [Qemu-devel] " Richard Henderson
2017-11-13 11:33 ` [Qemu-arm] " Alex Bennée
2017-11-13 11:33 ` [Qemu-devel] " Alex Bennée
2017-11-14 8:38 ` Richard Henderson
2017-11-14 8:38 ` [Qemu-devel] " Richard Henderson
2017-10-04 18:43 ` [Qemu-arm] [PATCH v1 02/12] target/arm: Add ARM_FEATURE_V8_1_SIMD Richard Henderson
2017-10-04 18:43 ` [Qemu-devel] " Richard Henderson
2017-11-13 11:34 ` [Qemu-arm] " Alex Bennée
2017-11-13 11:34 ` [Qemu-devel] " Alex Bennée
2017-10-04 18:43 ` [Qemu-arm] [PATCH v1 03/12] target/arm: Decode aa64 armv8.1 scalar three same extra Richard Henderson
2017-10-04 18:43 ` [Qemu-devel] " Richard Henderson
2017-11-13 16:30 ` [Qemu-arm] " Alex Bennée
2017-11-13 16:30 ` [Qemu-devel] " Alex Bennée
2017-11-13 16:42 ` Peter Maydell
2017-11-14 8:44 ` Richard Henderson
2017-11-14 8:44 ` [Qemu-devel] " Richard Henderson
2017-10-04 18:43 ` [Qemu-devel] [PATCH v1 04/12] target/arm: Decode aa64 armv8.1 " Richard Henderson
2017-11-13 16:41 ` Alex Bennée
2017-10-04 18:43 ` [Qemu-arm] [PATCH v1 05/12] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element Richard Henderson
2017-10-04 18:43 ` [Qemu-devel] " Richard Henderson
2017-11-13 16:44 ` [Qemu-arm] " Alex Bennée
2017-11-13 16:44 ` [Qemu-devel] " Alex Bennée
2017-10-04 18:43 ` [Qemu-arm] [PATCH v1 06/12] target/arm: Decode aa32 armv8.1 three same Richard Henderson
2017-10-04 18:43 ` [Qemu-devel] " Richard Henderson
2017-11-13 16:55 ` [Qemu-arm] " Alex Bennée
2017-11-13 16:55 ` [Qemu-devel] " Alex Bennée
2017-11-14 8:46 ` Richard Henderson
2017-11-14 8:46 ` [Qemu-devel] " Richard Henderson
2017-11-14 10:06 ` Alex Bennée
2017-11-14 10:06 ` [Qemu-devel] " Alex Bennée
2017-11-14 10:46 ` Richard Henderson
2017-11-14 10:46 ` [Qemu-devel] " Richard Henderson
2017-10-04 18:43 ` [Qemu-devel] [PATCH v1 07/12] target/arm: Decode aa32 armv8.1 two reg and a scalar Richard Henderson
2017-11-13 17:05 ` Alex Bennée
2017-11-22 13:12 ` Richard Henderson
2017-10-04 18:43 ` [Qemu-arm] [PATCH v1 08/12] target/arm: Add ARM_FEATURE_V8_FCMA Richard Henderson
2017-10-04 18:43 ` [Qemu-devel] " Richard Henderson
2017-11-13 17:06 ` [Qemu-arm] " Alex Bennée
2017-11-13 17:06 ` [Qemu-devel] " Alex Bennée
2017-10-04 18:43 ` [Qemu-devel] [PATCH v1 09/12] target/arm: Decode aa64 armv8.3 fcadd Richard Henderson
2017-11-13 17:12 ` Alex Bennée
2017-10-04 18:43 ` [Qemu-devel] [PATCH v1 10/12] target/arm: Decode aa64 armv8.3 fcmla Richard Henderson
2017-10-04 18:43 ` [Qemu-devel] [PATCH v1 11/12] target/arm: Decode aa32 armv8.3 3-same Richard Henderson
2017-10-04 18:43 ` [Qemu-devel] [PATCH v1 12/12] target/arm: Decode aa32 armv8.3 2-reg-index Richard Henderson
2017-10-04 18:58 ` [Qemu-devel] [PATCH v1 00/12] ARM v8.1 simd + v8.3 complex insns no-reply
2017-10-04 18:58 ` no-reply
2017-10-04 18:58 ` [Qemu-arm] " no-reply
2017-10-04 18:58 ` no-reply
2017-10-04 18:58 ` [Qemu-arm] " no-reply
2017-10-04 18:58 ` no-reply
2017-11-13 17:16 ` Alex Bennée [this message]
2017-11-13 17:16 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
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