[PATCH 1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

[PATCH 1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use intel_ddi_dp_voltage_max() for HSW/BDW too instead of letting these
fall through the if ladder in a weird way. This function will look at
the actual buf trans tables we have for HSW/BDW to determine the max
vswing level.

It looks to me like the current code leads HSW port A down the IVB port
A path, HSW port B+ and BDW fall through to the very end. Both cases do
result in the correct max vswing level 2, but it's very hard to see that
from the code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2cc58596ff5a..4755bb1b0b40 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3220,12 +3220,12 @@ uint8_t
 intel_dp_voltage_max(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
-	enum port port = dp_to_dig_port(intel_dp)->base.port;
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	enum port port = encoder->port;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
-		struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	if (HAS_DDI(dev_priv))
 		return intel_ddi_dp_voltage_max(encoder);
-	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else if (IS_GEN7(dev_priv) && port == PORT_A)
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
-- 
2.16.1

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[PATCH 2/5] drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All DDI platforms support the full set of preemph settings for each
supported vswing, so let's use the same code for them. We'll also move
the code into intel_ddi.c so that it sits closer to the actual buf trans
tables.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c  | 30 ++++--------------------------
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 3 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index b98ac0541f19..1665bc588241 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2115,6 +2115,26 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 		DP_TRAIN_VOLTAGE_SWING_MASK;
 }
 
+/*
+ * We assume that the full set of pre-emphasis values can be
+ * used on all DDI platforms. Should that change we need to
+ * rethink this code.
+ */
+u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
+{
+	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
+		return DP_TRAIN_PRE_EMPH_LEVEL_3;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+		return DP_TRAIN_PRE_EMPH_LEVEL_2;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+		return DP_TRAIN_PRE_EMPH_LEVEL_1;
+	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
+	default:
+		return DP_TRAIN_PRE_EMPH_LEVEL_0;
+	}
+}
+
 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
 				   int level, enum intel_output_type type)
 {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4755bb1b0b40..538b10084a9d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3239,33 +3239,11 @@ uint8_t
 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
-	enum port port = dp_to_dig_port(intel_dp)->base.port;
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	enum port port = encoder->port;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
-		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-			return DP_TRAIN_PRE_EMPH_LEVEL_3;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-			return DP_TRAIN_PRE_EMPH_LEVEL_2;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-			return DP_TRAIN_PRE_EMPH_LEVEL_1;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
-			return DP_TRAIN_PRE_EMPH_LEVEL_0;
-		default:
-			return DP_TRAIN_PRE_EMPH_LEVEL_0;
-		}
-	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
-			return DP_TRAIN_PRE_EMPH_LEVEL_3;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
-			return DP_TRAIN_PRE_EMPH_LEVEL_2;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
-			return DP_TRAIN_PRE_EMPH_LEVEL_1;
-		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
-		default:
-			return DP_TRAIN_PRE_EMPH_LEVEL_0;
-		}
+	if (HAS_DDI(dev_priv)) {
+		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 12002fc77235..22af249393a4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1410,6 +1410,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 u32 bxt_signal_levels(struct intel_dp *intel_dp);
 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
+u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
+				 u8 voltage_swing);
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
 				     bool enable);
 void icl_map_plls_to_ports(struct drm_crtc *crtc,
-- 
2.16.1

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[PATCH 3/5] drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Almost all of the GEN7 checks in the DP code are actually looking for
IVB. HSW doesn't even take these codepaths, and VLV is excluded on
account of not having port A. So let's change the checks to IS_IVB to
make the code less confusing.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 538b10084a9d..263e4b1d1db9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1989,7 +1989,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 
 	/* Split out the IBX/CPU vs CPT settings */
 
-	if (IS_GEN7(dev_priv) && port == PORT_A) {
+	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 			intel_dp->DP |= DP_SYNC_HS_HIGH;
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -2669,7 +2669,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 	if (!(tmp & DP_PORT_EN))
 		goto out;
 
-	if (IS_GEN7(dev_priv) && port == PORT_A) {
+	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
 		*pipe = PORT_TO_PIPE_CPT(tmp);
 	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
 		enum pipe p;
@@ -2908,7 +2908,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
 		}
 		I915_WRITE(DP_TP_CTL(port), temp);
 
-	} else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
+	} else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
 		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
 		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
 
@@ -3227,7 +3227,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 		return intel_ddi_dp_voltage_max(encoder);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
-	else if (IS_GEN7(dev_priv) && port == PORT_A)
+	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
@@ -3256,7 +3256,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 		default:
 			return DP_TRAIN_PRE_EMPH_LEVEL_0;
 		}
-	} else if (IS_GEN7(dev_priv) && port == PORT_A) {
+	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			return DP_TRAIN_PRE_EMPH_LEVEL_2;
@@ -3565,7 +3565,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 		signal_levels = chv_signal_levels(intel_dp);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		signal_levels = vlv_signal_levels(intel_dp);
-	} else if (IS_GEN7(dev_priv) && port == PORT_A) {
+	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
 		signal_levels = gen7_edp_signal_levels(train_set);
 		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
 	} else if (IS_GEN6(dev_priv) && port == PORT_A) {
@@ -3655,7 +3655,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
 
 	DRM_DEBUG_KMS("\n");
 
-	if ((IS_GEN7(dev_priv) && port == PORT_A) ||
+	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
 	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
 		DP &= ~DP_LINK_TRAIN_MASK_CPT;
 		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
-- 
2.16.1

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[PATCH 4/5] drm/i915: Rename SNB/IVB CPU eDP signal level funcs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

To make the intent more clear, let's rename the signal level funcs for
the SNB/IVB CPU eDP.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 263e4b1d1db9..cd4c60bfc4c2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3488,9 +3488,9 @@ gen4_signal_levels(uint8_t train_set)
 	return signal_levels;
 }
 
-/* Gen6's DP voltage swing and pre-emphasis control */
+/* SNB CPU eDP voltage swing and pre-emphasis control */
 static uint32_t
-gen6_edp_signal_levels(uint8_t train_set)
+snb_cpu_edp_signal_levels(uint8_t train_set)
 {
 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
 					 DP_TRAIN_PRE_EMPHASIS_MASK);
@@ -3516,9 +3516,9 @@ gen6_edp_signal_levels(uint8_t train_set)
 	}
 }
 
-/* Gen7's DP voltage swing and pre-emphasis control */
+/* IVB CPU eDP voltage swing and pre-emphasis control */
 static uint32_t
-gen7_edp_signal_levels(uint8_t train_set)
+ivb_cpu_edp_signal_levels(uint8_t train_set)
 {
 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
 					 DP_TRAIN_PRE_EMPHASIS_MASK);
@@ -3566,10 +3566,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		signal_levels = vlv_signal_levels(intel_dp);
 	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
-		signal_levels = gen7_edp_signal_levels(train_set);
+		signal_levels = ivb_cpu_edp_signal_levels(train_set);
 		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
 	} else if (IS_GEN6(dev_priv) && port == PORT_A) {
-		signal_levels = gen6_edp_signal_levels(train_set);
+		signal_levels = snb_cpu_edp_signal_levels(train_set);
 		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
 	} else {
 		signal_levels = gen4_signal_levels(train_set);
-- 
2.16.1

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[PATCH 5/5] drm/i915: Rename the remaining gen4 references to g4x in the DP code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

i965 does not have native DP. Let's rename the remaining gen4 references
in the DP code to g4x.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cd4c60bfc4c2..102070940095 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -56,7 +56,7 @@ struct dp_link_dpll {
 	struct dpll dpll;
 };
 
-static const struct dp_link_dpll gen4_dpll[] = {
+static const struct dp_link_dpll g4x_dpll[] = {
 	{ 162000,
 		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
 	{ 270000,
@@ -1550,8 +1550,8 @@ intel_dp_set_clock(struct intel_encoder *encoder,
 	int i, count = 0;
 
 	if (IS_G4X(dev_priv)) {
-		divisor = gen4_dpll;
-		count = ARRAY_SIZE(gen4_dpll);
+		divisor = g4x_dpll;
+		count = ARRAY_SIZE(g4x_dpll);
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		divisor = pch_dpll;
 		count = ARRAY_SIZE(pch_dpll);
@@ -3451,7 +3451,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
 }
 
 static uint32_t
-gen4_signal_levels(uint8_t train_set)
+g4x_signal_levels(uint8_t train_set)
 {
 	uint32_t	signal_levels = 0;
 
@@ -3572,7 +3572,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 		signal_levels = snb_cpu_edp_signal_levels(train_set);
 		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
 	} else {
-		signal_levels = gen4_signal_levels(train_set);
+		signal_levels = g4x_signal_levels(train_set);
 		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
 	}
 
-- 
2.16.1

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Re: [PATCH 1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

[Jani Nikula]

On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use intel_ddi_dp_voltage_max() for HSW/BDW too instead of letting these
> fall through the if ladder in a weird way. This function will look at
> the actual buf trans tables we have for HSW/BDW to determine the max
> vswing level.
>
> It looks to me like the current code leads HSW port A down the IVB port
> A path, HSW port B+ and BDW fall through to the very end. Both cases do
> result in the correct max vswing level 2, but it's very hard to see that
> from the code.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

What a PITA patch to review that there are no functional changes!

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2cc58596ff5a..4755bb1b0b40 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3220,12 +3220,12 @@ uint8_t
>  intel_dp_voltage_max(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> -	enum port port = dp_to_dig_port(intel_dp)->base.port;
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	enum port port = encoder->port;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> -		struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	if (HAS_DDI(dev_priv))
>  		return intel_ddi_dp_voltage_max(encoder);
> -	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> +	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  	else if (IS_GEN7(dev_priv) && port == PORT_A)
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 2/5] drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+

[Jani Nikula]

On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> All DDI platforms support the full set of preemph settings for each
> supported vswing, so let's use the same code for them. We'll also move
> the code into intel_ddi.c so that it sits closer to the actual buf trans
> tables.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c  | 30 ++++--------------------------
>  drivers/gpu/drm/i915/intel_drv.h |  2 ++
>  3 files changed, 26 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index b98ac0541f19..1665bc588241 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2115,6 +2115,26 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>  		DP_TRAIN_VOLTAGE_SWING_MASK;
>  }
>  
> +/*
> + * We assume that the full set of pre-emphasis values can be
> + * used on all DDI platforms. Should that change we need to
> + * rethink this code.
> + */
> +u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
> +{
> +	switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> +		return DP_TRAIN_PRE_EMPH_LEVEL_3;
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> +		return DP_TRAIN_PRE_EMPH_LEVEL_2;
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> +		return DP_TRAIN_PRE_EMPH_LEVEL_1;
> +	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> +	default:
> +		return DP_TRAIN_PRE_EMPH_LEVEL_0;
> +	}
> +}
> +
>  static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
>  				   int level, enum intel_output_type type)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4755bb1b0b40..538b10084a9d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3239,33 +3239,11 @@ uint8_t
>  intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> -	enum port port = dp_to_dig_port(intel_dp)->base.port;
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	enum port port = encoder->port;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> -		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_3;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_1;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_0;
> -		default:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_0;
> -		}
> -	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_3;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_1;
> -		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
> -		default:
> -			return DP_TRAIN_PRE_EMPH_LEVEL_0;
> -		}
> +	if (HAS_DDI(dev_priv)) {
> +		return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 12002fc77235..22af249393a4 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1410,6 +1410,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
>  u32 bxt_signal_levels(struct intel_dp *intel_dp);
>  uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
>  u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
> +u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
> +				 u8 voltage_swing);
>  int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
>  				     bool enable);
>  void icl_map_plls_to_ports(struct drm_crtc *crtc,

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/5] drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP

[Jani Nikula]

On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Almost all of the GEN7 checks in the DP code are actually looking for
> IVB. HSW doesn't even take these codepaths, and VLV is excluded on
> account of not having port A. So let's change the checks to IS_IVB to
> make the code less confusing.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Yup.

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 538b10084a9d..263e4b1d1db9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1989,7 +1989,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
>  
>  	/* Split out the IBX/CPU vs CPT settings */
>  
> -	if (IS_GEN7(dev_priv) && port == PORT_A) {
> +	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>  			intel_dp->DP |= DP_SYNC_HS_HIGH;
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> @@ -2669,7 +2669,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>  	if (!(tmp & DP_PORT_EN))
>  		goto out;
>  
> -	if (IS_GEN7(dev_priv) && port == PORT_A) {
> +	if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
>  		*pipe = PORT_TO_PIPE_CPT(tmp);
>  	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
>  		enum pipe p;
> @@ -2908,7 +2908,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
>  		}
>  		I915_WRITE(DP_TP_CTL(port), temp);
>  
> -	} else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
> +	} else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
>  		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
>  		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
>  
> @@ -3227,7 +3227,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  		return intel_ddi_dp_voltage_max(encoder);
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> -	else if (IS_GEN7(dev_priv) && port == PORT_A)
> +	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
>  	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> @@ -3256,7 +3256,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  		default:
>  			return DP_TRAIN_PRE_EMPH_LEVEL_0;
>  		}
> -	} else if (IS_GEN7(dev_priv) && port == PORT_A) {
> +	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			return DP_TRAIN_PRE_EMPH_LEVEL_2;
> @@ -3565,7 +3565,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  		signal_levels = chv_signal_levels(intel_dp);
>  	} else if (IS_VALLEYVIEW(dev_priv)) {
>  		signal_levels = vlv_signal_levels(intel_dp);
> -	} else if (IS_GEN7(dev_priv) && port == PORT_A) {
> +	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
>  		signal_levels = gen7_edp_signal_levels(train_set);
>  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
>  	} else if (IS_GEN6(dev_priv) && port == PORT_A) {
> @@ -3655,7 +3655,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
>  
>  	DRM_DEBUG_KMS("\n");
>  
> -	if ((IS_GEN7(dev_priv) && port == PORT_A) ||
> +	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
>  	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
>  		DP &= ~DP_LINK_TRAIN_MASK_CPT;
>  		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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Re: [PATCH 4/5] drm/i915: Rename SNB/IVB CPU eDP signal level funcs

[Jani Nikula]

On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> To make the intent more clear, let's rename the signal level funcs for
> the SNB/IVB CPU eDP.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 263e4b1d1db9..cd4c60bfc4c2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3488,9 +3488,9 @@ gen4_signal_levels(uint8_t train_set)
>  	return signal_levels;
>  }
>  
> -/* Gen6's DP voltage swing and pre-emphasis control */
> +/* SNB CPU eDP voltage swing and pre-emphasis control */
>  static uint32_t
> -gen6_edp_signal_levels(uint8_t train_set)
> +snb_cpu_edp_signal_levels(uint8_t train_set)
>  {
>  	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
>  					 DP_TRAIN_PRE_EMPHASIS_MASK);
> @@ -3516,9 +3516,9 @@ gen6_edp_signal_levels(uint8_t train_set)
>  	}
>  }
>  
> -/* Gen7's DP voltage swing and pre-emphasis control */
> +/* IVB CPU eDP voltage swing and pre-emphasis control */
>  static uint32_t
> -gen7_edp_signal_levels(uint8_t train_set)
> +ivb_cpu_edp_signal_levels(uint8_t train_set)
>  {
>  	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
>  					 DP_TRAIN_PRE_EMPHASIS_MASK);
> @@ -3566,10 +3566,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  	} else if (IS_VALLEYVIEW(dev_priv)) {
>  		signal_levels = vlv_signal_levels(intel_dp);
>  	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> -		signal_levels = gen7_edp_signal_levels(train_set);
> +		signal_levels = ivb_cpu_edp_signal_levels(train_set);
>  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
>  	} else if (IS_GEN6(dev_priv) && port == PORT_A) {

Should we use IS_SANDYBRIDGE() - which doesn't exist - here then...

Anyway,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> -		signal_levels = gen6_edp_signal_levels(train_set);
> +		signal_levels = snb_cpu_edp_signal_levels(train_set);
>  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
>  	} else {
>  		signal_levels = gen4_signal_levels(train_set);

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
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Re: [PATCH 5/5] drm/i915: Rename the remaining gen4 references to g4x in the DP code

[Jani Nikula]

On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> i965 does not have native DP. Let's rename the remaining gen4 references
> in the DP code to g4x.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cd4c60bfc4c2..102070940095 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -56,7 +56,7 @@ struct dp_link_dpll {
>  	struct dpll dpll;
>  };
>  
> -static const struct dp_link_dpll gen4_dpll[] = {
> +static const struct dp_link_dpll g4x_dpll[] = {
>  	{ 162000,
>  		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
>  	{ 270000,
> @@ -1550,8 +1550,8 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>  	int i, count = 0;
>  
>  	if (IS_G4X(dev_priv)) {
> -		divisor = gen4_dpll;
> -		count = ARRAY_SIZE(gen4_dpll);
> +		divisor = g4x_dpll;
> +		count = ARRAY_SIZE(g4x_dpll);
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		divisor = pch_dpll;
>  		count = ARRAY_SIZE(pch_dpll);
> @@ -3451,7 +3451,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
>  }
>  
>  static uint32_t
> -gen4_signal_levels(uint8_t train_set)
> +g4x_signal_levels(uint8_t train_set)
>  {
>  	uint32_t	signal_levels = 0;
>  
> @@ -3572,7 +3572,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  		signal_levels = snb_cpu_edp_signal_levels(train_set);
>  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
>  	} else {
> -		signal_levels = gen4_signal_levels(train_set);
> +		signal_levels = g4x_signal_levels(train_set);
>  		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
>  	}

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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Re: [PATCH 4/5] drm/i915: Rename SNB/IVB CPU eDP signal level funcs

[Ville Syrjälä]

On Thu, May 17, 2018 at 08:48:49PM +0300, Jani Nikula wrote:
> On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > To make the intent more clear, let's rename the signal level funcs for
> > the SNB/IVB CPU eDP.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 263e4b1d1db9..cd4c60bfc4c2 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3488,9 +3488,9 @@ gen4_signal_levels(uint8_t train_set)
> >  	return signal_levels;
> >  }
> >  
> > -/* Gen6's DP voltage swing and pre-emphasis control */
> > +/* SNB CPU eDP voltage swing and pre-emphasis control */
> >  static uint32_t
> > -gen6_edp_signal_levels(uint8_t train_set)
> > +snb_cpu_edp_signal_levels(uint8_t train_set)
> >  {
> >  	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> >  					 DP_TRAIN_PRE_EMPHASIS_MASK);
> > @@ -3516,9 +3516,9 @@ gen6_edp_signal_levels(uint8_t train_set)
> >  	}
> >  }
> >  
> > -/* Gen7's DP voltage swing and pre-emphasis control */
> > +/* IVB CPU eDP voltage swing and pre-emphasis control */
> >  static uint32_t
> > -gen7_edp_signal_levels(uint8_t train_set)
> > +ivb_cpu_edp_signal_levels(uint8_t train_set)
> >  {
> >  	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> >  					 DP_TRAIN_PRE_EMPHASIS_MASK);
> > @@ -3566,10 +3566,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> >  	} else if (IS_VALLEYVIEW(dev_priv)) {
> >  		signal_levels = vlv_signal_levels(intel_dp);
> >  	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> > -		signal_levels = gen7_edp_signal_levels(train_set);
> > +		signal_levels = ivb_cpu_edp_signal_levels(train_set);
> >  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
> >  	} else if (IS_GEN6(dev_priv) && port == PORT_A) {
> 
> Should we use IS_SANDYBRIDGE() - which doesn't exist - here then...

I have considered adding IS_ILK and IS_SNB to make some of
the display code more consistent looking. But I never bothered
to actually write the patch.

> 
> Anyway,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> > -		signal_levels = gen6_edp_signal_levels(train_set);
> > +		signal_levels = snb_cpu_edp_signal_levels(train_set);
> >  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
> >  	} else {
> >  		signal_levels = gen4_signal_levels(train_set);
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel
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✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too
URL   : https://patchwork.freedesktop.org/series/43353/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4200 -> Patchwork_9035 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/43353/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9035 that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-kbl-7567u:       FAIL (fdo#104724, fdo#103191) -> PASS

    
    ==== Warnings ====

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       DMESG-WARN -> DMESG-FAIL (fdo#102614, fdo#106103)

    
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (43 -> 39) ==

  Missing    (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4200 -> Patchwork_9035

  CI_DRM_4200: d7b67c87685f05c99d52db49184552f810bf1729 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9035: 2749433724c67bb7a20f7bbecb4f237b4d054e35 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit


== Linux commits ==

2749433724c6 drm/i915: Rename the remaining gen4 references to g4x in the DP code
1cf1eb527fc3 drm/i915: Rename SNB/IVB CPU eDP signal level funcs
2d6c51e9fad4 drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP
32fe5444b6b8 drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+
c71dc14d0f43 drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9035/issues.html
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✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too
URL   : https://patchwork.freedesktop.org/series/43353/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4200_full -> Patchwork_9035_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9035_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9035_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/43353/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9035_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-bsd1:
      shard-kbl:          PASS -> SKIP +3

    
== Known issues ==

  Here are the changes found in Patchwork_9035_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@modeset-vs-vblank-race:
      shard-glk:          PASS -> FAIL (fdo#103060)

    igt@kms_flip@plain-flip-fb-recreate:
      shard-glk:          PASS -> FAIL (fdo#100368) +1

    igt@kms_flip_tiling@flip-to-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#104724)

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
      shard-glk:          PASS -> FAIL (fdo#104724, fdo#103167) +1

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      shard-kbl:          DMESG-FAIL -> PASS

    igt@kms_flip@basic-flip-vs-dpms:
      shard-hsw:          DMESG-WARN (fdo#102614) -> PASS

    igt@kms_flip@flip-vs-expired-vblank:
      shard-hsw:          FAIL (fdo#102887) -> PASS
      shard-glk:          FAIL (fdo#105363) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4200 -> Patchwork_9035

  CI_DRM_4200: d7b67c87685f05c99d52db49184552f810bf1729 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9035: 2749433724c67bb7a20f7bbecb4f237b4d054e35 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9035/shards.html
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Re: [PATCH 5/5] drm/i915: Rename the remaining gen4 references to g4x in the DP code

[Ville Syrjälä]

On Thu, May 17, 2018 at 08:49:27PM +0300, Jani Nikula wrote:
> On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > i965 does not have native DP. Let's rename the remaining gen4 references
> > in the DP code to g4x.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Thanks. Entire series pushed to dinq.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index cd4c60bfc4c2..102070940095 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -56,7 +56,7 @@ struct dp_link_dpll {
> >  	struct dpll dpll;
> >  };
> >  
> > -static const struct dp_link_dpll gen4_dpll[] = {
> > +static const struct dp_link_dpll g4x_dpll[] = {
> >  	{ 162000,
> >  		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
> >  	{ 270000,
> > @@ -1550,8 +1550,8 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> >  	int i, count = 0;
> >  
> >  	if (IS_G4X(dev_priv)) {
> > -		divisor = gen4_dpll;
> > -		count = ARRAY_SIZE(gen4_dpll);
> > +		divisor = g4x_dpll;
> > +		count = ARRAY_SIZE(g4x_dpll);
> >  	} else if (HAS_PCH_SPLIT(dev_priv)) {
> >  		divisor = pch_dpll;
> >  		count = ARRAY_SIZE(pch_dpll);
> > @@ -3451,7 +3451,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
> >  }
> >  
> >  static uint32_t
> > -gen4_signal_levels(uint8_t train_set)
> > +g4x_signal_levels(uint8_t train_set)
> >  {
> >  	uint32_t	signal_levels = 0;
> >  
> > @@ -3572,7 +3572,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> >  		signal_levels = snb_cpu_edp_signal_levels(train_set);
> >  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
> >  	} else {
> > -		signal_levels = gen4_signal_levels(train_set);
> > +		signal_levels = g4x_signal_levels(train_set);
> >  		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
> >  	}
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel
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