[RFC PATCH 1/3] riscv: Correctly print supported extensions

[RFC PATCH 1/3] riscv: Correctly print supported extensions

[Tsukasa OI]

This commit replaces BITS_PER_LONG with magic number 26.

Current ISA pretty-printing code expects extension 'a' (bit 0) through
'z' (bit 25).  Although bit 26 and higher is not currently used (thus never
cause an issue in practice), it will be an annoying problem if we start to
use those in the future.

This commit disables printing high bits for now.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
 arch/riscv/kernel/cpufeature.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index d959d207a40d..6f2bf6ae4ae2 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -63,7 +63,7 @@ void __init riscv_fill_hwcap(void)
 {
 	struct device_node *node;
 	const char *isa;
-	char print_str[BITS_PER_LONG + 1];
+	char print_str[26 + 1];
 	size_t i, j, isa_len;
 	static unsigned long isa2hwcap[256] = {0};
 
@@ -133,13 +133,13 @@ void __init riscv_fill_hwcap(void)
 	}
 
 	memset(print_str, 0, sizeof(print_str));
-	for (i = 0, j = 0; i < BITS_PER_LONG; i++)
+	for (i = 0, j = 0; i < 26; i++)
 		if (riscv_isa[0] & BIT_MASK(i))
 			print_str[j++] = (char)('a' + i);
 	pr_info("riscv: ISA extensions %s\n", print_str);
 
 	memset(print_str, 0, sizeof(print_str));
-	for (i = 0, j = 0; i < BITS_PER_LONG; i++)
+	for (i = 0, j = 0; i < 26; i++)
 		if (elf_hwcap & BIT_MASK(i))
 			print_str[j++] = (char)('a' + i);
 	pr_info("riscv: ELF capabilities %s\n", print_str);
-- 
2.32.0


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Re: [RFC PATCH 1/3] riscv: Correctly print supported extensions

[Ben Dooks]

On 20/11/2021 08:53, Tsukasa OI wrote:
> This commit replaces BITS_PER_LONG with magic number 26.
> 
> Current ISA pretty-printing code expects extension 'a' (bit 0) through
> 'z' (bit 25).  Although bit 26 and higher is not currently used (thus never
> cause an issue in practice), it will be an annoying problem if we start to
> use those in the future.
> 
> This commit disables printing high bits for now.
> 
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
> ---
>   arch/riscv/kernel/cpufeature.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index d959d207a40d..6f2bf6ae4ae2 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -63,7 +63,7 @@ void __init riscv_fill_hwcap(void)
>   {
>   	struct device_node *node;
>   	const char *isa;
> -	char print_str[BITS_PER_LONG + 1];
> +	char print_str[26 + 1];
>   	size_t i, j, isa_len;
>   	static unsigned long isa2hwcap[256] = {0};
>   
> @@ -133,13 +133,13 @@ void __init riscv_fill_hwcap(void)
>   	}
>   
>   	memset(print_str, 0, sizeof(print_str));
> -	for (i = 0, j = 0; i < BITS_PER_LONG; i++)
> +	for (i = 0, j = 0; i < 26; i++)
>   		if (riscv_isa[0] & BIT_MASK(i))
>   			print_str[j++] = (char)('a' + i);
>   	pr_info("riscv: ISA extensions %s\n", print_str);
>   
>   	memset(print_str, 0, sizeof(print_str));
> -	for (i = 0, j = 0; i < BITS_PER_LONG; i++)
> +	for (i = 0, j = 0; i < 26; i++)
>   		if (elf_hwcap & BIT_MASK(i))
>   			print_str[j++] = (char)('a' + i);
>   	pr_info("riscv: ELF capabilities %s\n", print_str);
> 

Maybe add a warn on if there are bits set between 26 and BITS_PER_LONG ?



-- 
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Re: [RFC PATCH 1/3] riscv: Correctly print supported extensions

[Tsukasa OI]

On 2021/11/22 21:14, Ben Dooks wrote:
> 
> Maybe add a warn on if there are bits set between 26 and BITS_PER_LONG ?
> 

I think that's not necessary  because riscv_isa[0] and elf_hwcap on the
current parser will not have higher bits.  This commit is just for future-
proofing (not to break anything when we extend feature bits) and adding
warning message now feels a bit ... too much.

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Re: [RFC PATCH 1/3] riscv: Correctly print supported extensions

[Andreas Schwab]

On Nov 20 2021, Tsukasa OI wrote:

> This commit replaces BITS_PER_LONG with magic number 26.
>
> Current ISA pretty-printing code expects extension 'a' (bit 0) through
> 'z' (bit 25).  Although bit 26 and higher is not currently used (thus never
> cause an issue in practice), it will be an annoying problem if we start to
> use those in the future.

Perhaps replace 26 by 'z' - 'a' + 1?

Andreas.

-- 
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Re: [RFC PATCH 1/3] riscv: Correctly print supported extensions

[Tsukasa OI]

On 2021/11/22 21:35, Andreas Schwab wrote:
> On Nov 20 2021, Tsukasa OI wrote:
> 
>> This commit replaces BITS_PER_LONG with magic number 26.
>>
>> Current ISA pretty-printing code expects extension 'a' (bit 0) through
>> 'z' (bit 25).  Although bit 26 and higher is not currently used (thus never
>> cause an issue in practice), it will be an annoying problem if we start to
>> use those in the future.
> 
> Perhaps replace 26 by 'z' - 'a' + 1?

That's not bad. Possibly I can define:
#define NUM_ALPHA_EXTS ('z' - 'a' + 1)

I will submit RFC PATCH v2 by end of this week (I found several minor bugs in 
"riscv,isa" parser [patch 2,3] anyway) so I'll rewrite it.

Thanks!
Tsukasa,

> 
> Andreas.
> 

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