From: Nam Cao <namcao@linutronix.de>
To: "Charlie Jenkins" <thecharlesjenkins@gmail.com>,
"Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atish.patra@linux.dev>,
"Conor Dooley" <conor@kernel.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Shuah Khan" <shuah@kernel.org>,
"Radim Krčmář" <radim.krcmar@oss.qualcomm.com>,
"Jesse Taube" <jtaubepe@redhat.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <thecharlesjenkins@gmail.com>
Subject: Re: [PATCH v3 04/17] riscv: Add kprobes instruction simulation KUnit
Date: Thu, 06 Aug 2026 10:23:12 +0200 [thread overview]
Message-ID: <87ldajd5e7.fsf@yellow.woof> (raw)
In-Reply-To: <20260707-riscv_insn_table-v3-4-3f8e5f75ba97@gmail.com>
> + } else if (riscv_insn_is_c_jr(i)) {
> + u32 rs1_index = riscv_insn_c_jr_extract_xs1(i);
> +
> + simulate_c_jr(i, addr, ®s);
> +
> + KUNIT_EXPECT_EQ_MSG(test, regs.epc,
> + riscv_insn_reg_get_val((unsigned long *)®s,
> + rs1_index),
> + "c.jr instruction (0x%x) incorrectly simulated", i);
Should we set a value to rs1, just like everything else?
> diff --git a/arch/riscv/kernel/tests/kprobes/test-kprobes.h b/arch/riscv/kernel/tests/kprobes/test-kprobes.h
> index 537f44aa9d3f..7a672de8f130 100644
> --- a/arch/riscv/kernel/tests/kprobes/test-kprobes.h
> +++ b/arch/riscv/kernel/tests/kprobes/test-kprobes.h
> @@ -19,6 +19,12 @@ extern void *test_kprobes_addresses[];
> /* array of functions that return KPROBE_TEST_MAGIC */
> extern long (*test_kprobes_functions[])(void);
>
> +void test_kprobes_arbitrary(void);
> +
> +extern unsigned int *test_kprobes_arbitrary_addr;
> +
> +extern unsigned int *test_kprobes_c_bnez_addr1;
> +
Are these declarations used somewhere?
Nam
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kvm-riscv@lists.infradead.org
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WARNING: multiple messages have this Message-ID (diff)
From: Nam Cao <namcao@linutronix.de>
To: "Charlie Jenkins" <thecharlesjenkins@gmail.com>,
"Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atish.patra@linux.dev>,
"Conor Dooley" <conor@kernel.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Shuah Khan" <shuah@kernel.org>,
"Radim Krčmář" <radim.krcmar@oss.qualcomm.com>,
"Jesse Taube" <jtaubepe@redhat.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <thecharlesjenkins@gmail.com>
Subject: Re: [PATCH v3 04/17] riscv: Add kprobes instruction simulation KUnit
Date: Thu, 06 Aug 2026 10:23:12 +0200 [thread overview]
Message-ID: <87ldajd5e7.fsf@yellow.woof> (raw)
In-Reply-To: <20260707-riscv_insn_table-v3-4-3f8e5f75ba97@gmail.com>
> + } else if (riscv_insn_is_c_jr(i)) {
> + u32 rs1_index = riscv_insn_c_jr_extract_xs1(i);
> +
> + simulate_c_jr(i, addr, ®s);
> +
> + KUNIT_EXPECT_EQ_MSG(test, regs.epc,
> + riscv_insn_reg_get_val((unsigned long *)®s,
> + rs1_index),
> + "c.jr instruction (0x%x) incorrectly simulated", i);
Should we set a value to rs1, just like everything else?
> diff --git a/arch/riscv/kernel/tests/kprobes/test-kprobes.h b/arch/riscv/kernel/tests/kprobes/test-kprobes.h
> index 537f44aa9d3f..7a672de8f130 100644
> --- a/arch/riscv/kernel/tests/kprobes/test-kprobes.h
> +++ b/arch/riscv/kernel/tests/kprobes/test-kprobes.h
> @@ -19,6 +19,12 @@ extern void *test_kprobes_addresses[];
> /* array of functions that return KPROBE_TEST_MAGIC */
> extern long (*test_kprobes_functions[])(void);
>
> +void test_kprobes_arbitrary(void);
> +
> +extern unsigned int *test_kprobes_arbitrary_addr;
> +
> +extern unsigned int *test_kprobes_c_bnez_addr1;
> +
Are these declarations used somewhere?
Nam
WARNING: multiple messages have this Message-ID (diff)
From: Nam Cao <namcao@linutronix.de>
To: "Charlie Jenkins" <thecharlesjenkins@gmail.com>,
"Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atish.patra@linux.dev>,
"Conor Dooley" <conor@kernel.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Shuah Khan" <shuah@kernel.org>,
"Radim Krčmář" <radim.krcmar@oss.qualcomm.com>,
"Jesse Taube" <jtaubepe@redhat.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <thecharlesjenkins@gmail.com>
Subject: Re: [PATCH v3 04/17] riscv: Add kprobes instruction simulation KUnit
Date: Thu, 06 Aug 2026 10:23:12 +0200 [thread overview]
Message-ID: <87ldajd5e7.fsf@yellow.woof> (raw)
In-Reply-To: <20260707-riscv_insn_table-v3-4-3f8e5f75ba97@gmail.com>
> + } else if (riscv_insn_is_c_jr(i)) {
> + u32 rs1_index = riscv_insn_c_jr_extract_xs1(i);
> +
> + simulate_c_jr(i, addr, ®s);
> +
> + KUNIT_EXPECT_EQ_MSG(test, regs.epc,
> + riscv_insn_reg_get_val((unsigned long *)®s,
> + rs1_index),
> + "c.jr instruction (0x%x) incorrectly simulated", i);
Should we set a value to rs1, just like everything else?
> diff --git a/arch/riscv/kernel/tests/kprobes/test-kprobes.h b/arch/riscv/kernel/tests/kprobes/test-kprobes.h
> index 537f44aa9d3f..7a672de8f130 100644
> --- a/arch/riscv/kernel/tests/kprobes/test-kprobes.h
> +++ b/arch/riscv/kernel/tests/kprobes/test-kprobes.h
> @@ -19,6 +19,12 @@ extern void *test_kprobes_addresses[];
> /* array of functions that return KPROBE_TEST_MAGIC */
> extern long (*test_kprobes_functions[])(void);
>
> +void test_kprobes_arbitrary(void);
> +
> +extern unsigned int *test_kprobes_arbitrary_addr;
> +
> +extern unsigned int *test_kprobes_c_bnez_addr1;
> +
Are these declarations used somewhere?
Nam
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2026-08-06 8:23 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-08 3:34 [PATCH v3 00/17] riscv: Generate riscv instruction functions Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` [PATCH v3 01/17] riscv: Introduce instruction table generation Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:50 ` sashiko-bot
2026-07-09 6:23 ` Charlie Jenkins
2026-08-05 11:32 ` Nam Cao
2026-08-05 11:32 ` Nam Cao
2026-08-05 11:32 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 02/17] riscv: alternatives: Use generated instruction headers for patching code Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:45 ` sashiko-bot
2026-08-06 6:50 ` Nam Cao
2026-08-06 6:50 ` Nam Cao
2026-08-06 6:50 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 03/17] riscv: kgdb: Use generated instruction headers Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-08-06 7:09 ` Nam Cao
2026-08-06 7:09 ` Nam Cao
2026-08-06 7:09 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 04/17] riscv: Add kprobes instruction simulation KUnit Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:51 ` sashiko-bot
2026-08-06 8:23 ` Nam Cao [this message]
2026-08-06 8:23 ` Nam Cao
2026-08-06 8:23 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 05/17] riscv: kprobes: Use generated instruction headers Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:52 ` sashiko-bot
2026-08-06 8:30 ` Nam Cao
2026-08-06 8:30 ` Nam Cao
2026-08-06 8:30 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 06/17] riscv: cfi: " Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-08-06 8:30 ` Nam Cao
2026-08-06 8:30 ` Nam Cao
2026-08-06 8:30 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 07/17] riscv: Maintain epc on misaligned emulation error Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:55 ` sashiko-bot
2026-08-06 8:38 ` Nam Cao
2026-08-06 8:38 ` Nam Cao
2026-08-06 8:38 ` Nam Cao
2026-08-06 16:36 ` Damien Le Moal
2026-08-06 16:36 ` Damien Le Moal
2026-08-06 16:36 ` Damien Le Moal
2026-07-08 3:34 ` [PATCH v3 08/17] riscv: Use generated instruction headers for misaligned loads/stores Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:49 ` sashiko-bot
2026-08-06 14:45 ` Nam Cao
2026-08-06 14:45 ` Nam Cao
2026-08-06 14:45 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 09/17] riscv: kvm: Use generated instruction headers for csr code Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:48 ` sashiko-bot
2026-08-06 15:04 ` Nam Cao
2026-08-06 15:04 ` Nam Cao
2026-08-06 15:04 ` Nam Cao
2026-07-08 3:34 ` [PATCH v3 10/17] KVM: device: Add test device Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:48 ` sashiko-bot
2026-07-08 3:34 ` [PATCH v3 11/17] KVM: riscv: selftests: Add mmio test Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:59 ` sashiko-bot
2026-07-08 3:34 ` [PATCH v3 12/17] riscv: kvm: Use generated instruction headers for mmio emulation Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 4:01 ` sashiko-bot
2026-07-08 3:34 ` [PATCH v3 13/17] riscv: kvm: Add emulated test csr Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 4:00 ` sashiko-bot
2026-07-08 3:34 ` [PATCH v3 14/17] KVM: riscv: selftests: Add csr emulation test Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:58 ` sashiko-bot
2026-07-08 3:34 ` [PATCH v3 15/17] riscv: kvm: Use generated instruction headers for csr emulation Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 4:04 ` sashiko-bot
2026-07-08 3:34 ` [PATCH v3 16/17] riscv: kexec: Use generated instruction headers for kexec relocations Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 4:01 ` sashiko-bot
2026-07-08 3:34 ` [PATCH v3 17/17] riscv: Remove unused instruction headers Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 3:34 ` Charlie Jenkins
2026-07-08 4:09 ` sashiko-bot
2026-07-09 6:26 ` [syzbot ci] Re: riscv: Generate riscv instruction functions syzbot ci
2026-07-09 6:26 ` syzbot ci
2026-07-09 6:26 ` syzbot ci
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