From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <rth@twiddle.net>
Subject: Re: [PATCH 03/27] Make address_space_translate{,_cached}() take a MemTxAttrs argument
Date: Tue, 22 May 2018 11:49:17 +0100 [thread overview]
Message-ID: <87lgccufrm.fsf@linaro.org> (raw)
In-Reply-To: <20180521140402.23318-4-peter.maydell@linaro.org>
Peter Maydell <peter.maydell@linaro.org> writes:
> As part of plumbing MemTxAttrs down to the IOMMU translate method,
> add MemTxAttrs as an argument to address_space_translate()
> and address_space_translate_cached(). Callers either have an
> attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Following the chain down I discovered yet another set of not quite
templates leading to the bottom, but not this patches fault...
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/exec/memory.h | 4 +++-
> accel/tcg/translate-all.c | 2 +-
> exec.c | 14 +++++++++-----
> hw/vfio/common.c | 3 ++-
> memory_ldst.inc.c | 18 +++++++++---------
> target/riscv/helper.c | 2 +-
> 6 files changed, 25 insertions(+), 18 deletions(-)
>
> diff --git a/include/exec/memory.h b/include/exec/memory.h
> index cce355d2d8..9a30a1bb9e 100644
> --- a/include/exec/memory.h
> +++ b/include/exec/memory.h
> @@ -1908,6 +1908,7 @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
> * #MemoryRegion.
> * @len: pointer to length
> * @is_write: indicates the transfer direction
> + * @attrs: memory attributes
> */
> MemoryRegion *flatview_translate(FlatView *fv,
> hwaddr addr, hwaddr *xlat,
> @@ -1915,7 +1916,8 @@ MemoryRegion *flatview_translate(FlatView *fv,
>
> static inline MemoryRegion *address_space_translate(AddressSpace *as,
> hwaddr addr, hwaddr *xlat,
> - hwaddr *len, bool is_write)
> + hwaddr *len, bool is_write,
> + MemTxAttrs attrs)
> {
> return flatview_translate(address_space_to_flatview(as),
> addr, xlat, len, is_write);
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index f04a922ef7..52f7bd59a9 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -1679,7 +1679,7 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
> hwaddr l = 1;
>
> rcu_read_lock();
> - mr = address_space_translate(as, addr, &addr, &l, false);
> + mr = address_space_translate(as, addr, &addr, &l, false, attrs);
> if (!(memory_region_is_ram(mr)
> || memory_region_is_romd(mr))) {
> rcu_read_unlock();
> diff --git a/exec.c b/exec.c
> index c3a197e67b..d314c7cc39 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -3322,7 +3322,8 @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
> rcu_read_lock();
> while (len > 0) {
> l = len;
> - mr = address_space_translate(as, addr, &addr1, &l, true);
> + mr = address_space_translate(as, addr, &addr1, &l, true,
> + MEMTXATTRS_UNSPECIFIED);
>
> if (!(memory_region_is_ram(mr) ||
> memory_region_is_romd(mr))) {
> @@ -3699,7 +3700,7 @@ void address_space_cache_destroy(MemoryRegionCache *cache)
> */
> static inline MemoryRegion *address_space_translate_cached(
> MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
> - hwaddr *plen, bool is_write)
> + hwaddr *plen, bool is_write, MemTxAttrs attrs)
> {
> MemoryRegionSection section;
> MemoryRegion *mr;
> @@ -3733,7 +3734,8 @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
> MemoryRegion *mr;
>
> l = len;
> - mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
> + mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
> + MEMTXATTRS_UNSPECIFIED);
> flatview_read_continue(cache->fv,
> addr, MEMTXATTRS_UNSPECIFIED, buf, len,
> addr1, l, mr);
> @@ -3750,7 +3752,8 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
> MemoryRegion *mr;
>
> l = len;
> - mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
> + mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
> + MEMTXATTRS_UNSPECIFIED);
> flatview_write_continue(cache->fv,
> addr, MEMTXATTRS_UNSPECIFIED, buf, len,
> addr1, l, mr);
> @@ -3848,7 +3851,8 @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
>
> rcu_read_lock();
> mr = address_space_translate(&address_space_memory,
> - phys_addr, &phys_addr, &l, false);
> + phys_addr, &phys_addr, &l, false,
> + MEMTXATTRS_UNSPECIFIED);
>
> res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
> rcu_read_unlock();
> diff --git a/hw/vfio/common.c b/hw/vfio/common.c
> index 07ffa0ba10..8e57265edf 100644
> --- a/hw/vfio/common.c
> +++ b/hw/vfio/common.c
> @@ -324,7 +324,8 @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
> */
> mr = address_space_translate(&address_space_memory,
> iotlb->translated_addr,
> - &xlat, &len, writable);
> + &xlat, &len, writable,
> + MEMTXATTRS_UNSPECIFIED);
> if (!memory_region_is_ram(mr)) {
> error_report("iommu map to non memory area %"HWADDR_PRIx"",
> xlat);
> diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
> index 25d6125747..15483987fe 100644
> --- a/memory_ldst.inc.c
> +++ b/memory_ldst.inc.c
> @@ -33,7 +33,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, false);
> + mr = TRANSLATE(addr, &addr1, &l, false, attrs);
> if (l < 4 || !IS_DIRECT(mr, false)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -109,7 +109,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, false);
> + mr = TRANSLATE(addr, &addr1, &l, false, attrs);
> if (l < 8 || !IS_DIRECT(mr, false)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -183,7 +183,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, false);
> + mr = TRANSLATE(addr, &addr1, &l, false, attrs);
> if (!IS_DIRECT(mr, false)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -219,7 +219,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, false);
> + mr = TRANSLATE(addr, &addr1, &l, false, attrs);
> if (l < 2 || !IS_DIRECT(mr, false)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -296,7 +296,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, true);
> + mr = TRANSLATE(addr, &addr1, &l, true, attrs);
> if (l < 4 || !IS_DIRECT(mr, true)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -333,7 +333,7 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, true);
> + mr = TRANSLATE(addr, &addr1, &l, true, attrs);
> if (l < 4 || !IS_DIRECT(mr, true)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -405,7 +405,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, true);
> + mr = TRANSLATE(addr, &addr1, &l, true, attrs);
> if (!IS_DIRECT(mr, true)) {
> release_lock |= prepare_mmio_access(mr);
> r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
> @@ -438,7 +438,7 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, true);
> + mr = TRANSLATE(addr, &addr1, &l, true, attrs);
> if (l < 2 || !IS_DIRECT(mr, true)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -511,7 +511,7 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, true);
> + mr = TRANSLATE(addr, &addr1, &l, true, attrs);
> if (l < 8 || !IS_DIRECT(mr, true)) {
> release_lock |= prepare_mmio_access(mr);
>
> diff --git a/target/riscv/helper.c b/target/riscv/helper.c
> index 95889f23b9..29e1a603dc 100644
> --- a/target/riscv/helper.c
> +++ b/target/riscv/helper.c
> @@ -210,7 +210,7 @@ restart:
> MemoryRegion *mr;
> hwaddr l = sizeof(target_ulong), addr1;
> mr = address_space_translate(cs->as, pte_addr,
> - &addr1, &l, false);
> + &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
> if (memory_access_is_direct(mr, true)) {
> target_ulong *pte_pa =
> qemu_map_ram_ptr(mr->ram_block, addr1);
--
Alex Bennée
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH 03/27] Make address_space_translate{, _cached}() take a MemTxAttrs argument
Date: Tue, 22 May 2018 11:49:17 +0100 [thread overview]
Message-ID: <87lgccufrm.fsf@linaro.org> (raw)
In-Reply-To: <20180521140402.23318-4-peter.maydell@linaro.org>
Peter Maydell <peter.maydell@linaro.org> writes:
> As part of plumbing MemTxAttrs down to the IOMMU translate method,
> add MemTxAttrs as an argument to address_space_translate()
> and address_space_translate_cached(). Callers either have an
> attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Following the chain down I discovered yet another set of not quite
templates leading to the bottom, but not this patches fault...
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/exec/memory.h | 4 +++-
> accel/tcg/translate-all.c | 2 +-
> exec.c | 14 +++++++++-----
> hw/vfio/common.c | 3 ++-
> memory_ldst.inc.c | 18 +++++++++---------
> target/riscv/helper.c | 2 +-
> 6 files changed, 25 insertions(+), 18 deletions(-)
>
> diff --git a/include/exec/memory.h b/include/exec/memory.h
> index cce355d2d8..9a30a1bb9e 100644
> --- a/include/exec/memory.h
> +++ b/include/exec/memory.h
> @@ -1908,6 +1908,7 @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
> * #MemoryRegion.
> * @len: pointer to length
> * @is_write: indicates the transfer direction
> + * @attrs: memory attributes
> */
> MemoryRegion *flatview_translate(FlatView *fv,
> hwaddr addr, hwaddr *xlat,
> @@ -1915,7 +1916,8 @@ MemoryRegion *flatview_translate(FlatView *fv,
>
> static inline MemoryRegion *address_space_translate(AddressSpace *as,
> hwaddr addr, hwaddr *xlat,
> - hwaddr *len, bool is_write)
> + hwaddr *len, bool is_write,
> + MemTxAttrs attrs)
> {
> return flatview_translate(address_space_to_flatview(as),
> addr, xlat, len, is_write);
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index f04a922ef7..52f7bd59a9 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -1679,7 +1679,7 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
> hwaddr l = 1;
>
> rcu_read_lock();
> - mr = address_space_translate(as, addr, &addr, &l, false);
> + mr = address_space_translate(as, addr, &addr, &l, false, attrs);
> if (!(memory_region_is_ram(mr)
> || memory_region_is_romd(mr))) {
> rcu_read_unlock();
> diff --git a/exec.c b/exec.c
> index c3a197e67b..d314c7cc39 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -3322,7 +3322,8 @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
> rcu_read_lock();
> while (len > 0) {
> l = len;
> - mr = address_space_translate(as, addr, &addr1, &l, true);
> + mr = address_space_translate(as, addr, &addr1, &l, true,
> + MEMTXATTRS_UNSPECIFIED);
>
> if (!(memory_region_is_ram(mr) ||
> memory_region_is_romd(mr))) {
> @@ -3699,7 +3700,7 @@ void address_space_cache_destroy(MemoryRegionCache *cache)
> */
> static inline MemoryRegion *address_space_translate_cached(
> MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
> - hwaddr *plen, bool is_write)
> + hwaddr *plen, bool is_write, MemTxAttrs attrs)
> {
> MemoryRegionSection section;
> MemoryRegion *mr;
> @@ -3733,7 +3734,8 @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
> MemoryRegion *mr;
>
> l = len;
> - mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
> + mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
> + MEMTXATTRS_UNSPECIFIED);
> flatview_read_continue(cache->fv,
> addr, MEMTXATTRS_UNSPECIFIED, buf, len,
> addr1, l, mr);
> @@ -3750,7 +3752,8 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
> MemoryRegion *mr;
>
> l = len;
> - mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
> + mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
> + MEMTXATTRS_UNSPECIFIED);
> flatview_write_continue(cache->fv,
> addr, MEMTXATTRS_UNSPECIFIED, buf, len,
> addr1, l, mr);
> @@ -3848,7 +3851,8 @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
>
> rcu_read_lock();
> mr = address_space_translate(&address_space_memory,
> - phys_addr, &phys_addr, &l, false);
> + phys_addr, &phys_addr, &l, false,
> + MEMTXATTRS_UNSPECIFIED);
>
> res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
> rcu_read_unlock();
> diff --git a/hw/vfio/common.c b/hw/vfio/common.c
> index 07ffa0ba10..8e57265edf 100644
> --- a/hw/vfio/common.c
> +++ b/hw/vfio/common.c
> @@ -324,7 +324,8 @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
> */
> mr = address_space_translate(&address_space_memory,
> iotlb->translated_addr,
> - &xlat, &len, writable);
> + &xlat, &len, writable,
> + MEMTXATTRS_UNSPECIFIED);
> if (!memory_region_is_ram(mr)) {
> error_report("iommu map to non memory area %"HWADDR_PRIx"",
> xlat);
> diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
> index 25d6125747..15483987fe 100644
> --- a/memory_ldst.inc.c
> +++ b/memory_ldst.inc.c
> @@ -33,7 +33,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, false);
> + mr = TRANSLATE(addr, &addr1, &l, false, attrs);
> if (l < 4 || !IS_DIRECT(mr, false)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -109,7 +109,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, false);
> + mr = TRANSLATE(addr, &addr1, &l, false, attrs);
> if (l < 8 || !IS_DIRECT(mr, false)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -183,7 +183,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, false);
> + mr = TRANSLATE(addr, &addr1, &l, false, attrs);
> if (!IS_DIRECT(mr, false)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -219,7 +219,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, false);
> + mr = TRANSLATE(addr, &addr1, &l, false, attrs);
> if (l < 2 || !IS_DIRECT(mr, false)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -296,7 +296,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, true);
> + mr = TRANSLATE(addr, &addr1, &l, true, attrs);
> if (l < 4 || !IS_DIRECT(mr, true)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -333,7 +333,7 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, true);
> + mr = TRANSLATE(addr, &addr1, &l, true, attrs);
> if (l < 4 || !IS_DIRECT(mr, true)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -405,7 +405,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, true);
> + mr = TRANSLATE(addr, &addr1, &l, true, attrs);
> if (!IS_DIRECT(mr, true)) {
> release_lock |= prepare_mmio_access(mr);
> r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
> @@ -438,7 +438,7 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, true);
> + mr = TRANSLATE(addr, &addr1, &l, true, attrs);
> if (l < 2 || !IS_DIRECT(mr, true)) {
> release_lock |= prepare_mmio_access(mr);
>
> @@ -511,7 +511,7 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
> bool release_lock = false;
>
> RCU_READ_LOCK();
> - mr = TRANSLATE(addr, &addr1, &l, true);
> + mr = TRANSLATE(addr, &addr1, &l, true, attrs);
> if (l < 8 || !IS_DIRECT(mr, true)) {
> release_lock |= prepare_mmio_access(mr);
>
> diff --git a/target/riscv/helper.c b/target/riscv/helper.c
> index 95889f23b9..29e1a603dc 100644
> --- a/target/riscv/helper.c
> +++ b/target/riscv/helper.c
> @@ -210,7 +210,7 @@ restart:
> MemoryRegion *mr;
> hwaddr l = sizeof(target_ulong), addr1;
> mr = address_space_translate(cs->as, pte_addr,
> - &addr1, &l, false);
> + &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
> if (memory_access_is_direct(mr, true)) {
> target_ulong *pte_pa =
> qemu_map_ram_ptr(mr->ram_block, addr1);
--
Alex Bennée
next prev parent reply other threads:[~2018-05-22 10:49 UTC|newest]
Thread overview: 191+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-21 14:03 [PATCH 00/27] iommu: support txattrs, support TCG execution, implement TZ MPC Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-21 14:03 ` [PATCH 01/27] memory.h: Improve IOMMU related documentation Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-21 19:46 ` Richard Henderson
2018-05-21 19:46 ` [Qemu-devel] " Richard Henderson
2018-05-22 9:16 ` Alex Bennée
2018-05-22 9:16 ` [Qemu-devel] " Alex Bennée
2018-05-22 11:40 ` Auger Eric
2018-05-21 14:03 ` [PATCH 02/27] Make tb_invalidate_phys_addr() take a MemTxAttrs argument Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-21 23:54 ` Richard Henderson
2018-05-21 23:54 ` [Qemu-devel] " Richard Henderson
2018-05-22 9:21 ` Alex Bennée
2018-05-22 9:21 ` [Qemu-devel] " Alex Bennée
2018-05-21 14:03 ` [PATCH 03/27] Make address_space_translate{,_cached}() " Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] [PATCH 03/27] Make address_space_translate{, _cached}() " Peter Maydell
2018-05-22 10:49 ` Alex Bennée [this message]
2018-05-22 10:49 ` Alex Bennée
2018-05-22 16:12 ` [PATCH 03/27] Make address_space_translate{,_cached}() " Richard Henderson
2018-05-22 16:12 ` [Qemu-devel] [PATCH 03/27] Make address_space_translate{, _cached}() " Richard Henderson
2018-05-21 14:03 ` [PATCH 04/27] Make address_space_map() " Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 10:49 ` Alex Bennée
2018-05-22 10:49 ` [Qemu-devel] " Alex Bennée
2018-05-22 16:13 ` Richard Henderson
2018-05-22 16:13 ` [Qemu-devel] " Richard Henderson
2018-05-21 14:03 ` [PATCH 05/27] Make address_space_access_valid() " Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 10:50 ` Alex Bennée
2018-05-22 10:50 ` [Qemu-devel] " Alex Bennée
2018-05-22 16:14 ` Richard Henderson
2018-05-22 16:14 ` [Qemu-devel] " Richard Henderson
2018-05-21 14:03 ` [PATCH 06/27] Make flatview_extend_translation() " Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 10:56 ` Alex Bennée
2018-05-22 10:56 ` [Qemu-devel] " Alex Bennée
2018-05-22 16:15 ` Richard Henderson
2018-05-22 16:15 ` [Qemu-devel] " Richard Henderson
2018-05-21 14:03 ` [PATCH 07/27] Make memory_region_access_valid() " Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 10:57 ` Alex Bennée
2018-05-22 10:57 ` [Qemu-devel] " Alex Bennée
2018-05-22 16:17 ` Richard Henderson
2018-05-22 16:17 ` [Qemu-devel] " Richard Henderson
2018-05-21 14:03 ` [PATCH 08/27] Make MemoryRegion valid.accepts callback " Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 10:58 ` Alex Bennée
2018-05-22 10:58 ` [Qemu-devel] " Alex Bennée
2018-05-22 16:20 ` Richard Henderson
2018-05-22 16:20 ` [Qemu-devel] " Richard Henderson
2018-05-21 14:03 ` [PATCH 09/27] Make flatview_access_valid() " Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 10:58 ` Alex Bennée
2018-05-22 10:58 ` [Qemu-devel] " Alex Bennée
2018-05-22 16:33 ` Richard Henderson
2018-05-22 16:33 ` [Qemu-devel] " Richard Henderson
2018-05-22 16:37 ` Peter Maydell
2018-05-22 16:37 ` [Qemu-devel] " Peter Maydell
2018-05-21 14:03 ` [PATCH 10/27] Make flatview_translate() " Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 10:58 ` Alex Bennée
2018-05-22 10:58 ` [Qemu-devel] " Alex Bennée
2018-05-22 16:33 ` Richard Henderson
2018-05-22 16:33 ` [Qemu-devel] " Richard Henderson
2018-05-21 14:03 ` [PATCH 11/27] Make address_space_get_iotlb_entry() " Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 11:00 ` Alex Bennée
2018-05-22 11:00 ` [Qemu-devel] " Alex Bennée
2018-05-22 17:29 ` Richard Henderson
2018-05-22 17:29 ` [Qemu-devel] " Richard Henderson
2018-05-21 14:03 ` [PATCH 12/27] Make flatview_do_translate() " Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 11:00 ` Alex Bennée
2018-05-22 11:00 ` [Qemu-devel] " Alex Bennée
2018-05-22 17:29 ` Richard Henderson
2018-05-22 17:29 ` [Qemu-devel] " Richard Henderson
2018-05-21 14:03 ` [PATCH 13/27] Make address_space_translate_iommu " Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 11:00 ` Alex Bennée
2018-05-22 11:00 ` [Qemu-devel] " Alex Bennée
2018-05-22 17:30 ` Richard Henderson
2018-05-22 17:30 ` [Qemu-devel] " Richard Henderson
2018-05-21 14:03 ` [PATCH 14/27] iommu: Add IOMMU index concept to IOMMU API Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 3:03 ` Peter Xu
2018-05-22 8:40 ` Peter Maydell
2018-05-22 11:02 ` Peter Xu
2018-05-22 11:11 ` Peter Maydell
2018-05-23 1:06 ` Peter Xu
2018-05-23 11:47 ` Peter Maydell
2018-05-24 6:23 ` Peter Xu
2018-05-24 10:54 ` Peter Maydell
2018-05-25 2:50 ` Peter Xu
2018-05-25 9:27 ` Auger Eric
2018-05-25 9:34 ` Peter Maydell
2018-05-22 12:58 ` Auger Eric
2018-05-22 13:22 ` Peter Maydell
2018-05-22 14:11 ` Auger Eric
2018-05-22 14:19 ` Peter Maydell
2018-05-22 14:22 ` Auger Eric
2018-05-22 17:42 ` Richard Henderson
2018-05-22 17:42 ` [Qemu-devel] " Richard Henderson
2018-05-22 17:51 ` Peter Maydell
2018-05-22 17:51 ` [Qemu-devel] " Peter Maydell
2018-05-22 17:52 ` Richard Henderson
2018-05-22 17:52 ` [Qemu-devel] " Richard Henderson
2018-05-21 14:03 ` [PATCH 15/27] iommu: Add IOMMU index argument to notifier APIs Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 17:45 ` Richard Henderson
2018-05-22 17:45 ` [Qemu-devel] " Richard Henderson
2018-05-23 9:08 ` Alex Bennée
2018-05-23 9:08 ` [Qemu-devel] " Alex Bennée
2018-06-04 13:03 ` Peter Maydell
2018-06-04 13:03 ` [Qemu-devel] " Peter Maydell
2018-06-04 15:09 ` Alex Bennée
2018-06-04 15:09 ` [Qemu-devel] " Alex Bennée
2018-06-04 15:23 ` Peter Maydell
2018-06-04 15:23 ` [Qemu-devel] " Peter Maydell
2018-05-24 15:29 ` Auger Eric
2018-05-24 17:03 ` Peter Maydell
2018-05-24 19:13 ` Auger Eric
2018-05-21 14:03 ` [PATCH 16/27] iommu: Add IOMMU index argument to translate method Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 18:06 ` Richard Henderson
2018-05-22 18:06 ` [Qemu-devel] " Richard Henderson
2018-05-23 9:11 ` Alex Bennée
2018-05-23 9:11 ` [Qemu-devel] " Alex Bennée
2018-05-21 14:03 ` [PATCH 17/27] exec.c: Handle IOMMUs in address_space_translate_for_iotlb() Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-23 9:51 ` Alex Bennée
2018-05-23 9:51 ` [Qemu-devel] " Alex Bennée
2018-05-23 11:52 ` Peter Maydell
2018-05-23 11:52 ` [Qemu-devel] " Peter Maydell
2018-05-24 19:54 ` Auger Eric
2018-05-25 8:52 ` Peter Maydell
2018-05-25 9:50 ` Auger Eric
2018-05-25 9:59 ` Peter Maydell
2018-05-21 14:03 ` [PATCH 18/27] hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-22 11:30 ` Auger Eric
2018-05-22 11:56 ` Peter Maydell
2018-05-22 12:23 ` Auger Eric
2018-05-23 10:41 ` Alex Bennée
2018-05-23 10:41 ` [Qemu-devel] " Alex Bennée
2018-05-21 14:03 ` [PATCH 19/27] hw/misc/tz-mpc.c: Implement registers Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-23 10:44 ` Alex Bennée
2018-05-23 10:44 ` [Qemu-devel] " Alex Bennée
2018-05-21 14:03 ` [PATCH 20/27] hw/misc/tz-mpc.c: Implement correct blocked-access behaviour Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-23 10:49 ` Alex Bennée
2018-05-23 10:49 ` [Qemu-devel] " Alex Bennée
2018-05-23 11:54 ` Peter Maydell
2018-05-23 11:54 ` [Qemu-devel] " Peter Maydell
2018-05-21 14:03 ` [PATCH 21/27] hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-21 14:03 ` [PATCH 22/27] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-23 11:01 ` Alex Bennée
2018-05-23 11:01 ` [Qemu-devel] " Alex Bennée
2018-05-21 14:03 ` [PATCH 23/27] hw/core/or-irq: Support more than 16 inputs to an OR gate Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-21 14:34 ` Paolo Bonzini
2018-05-21 14:34 ` [Qemu-devel] " Paolo Bonzini
2018-05-21 15:02 ` Peter Maydell
2018-05-21 15:02 ` [Qemu-devel] " Peter Maydell
2018-05-30 16:59 ` Paolo Bonzini
2018-05-30 17:35 ` Peter Maydell
2018-05-31 10:21 ` Paolo Bonzini
2018-05-31 10:50 ` Peter Maydell
2018-05-31 11:50 ` Paolo Bonzini
2018-05-31 11:59 ` Peter Maydell
2018-05-21 14:03 ` [PATCH 24/27] hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS Peter Maydell
2018-05-21 14:03 ` [Qemu-devel] " Peter Maydell
2018-05-21 14:04 ` [PATCH 25/27] hw/arm/iotkit: Instantiate MPC Peter Maydell
2018-05-21 14:04 ` [Qemu-devel] " Peter Maydell
2018-05-23 11:38 ` Alex Bennée
2018-05-23 11:38 ` [Qemu-devel] " Alex Bennée
2018-05-21 14:04 ` [PATCH 26/27] hw/arm/iotkit: Wire up MPC interrupt lines Peter Maydell
2018-05-21 14:04 ` [Qemu-devel] " Peter Maydell
2018-05-23 11:39 ` Alex Bennée
2018-05-23 11:39 ` [Qemu-devel] " Alex Bennée
2018-05-21 14:04 ` [PATCH 27/27] hw/arm/mps2-tz.c: Instantiate MPCs Peter Maydell
2018-05-21 14:04 ` [Qemu-devel] " Peter Maydell
2018-05-23 11:41 ` Alex Bennée
2018-05-23 11:41 ` [Qemu-devel] " Alex Bennée
2018-05-21 15:10 ` [Qemu-devel] [PATCH 00/27] iommu: support txattrs, support TCG execution, implement TZ MPC no-reply
2018-05-30 16:58 ` Paolo Bonzini
2018-05-31 9:54 ` Peter Maydell
2018-05-31 13:37 ` Peter Maydell
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