* [PATCH 1/2] drm/i915/glk: Calculate high/low switch count for GLK
@ 2017-05-09 13:29 Madhav Chauhan
2017-05-09 13:29 ` [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI Madhav Chauhan
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Madhav Chauhan @ 2017-05-09 13:29 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ander.conselvan.de.oliveira, shashidhar.hiremath
As per BSPEC, high/low switch count to be programmed in
terms of byteclock using exit_zero_count and prep_count.
For Geminilake exit/prep counts are already calculated
in terms of byteclock. This patch calculates high/low
switch count using counts value in byteclock, old calculation
leads to screen flicker/shift issue while resuming from S3/S4.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 0dce779..7158c7c 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -694,8 +694,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
clk_zero_cnt << 8 | prepare_cnt;
/*
- * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
- * + 10UI + Extra Byte Count
+ * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
+ * mul + 10UI + Extra Byte Count
*
* HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
* Extra Byte Count is calculated according to number of lanes.
@@ -708,8 +708,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
/* B044 */
/* FIXME:
* The comment above does not match with the code */
- lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
- exit_zero_cnt * 2 + 10, 8);
+ lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
+ exit_zero_cnt * mul + 10, 8);
hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
--
1.9.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI 2017-05-09 13:29 [PATCH 1/2] drm/i915/glk: Calculate high/low switch count for GLK Madhav Chauhan @ 2017-05-09 13:29 ` Madhav Chauhan 2017-05-09 13:58 ` Ville Syrjälä 2017-05-09 14:09 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/glk: Calculate high/low switch count for GLK Patchwork 2017-05-15 15:48 ` [PATCH 1/2] " Jani Nikula 2 siblings, 1 reply; 12+ messages in thread From: Madhav Chauhan @ 2017-05-09 13:29 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, ander.conselvan.de.oliveira, shashidhar.hiremath As per BSEPC, if device ready bit is '0' in enable IO sequence then its a cold boot/reset scenario eg: S3/S4 resume. In these conditions we need to program certain registers and prepare port from the middle of DSI enable sequence otherwise feature like S3/S4 doesn't work. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> --- drivers/gpu/drm/i915/intel_dsi.c | 79 ++++++++++++++++++++++++---------------- 1 file changed, 48 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index fc0ef49..6b68864 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -346,12 +346,17 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, return true; } -static void glk_dsi_device_ready(struct intel_encoder *encoder) +static void intel_dsi_prepare(struct intel_encoder *intel_encoder, + struct intel_crtc_state *pipe_config); + +static void glk_dsi_device_ready(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); enum port port; u32 tmp, val; + bool cold_boot = false; /* Set the MIPI mode * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. @@ -370,7 +375,10 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) /* Program LP Wake */ for_each_dsi_port(port, intel_dsi->ports) { tmp = I915_READ(MIPI_CTRL(port)); - tmp |= GLK_LP_WAKE; + if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) + tmp &= ~GLK_LP_WAKE; + else + tmp |= GLK_LP_WAKE; I915_WRITE(MIPI_CTRL(port), tmp); } @@ -382,6 +390,15 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) DRM_ERROR("MIPIO port is powergated\n"); } + /* Check if cold boot scenario */ + for_each_dsi_port(port, intel_dsi->ports) { + cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) & + DEVICE_READY); + } + + if (cold_boot) + intel_dsi_prepare(encoder, pipe_config); + /* Wait for MIPI PHY status bit to set */ for_each_dsi_port(port, intel_dsi->ports) { if (intel_wait_for_register(dev_priv, @@ -402,34 +419,34 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) val |= DEVICE_READY; I915_WRITE(MIPI_DEVICE_READY(port), val); usleep_range(10, 15); - } - - /* Enter ULPS */ - val = I915_READ(MIPI_DEVICE_READY(port)); - val &= ~ULPS_STATE_MASK; - val |= (ULPS_STATE_ENTER | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); + } else { + /* Enter ULPS */ + val = I915_READ(MIPI_DEVICE_READY(port)); + val &= ~ULPS_STATE_MASK; + val |= (ULPS_STATE_ENTER | DEVICE_READY); + I915_WRITE(MIPI_DEVICE_READY(port), val); - /* Wait for ULPS active */ - if (intel_wait_for_register(dev_priv, + /* Wait for ULPS active */ + if (intel_wait_for_register(dev_priv, MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20)) - DRM_ERROR("ULPS not active\n"); + DRM_ERROR("ULPS not active\n"); - /* Exit ULPS */ - val = I915_READ(MIPI_DEVICE_READY(port)); - val &= ~ULPS_STATE_MASK; - val |= (ULPS_STATE_EXIT | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); + /* Exit ULPS */ + val = I915_READ(MIPI_DEVICE_READY(port)); + val &= ~ULPS_STATE_MASK; + val |= (ULPS_STATE_EXIT | DEVICE_READY); + I915_WRITE(MIPI_DEVICE_READY(port), val); - /* Enter Normal Mode */ - val = I915_READ(MIPI_DEVICE_READY(port)); - val &= ~ULPS_STATE_MASK; - val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); + /* Enter Normal Mode */ + val = I915_READ(MIPI_DEVICE_READY(port)); + val &= ~ULPS_STATE_MASK; + val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); + I915_WRITE(MIPI_DEVICE_READY(port), val); - tmp = I915_READ(MIPI_CTRL(port)); - tmp &= ~GLK_LP_WAKE; - I915_WRITE(MIPI_CTRL(port), tmp); + tmp = I915_READ(MIPI_CTRL(port)); + tmp &= ~GLK_LP_WAKE; + I915_WRITE(MIPI_CTRL(port), tmp); + } } /* Wait for Stop state */ @@ -515,7 +532,8 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) } } -static void intel_dsi_device_ready(struct intel_encoder *encoder) +static void intel_dsi_device_ready(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -524,7 +542,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) else if (IS_BROXTON(dev_priv)) bxt_dsi_device_ready(encoder); else if (IS_GEMINILAKE(dev_priv)) - glk_dsi_device_ready(encoder); + glk_dsi_device_ready(encoder, pipe_config); } static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) @@ -710,8 +728,6 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) } } -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, - struct intel_crtc_state *pipe_config); static void intel_dsi_unprepare(struct intel_encoder *encoder); static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) @@ -800,7 +816,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, I915_WRITE(DSPCLK_GATE_D, val); } - intel_dsi_prepare(encoder, pipe_config); + if (!IS_GEMINILAKE(dev_priv)) + intel_dsi_prepare(encoder, pipe_config); /* Power on, try both CRC pmic gpio and VBT */ if (intel_dsi->gpio_panel) @@ -812,7 +829,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); /* Put device in ready state (LP-11) */ - intel_dsi_device_ready(encoder); + intel_dsi_device_ready(encoder, pipe_config); /* Send initialization commands in LP mode */ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI 2017-05-09 13:29 ` [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI Madhav Chauhan @ 2017-05-09 13:58 ` Ville Syrjälä 2017-05-15 15:49 ` Jani Nikula 0 siblings, 1 reply; 12+ messages in thread From: Ville Syrjälä @ 2017-05-09 13:58 UTC (permalink / raw) To: Madhav Chauhan Cc: jani.nikula, ander.conselvan.de.oliveira, intel-gfx, shashidhar.hiremath On Tue, May 09, 2017 at 06:59:25PM +0530, Madhav Chauhan wrote: > As per BSEPC, if device ready bit is '0' in enable IO sequence > then its a cold boot/reset scenario eg: S3/S4 resume. In these > conditions we need to program certain registers and prepare port > from the middle of DSI enable sequence otherwise feature like S3/S4 > doesn't work. Can't we just always follow the "cold boot" sequence? Less codepaths means less bugs. > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi.c | 79 ++++++++++++++++++++++++---------------- > 1 file changed, 48 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index fc0ef49..6b68864 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -346,12 +346,17 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, > return true; > } > > -static void glk_dsi_device_ready(struct intel_encoder *encoder) > +static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > + struct intel_crtc_state *pipe_config); > + > +static void glk_dsi_device_ready(struct intel_encoder *encoder, > + struct intel_crtc_state *pipe_config) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > enum port port; > u32 tmp, val; > + bool cold_boot = false; > > /* Set the MIPI mode > * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. > @@ -370,7 +375,10 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) > /* Program LP Wake */ > for_each_dsi_port(port, intel_dsi->ports) { > tmp = I915_READ(MIPI_CTRL(port)); > - tmp |= GLK_LP_WAKE; > + if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) > + tmp &= ~GLK_LP_WAKE; > + else > + tmp |= GLK_LP_WAKE; > I915_WRITE(MIPI_CTRL(port), tmp); > } > > @@ -382,6 +390,15 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) > DRM_ERROR("MIPIO port is powergated\n"); > } > > + /* Check if cold boot scenario */ > + for_each_dsi_port(port, intel_dsi->ports) { > + cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) & > + DEVICE_READY); > + } > + > + if (cold_boot) > + intel_dsi_prepare(encoder, pipe_config); > + > /* Wait for MIPI PHY status bit to set */ > for_each_dsi_port(port, intel_dsi->ports) { > if (intel_wait_for_register(dev_priv, > @@ -402,34 +419,34 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) > val |= DEVICE_READY; > I915_WRITE(MIPI_DEVICE_READY(port), val); > usleep_range(10, 15); > - } > - > - /* Enter ULPS */ > - val = I915_READ(MIPI_DEVICE_READY(port)); > - val &= ~ULPS_STATE_MASK; > - val |= (ULPS_STATE_ENTER | DEVICE_READY); > - I915_WRITE(MIPI_DEVICE_READY(port), val); > + } else { > + /* Enter ULPS */ > + val = I915_READ(MIPI_DEVICE_READY(port)); > + val &= ~ULPS_STATE_MASK; > + val |= (ULPS_STATE_ENTER | DEVICE_READY); > + I915_WRITE(MIPI_DEVICE_READY(port), val); > > - /* Wait for ULPS active */ > - if (intel_wait_for_register(dev_priv, > + /* Wait for ULPS active */ > + if (intel_wait_for_register(dev_priv, > MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20)) > - DRM_ERROR("ULPS not active\n"); > + DRM_ERROR("ULPS not active\n"); > > - /* Exit ULPS */ > - val = I915_READ(MIPI_DEVICE_READY(port)); > - val &= ~ULPS_STATE_MASK; > - val |= (ULPS_STATE_EXIT | DEVICE_READY); > - I915_WRITE(MIPI_DEVICE_READY(port), val); > + /* Exit ULPS */ > + val = I915_READ(MIPI_DEVICE_READY(port)); > + val &= ~ULPS_STATE_MASK; > + val |= (ULPS_STATE_EXIT | DEVICE_READY); > + I915_WRITE(MIPI_DEVICE_READY(port), val); > > - /* Enter Normal Mode */ > - val = I915_READ(MIPI_DEVICE_READY(port)); > - val &= ~ULPS_STATE_MASK; > - val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); > - I915_WRITE(MIPI_DEVICE_READY(port), val); > + /* Enter Normal Mode */ > + val = I915_READ(MIPI_DEVICE_READY(port)); > + val &= ~ULPS_STATE_MASK; > + val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); > + I915_WRITE(MIPI_DEVICE_READY(port), val); > > - tmp = I915_READ(MIPI_CTRL(port)); > - tmp &= ~GLK_LP_WAKE; > - I915_WRITE(MIPI_CTRL(port), tmp); > + tmp = I915_READ(MIPI_CTRL(port)); > + tmp &= ~GLK_LP_WAKE; > + I915_WRITE(MIPI_CTRL(port), tmp); > + } > } > > /* Wait for Stop state */ > @@ -515,7 +532,8 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) > } > } > > -static void intel_dsi_device_ready(struct intel_encoder *encoder) > +static void intel_dsi_device_ready(struct intel_encoder *encoder, > + struct intel_crtc_state *pipe_config) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > @@ -524,7 +542,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) > else if (IS_BROXTON(dev_priv)) > bxt_dsi_device_ready(encoder); > else if (IS_GEMINILAKE(dev_priv)) > - glk_dsi_device_ready(encoder); > + glk_dsi_device_ready(encoder, pipe_config); > } > > static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) > @@ -710,8 +728,6 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) > } > } > > -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > - struct intel_crtc_state *pipe_config); > static void intel_dsi_unprepare(struct intel_encoder *encoder); > > static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) > @@ -800,7 +816,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, > I915_WRITE(DSPCLK_GATE_D, val); > } > > - intel_dsi_prepare(encoder, pipe_config); > + if (!IS_GEMINILAKE(dev_priv)) > + intel_dsi_prepare(encoder, pipe_config); > > /* Power on, try both CRC pmic gpio and VBT */ > if (intel_dsi->gpio_panel) > @@ -812,7 +829,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, > intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); > > /* Put device in ready state (LP-11) */ > - intel_dsi_device_ready(encoder); > + intel_dsi_device_ready(encoder, pipe_config); > > /* Send initialization commands in LP mode */ > intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI 2017-05-09 13:58 ` Ville Syrjälä @ 2017-05-15 15:49 ` Jani Nikula 2017-05-15 17:42 ` Chauhan, Madhav 0 siblings, 1 reply; 12+ messages in thread From: Jani Nikula @ 2017-05-15 15:49 UTC (permalink / raw) To: Ville Syrjälä, Madhav Chauhan Cc: ander.conselvan.de.oliveira, intel-gfx, shashidhar.hiremath On Tue, 09 May 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Tue, May 09, 2017 at 06:59:25PM +0530, Madhav Chauhan wrote: >> As per BSEPC, if device ready bit is '0' in enable IO sequence >> then its a cold boot/reset scenario eg: S3/S4 resume. In these >> conditions we need to program certain registers and prepare port >> from the middle of DSI enable sequence otherwise feature like S3/S4 >> doesn't work. > > Can't we just always follow the "cold boot" sequence? Less codepaths > means less bugs. I agree. Madhav? BR, Jani. > >> >> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> >> --- >> drivers/gpu/drm/i915/intel_dsi.c | 79 ++++++++++++++++++++++++---------------- >> 1 file changed, 48 insertions(+), 31 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c >> index fc0ef49..6b68864 100644 >> --- a/drivers/gpu/drm/i915/intel_dsi.c >> +++ b/drivers/gpu/drm/i915/intel_dsi.c >> @@ -346,12 +346,17 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, >> return true; >> } >> >> -static void glk_dsi_device_ready(struct intel_encoder *encoder) >> +static void intel_dsi_prepare(struct intel_encoder *intel_encoder, >> + struct intel_crtc_state *pipe_config); >> + >> +static void glk_dsi_device_ready(struct intel_encoder *encoder, >> + struct intel_crtc_state *pipe_config) >> { >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); >> enum port port; >> u32 tmp, val; >> + bool cold_boot = false; >> >> /* Set the MIPI mode >> * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. >> @@ -370,7 +375,10 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) >> /* Program LP Wake */ >> for_each_dsi_port(port, intel_dsi->ports) { >> tmp = I915_READ(MIPI_CTRL(port)); >> - tmp |= GLK_LP_WAKE; >> + if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) >> + tmp &= ~GLK_LP_WAKE; >> + else >> + tmp |= GLK_LP_WAKE; >> I915_WRITE(MIPI_CTRL(port), tmp); >> } >> >> @@ -382,6 +390,15 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) >> DRM_ERROR("MIPIO port is powergated\n"); >> } >> >> + /* Check if cold boot scenario */ >> + for_each_dsi_port(port, intel_dsi->ports) { >> + cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) & >> + DEVICE_READY); >> + } >> + >> + if (cold_boot) >> + intel_dsi_prepare(encoder, pipe_config); >> + >> /* Wait for MIPI PHY status bit to set */ >> for_each_dsi_port(port, intel_dsi->ports) { >> if (intel_wait_for_register(dev_priv, >> @@ -402,34 +419,34 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) >> val |= DEVICE_READY; >> I915_WRITE(MIPI_DEVICE_READY(port), val); >> usleep_range(10, 15); >> - } >> - >> - /* Enter ULPS */ >> - val = I915_READ(MIPI_DEVICE_READY(port)); >> - val &= ~ULPS_STATE_MASK; >> - val |= (ULPS_STATE_ENTER | DEVICE_READY); >> - I915_WRITE(MIPI_DEVICE_READY(port), val); >> + } else { >> + /* Enter ULPS */ >> + val = I915_READ(MIPI_DEVICE_READY(port)); >> + val &= ~ULPS_STATE_MASK; >> + val |= (ULPS_STATE_ENTER | DEVICE_READY); >> + I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> - /* Wait for ULPS active */ >> - if (intel_wait_for_register(dev_priv, >> + /* Wait for ULPS active */ >> + if (intel_wait_for_register(dev_priv, >> MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20)) >> - DRM_ERROR("ULPS not active\n"); >> + DRM_ERROR("ULPS not active\n"); >> >> - /* Exit ULPS */ >> - val = I915_READ(MIPI_DEVICE_READY(port)); >> - val &= ~ULPS_STATE_MASK; >> - val |= (ULPS_STATE_EXIT | DEVICE_READY); >> - I915_WRITE(MIPI_DEVICE_READY(port), val); >> + /* Exit ULPS */ >> + val = I915_READ(MIPI_DEVICE_READY(port)); >> + val &= ~ULPS_STATE_MASK; >> + val |= (ULPS_STATE_EXIT | DEVICE_READY); >> + I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> - /* Enter Normal Mode */ >> - val = I915_READ(MIPI_DEVICE_READY(port)); >> - val &= ~ULPS_STATE_MASK; >> - val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); >> - I915_WRITE(MIPI_DEVICE_READY(port), val); >> + /* Enter Normal Mode */ >> + val = I915_READ(MIPI_DEVICE_READY(port)); >> + val &= ~ULPS_STATE_MASK; >> + val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); >> + I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> - tmp = I915_READ(MIPI_CTRL(port)); >> - tmp &= ~GLK_LP_WAKE; >> - I915_WRITE(MIPI_CTRL(port), tmp); >> + tmp = I915_READ(MIPI_CTRL(port)); >> + tmp &= ~GLK_LP_WAKE; >> + I915_WRITE(MIPI_CTRL(port), tmp); >> + } >> } >> >> /* Wait for Stop state */ >> @@ -515,7 +532,8 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) >> } >> } >> >> -static void intel_dsi_device_ready(struct intel_encoder *encoder) >> +static void intel_dsi_device_ready(struct intel_encoder *encoder, >> + struct intel_crtc_state *pipe_config) >> { >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> >> @@ -524,7 +542,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) >> else if (IS_BROXTON(dev_priv)) >> bxt_dsi_device_ready(encoder); >> else if (IS_GEMINILAKE(dev_priv)) >> - glk_dsi_device_ready(encoder); >> + glk_dsi_device_ready(encoder, pipe_config); >> } >> >> static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) >> @@ -710,8 +728,6 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) >> } >> } >> >> -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, >> - struct intel_crtc_state *pipe_config); >> static void intel_dsi_unprepare(struct intel_encoder *encoder); >> >> static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) >> @@ -800,7 +816,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, >> I915_WRITE(DSPCLK_GATE_D, val); >> } >> >> - intel_dsi_prepare(encoder, pipe_config); >> + if (!IS_GEMINILAKE(dev_priv)) >> + intel_dsi_prepare(encoder, pipe_config); >> >> /* Power on, try both CRC pmic gpio and VBT */ >> if (intel_dsi->gpio_panel) >> @@ -812,7 +829,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); >> >> /* Put device in ready state (LP-11) */ >> - intel_dsi_device_ready(encoder); >> + intel_dsi_device_ready(encoder, pipe_config); >> >> /* Send initialization commands in LP mode */ >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); >> -- >> 1.9.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI 2017-05-15 15:49 ` Jani Nikula @ 2017-05-15 17:42 ` Chauhan, Madhav 2017-05-24 13:51 ` Jani Nikula 0 siblings, 1 reply; 12+ messages in thread From: Chauhan, Madhav @ 2017-05-15 17:42 UTC (permalink / raw) To: Nikula, Jani, Ville Syrjälä Cc: Conselvan De Oliveira, Ander, intel-gfx@lists.freedesktop.org, Hiremath, Shashidhar > -----Original Message----- > From: Nikula, Jani > Sent: Monday, May 15, 2017 9:19 PM > To: Ville Syrjälä <ville.syrjala@linux.intel.com>; Chauhan, Madhav > <madhav.chauhan@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander > <ander.conselvan.de.oliveira@intel.com>; Hiremath, Shashidhar > <shashidhar.hiremath@intel.com> > Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK > DSI > > On Tue, 09 May 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > > On Tue, May 09, 2017 at 06:59:25PM +0530, Madhav Chauhan wrote: > >> As per BSEPC, if device ready bit is '0' in enable IO sequence then > >> its a cold boot/reset scenario eg: S3/S4 resume. In these conditions > >> we need to program certain registers and prepare port from the middle > >> of DSI enable sequence otherwise feature like S3/S4 doesn't work. > > > > Can't we just always follow the "cold boot" sequence? Less codepaths > > means less bugs. > > I agree. Madhav? Cold Boot scenario represents when DSI controller/IO is not initialized even once before use eg: 1. Connected HDMI boot with DSI panel 2. S3/S4 While normal scenario is: 1. Boot with DSI panel without HDMI. DSI will be initialized once by GOP/BIOS If we use cold boot sequence always, normal scenario doesn’t work as few registers can’t be Programmed as per cold boot scenario. LP_WAKE bit (MIPI_CTRL REG) is one of the example. Moreover, current changes works very well for all above scenarios :). > > BR, > Jani. > > > > > >> > >> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> > >> --- > >> drivers/gpu/drm/i915/intel_dsi.c | 79 > >> ++++++++++++++++++++++++---------------- > >> 1 file changed, 48 insertions(+), 31 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c > >> b/drivers/gpu/drm/i915/intel_dsi.c > >> index fc0ef49..6b68864 100644 > >> --- a/drivers/gpu/drm/i915/intel_dsi.c > >> +++ b/drivers/gpu/drm/i915/intel_dsi.c > >> @@ -346,12 +346,17 @@ static bool intel_dsi_compute_config(struct > intel_encoder *encoder, > >> return true; > >> } > >> > >> -static void glk_dsi_device_ready(struct intel_encoder *encoder) > >> +static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > >> + struct intel_crtc_state *pipe_config); > >> + > >> +static void glk_dsi_device_ready(struct intel_encoder *encoder, > >> + struct intel_crtc_state *pipe_config) > >> { > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > >> enum port port; > >> u32 tmp, val; > >> + bool cold_boot = false; > >> > >> /* Set the MIPI mode > >> * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. > >> @@ -370,7 +375,10 @@ static void glk_dsi_device_ready(struct > intel_encoder *encoder) > >> /* Program LP Wake */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> tmp = I915_READ(MIPI_CTRL(port)); > >> - tmp |= GLK_LP_WAKE; > >> + if (!(I915_READ(MIPI_DEVICE_READY(port)) & > DEVICE_READY)) > >> + tmp &= ~GLK_LP_WAKE; > >> + else > >> + tmp |= GLK_LP_WAKE; > >> I915_WRITE(MIPI_CTRL(port), tmp); > >> } > >> > >> @@ -382,6 +390,15 @@ static void glk_dsi_device_ready(struct > intel_encoder *encoder) > >> DRM_ERROR("MIPIO port is powergated\n"); > >> } > >> > >> + /* Check if cold boot scenario */ > >> + for_each_dsi_port(port, intel_dsi->ports) { > >> + cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) & > >> + DEVICE_READY); > >> + } > >> + > >> + if (cold_boot) > >> + intel_dsi_prepare(encoder, pipe_config); > >> + > >> /* Wait for MIPI PHY status bit to set */ > >> for_each_dsi_port(port, intel_dsi->ports) { > >> if (intel_wait_for_register(dev_priv, > >> @@ -402,34 +419,34 @@ static void glk_dsi_device_ready(struct > intel_encoder *encoder) > >> val |= DEVICE_READY; > >> I915_WRITE(MIPI_DEVICE_READY(port), val); > >> usleep_range(10, 15); > >> - } > >> - > >> - /* Enter ULPS */ > >> - val = I915_READ(MIPI_DEVICE_READY(port)); > >> - val &= ~ULPS_STATE_MASK; > >> - val |= (ULPS_STATE_ENTER | DEVICE_READY); > >> - I915_WRITE(MIPI_DEVICE_READY(port), val); > >> + } else { > >> + /* Enter ULPS */ > >> + val = I915_READ(MIPI_DEVICE_READY(port)); > >> + val &= ~ULPS_STATE_MASK; > >> + val |= (ULPS_STATE_ENTER | DEVICE_READY); > >> + I915_WRITE(MIPI_DEVICE_READY(port), val); > >> > >> - /* Wait for ULPS active */ > >> - if (intel_wait_for_register(dev_priv, > >> + /* Wait for ULPS active */ > >> + if (intel_wait_for_register(dev_priv, > >> MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, > 20)) > >> - DRM_ERROR("ULPS not active\n"); > >> + DRM_ERROR("ULPS not active\n"); > >> > >> - /* Exit ULPS */ > >> - val = I915_READ(MIPI_DEVICE_READY(port)); > >> - val &= ~ULPS_STATE_MASK; > >> - val |= (ULPS_STATE_EXIT | DEVICE_READY); > >> - I915_WRITE(MIPI_DEVICE_READY(port), val); > >> + /* Exit ULPS */ > >> + val = I915_READ(MIPI_DEVICE_READY(port)); > >> + val &= ~ULPS_STATE_MASK; > >> + val |= (ULPS_STATE_EXIT | DEVICE_READY); > >> + I915_WRITE(MIPI_DEVICE_READY(port), val); > >> > >> - /* Enter Normal Mode */ > >> - val = I915_READ(MIPI_DEVICE_READY(port)); > >> - val &= ~ULPS_STATE_MASK; > >> - val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); > >> - I915_WRITE(MIPI_DEVICE_READY(port), val); > >> + /* Enter Normal Mode */ > >> + val = I915_READ(MIPI_DEVICE_READY(port)); > >> + val &= ~ULPS_STATE_MASK; > >> + val |= (ULPS_STATE_NORMAL_OPERATION | > DEVICE_READY); > >> + I915_WRITE(MIPI_DEVICE_READY(port), val); > >> > >> - tmp = I915_READ(MIPI_CTRL(port)); > >> - tmp &= ~GLK_LP_WAKE; > >> - I915_WRITE(MIPI_CTRL(port), tmp); > >> + tmp = I915_READ(MIPI_CTRL(port)); > >> + tmp &= ~GLK_LP_WAKE; > >> + I915_WRITE(MIPI_CTRL(port), tmp); > >> + } > >> } > >> > >> /* Wait for Stop state */ > >> @@ -515,7 +532,8 @@ static void vlv_dsi_device_ready(struct > intel_encoder *encoder) > >> } > >> } > >> > >> -static void intel_dsi_device_ready(struct intel_encoder *encoder) > >> +static void intel_dsi_device_ready(struct intel_encoder *encoder, > >> + struct intel_crtc_state *pipe_config) > >> { > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> > >> @@ -524,7 +542,7 @@ static void intel_dsi_device_ready(struct > intel_encoder *encoder) > >> else if (IS_BROXTON(dev_priv)) > >> bxt_dsi_device_ready(encoder); > >> else if (IS_GEMINILAKE(dev_priv)) > >> - glk_dsi_device_ready(encoder); > >> + glk_dsi_device_ready(encoder, pipe_config); > >> } > >> > >> static void glk_dsi_enter_low_power_mode(struct intel_encoder > >> *encoder) @@ -710,8 +728,6 @@ static void intel_dsi_port_disable(struct > intel_encoder *encoder) > >> } > >> } > >> > >> -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > >> - struct intel_crtc_state *pipe_config); > >> static void intel_dsi_unprepare(struct intel_encoder *encoder); > >> > >> static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) > >> @@ -800,7 +816,8 @@ static void intel_dsi_pre_enable(struct > intel_encoder *encoder, > >> I915_WRITE(DSPCLK_GATE_D, val); > >> } > >> > >> - intel_dsi_prepare(encoder, pipe_config); > >> + if (!IS_GEMINILAKE(dev_priv)) > >> + intel_dsi_prepare(encoder, pipe_config); > >> > >> /* Power on, try both CRC pmic gpio and VBT */ > >> if (intel_dsi->gpio_panel) > >> @@ -812,7 +829,7 @@ static void intel_dsi_pre_enable(struct > intel_encoder *encoder, > >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); > >> > >> /* Put device in ready state (LP-11) */ > >> - intel_dsi_device_ready(encoder); > >> + intel_dsi_device_ready(encoder, pipe_config); > >> > >> /* Send initialization commands in LP mode */ > >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); > >> -- > >> 1.9.1 > >> > >> _______________________________________________ > >> Intel-gfx mailing list > >> Intel-gfx@lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI 2017-05-15 17:42 ` Chauhan, Madhav @ 2017-05-24 13:51 ` Jani Nikula 2017-05-24 18:00 ` Chauhan, Madhav 0 siblings, 1 reply; 12+ messages in thread From: Jani Nikula @ 2017-05-24 13:51 UTC (permalink / raw) To: Chauhan, Madhav, Ville Syrjälä Cc: Conselvan De Oliveira, Ander, intel-gfx@lists.freedesktop.org, Hiremath, Shashidhar On Mon, 15 May 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote: >> -----Original Message----- >> From: Nikula, Jani >> Sent: Monday, May 15, 2017 9:19 PM >> To: Ville Syrjälä <ville.syrjala@linux.intel.com>; Chauhan, Madhav >> <madhav.chauhan@intel.com> >> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander >> <ander.conselvan.de.oliveira@intel.com>; Hiremath, Shashidhar >> <shashidhar.hiremath@intel.com> >> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK >> DSI >> >> On Tue, 09 May 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: >> > On Tue, May 09, 2017 at 06:59:25PM +0530, Madhav Chauhan wrote: >> >> As per BSEPC, if device ready bit is '0' in enable IO sequence then >> >> its a cold boot/reset scenario eg: S3/S4 resume. In these conditions >> >> we need to program certain registers and prepare port from the middle >> >> of DSI enable sequence otherwise feature like S3/S4 doesn't work. >> > >> > Can't we just always follow the "cold boot" sequence? Less codepaths >> > means less bugs. >> >> I agree. Madhav? > > Cold Boot scenario represents when DSI controller/IO is not initialized even once before use eg: > 1. Connected HDMI boot with DSI panel > 2. S3/S4 > While normal scenario is: > 1. Boot with DSI panel without HDMI. DSI will be initialized once by GOP/BIOS > > If we use cold boot sequence always, normal scenario doesn’t work as few registers can’t be > Programmed as per cold boot scenario. LP_WAKE bit (MIPI_CTRL REG) is one of the example. > > Moreover, current changes works very well for all above scenarios :). Well, no. There's a very limited set of registers that can and must only be programmed in the "cold boot" case. This patch moves all of intel_dsi_prepare() for glk to only be done in the cold boot case, but there's a load of registers that aren't restricted in this way, and need to be programmed on enable regardless of device ready. Seems to me the change here is too coarse grained. BR, Jani. > >> >> BR, >> Jani. >> >> >> > >> >> >> >> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> >> >> --- >> >> drivers/gpu/drm/i915/intel_dsi.c | 79 >> >> ++++++++++++++++++++++++---------------- >> >> 1 file changed, 48 insertions(+), 31 deletions(-) >> >> >> >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c >> >> b/drivers/gpu/drm/i915/intel_dsi.c >> >> index fc0ef49..6b68864 100644 >> >> --- a/drivers/gpu/drm/i915/intel_dsi.c >> >> +++ b/drivers/gpu/drm/i915/intel_dsi.c >> >> @@ -346,12 +346,17 @@ static bool intel_dsi_compute_config(struct >> intel_encoder *encoder, >> >> return true; >> >> } >> >> >> >> -static void glk_dsi_device_ready(struct intel_encoder *encoder) >> >> +static void intel_dsi_prepare(struct intel_encoder *intel_encoder, >> >> + struct intel_crtc_state *pipe_config); >> >> + >> >> +static void glk_dsi_device_ready(struct intel_encoder *encoder, >> >> + struct intel_crtc_state *pipe_config) >> >> { >> >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); >> >> enum port port; >> >> u32 tmp, val; >> >> + bool cold_boot = false; >> >> >> >> /* Set the MIPI mode >> >> * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. >> >> @@ -370,7 +375,10 @@ static void glk_dsi_device_ready(struct >> intel_encoder *encoder) >> >> /* Program LP Wake */ >> >> for_each_dsi_port(port, intel_dsi->ports) { >> >> tmp = I915_READ(MIPI_CTRL(port)); >> >> - tmp |= GLK_LP_WAKE; >> >> + if (!(I915_READ(MIPI_DEVICE_READY(port)) & >> DEVICE_READY)) >> >> + tmp &= ~GLK_LP_WAKE; >> >> + else >> >> + tmp |= GLK_LP_WAKE; >> >> I915_WRITE(MIPI_CTRL(port), tmp); >> >> } >> >> >> >> @@ -382,6 +390,15 @@ static void glk_dsi_device_ready(struct >> intel_encoder *encoder) >> >> DRM_ERROR("MIPIO port is powergated\n"); >> >> } >> >> >> >> + /* Check if cold boot scenario */ >> >> + for_each_dsi_port(port, intel_dsi->ports) { >> >> + cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) & >> >> + DEVICE_READY); >> >> + } >> >> + >> >> + if (cold_boot) >> >> + intel_dsi_prepare(encoder, pipe_config); >> >> + >> >> /* Wait for MIPI PHY status bit to set */ >> >> for_each_dsi_port(port, intel_dsi->ports) { >> >> if (intel_wait_for_register(dev_priv, >> >> @@ -402,34 +419,34 @@ static void glk_dsi_device_ready(struct >> intel_encoder *encoder) >> >> val |= DEVICE_READY; >> >> I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> usleep_range(10, 15); >> >> - } >> >> - >> >> - /* Enter ULPS */ >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); >> >> - val &= ~ULPS_STATE_MASK; >> >> - val |= (ULPS_STATE_ENTER | DEVICE_READY); >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> + } else { >> >> + /* Enter ULPS */ >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); >> >> + val &= ~ULPS_STATE_MASK; >> >> + val |= (ULPS_STATE_ENTER | DEVICE_READY); >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> >> >> - /* Wait for ULPS active */ >> >> - if (intel_wait_for_register(dev_priv, >> >> + /* Wait for ULPS active */ >> >> + if (intel_wait_for_register(dev_priv, >> >> MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, >> 20)) >> >> - DRM_ERROR("ULPS not active\n"); >> >> + DRM_ERROR("ULPS not active\n"); >> >> >> >> - /* Exit ULPS */ >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); >> >> - val &= ~ULPS_STATE_MASK; >> >> - val |= (ULPS_STATE_EXIT | DEVICE_READY); >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> + /* Exit ULPS */ >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); >> >> + val &= ~ULPS_STATE_MASK; >> >> + val |= (ULPS_STATE_EXIT | DEVICE_READY); >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> >> >> - /* Enter Normal Mode */ >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); >> >> - val &= ~ULPS_STATE_MASK; >> >> - val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> + /* Enter Normal Mode */ >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); >> >> + val &= ~ULPS_STATE_MASK; >> >> + val |= (ULPS_STATE_NORMAL_OPERATION | >> DEVICE_READY); >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> >> >> - tmp = I915_READ(MIPI_CTRL(port)); >> >> - tmp &= ~GLK_LP_WAKE; >> >> - I915_WRITE(MIPI_CTRL(port), tmp); >> >> + tmp = I915_READ(MIPI_CTRL(port)); >> >> + tmp &= ~GLK_LP_WAKE; >> >> + I915_WRITE(MIPI_CTRL(port), tmp); >> >> + } >> >> } >> >> >> >> /* Wait for Stop state */ >> >> @@ -515,7 +532,8 @@ static void vlv_dsi_device_ready(struct >> intel_encoder *encoder) >> >> } >> >> } >> >> >> >> -static void intel_dsi_device_ready(struct intel_encoder *encoder) >> >> +static void intel_dsi_device_ready(struct intel_encoder *encoder, >> >> + struct intel_crtc_state *pipe_config) >> >> { >> >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> >> >> >> @@ -524,7 +542,7 @@ static void intel_dsi_device_ready(struct >> intel_encoder *encoder) >> >> else if (IS_BROXTON(dev_priv)) >> >> bxt_dsi_device_ready(encoder); >> >> else if (IS_GEMINILAKE(dev_priv)) >> >> - glk_dsi_device_ready(encoder); >> >> + glk_dsi_device_ready(encoder, pipe_config); >> >> } >> >> >> >> static void glk_dsi_enter_low_power_mode(struct intel_encoder >> >> *encoder) @@ -710,8 +728,6 @@ static void intel_dsi_port_disable(struct >> intel_encoder *encoder) >> >> } >> >> } >> >> >> >> -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, >> >> - struct intel_crtc_state *pipe_config); >> >> static void intel_dsi_unprepare(struct intel_encoder *encoder); >> >> >> >> static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) >> >> @@ -800,7 +816,8 @@ static void intel_dsi_pre_enable(struct >> intel_encoder *encoder, >> >> I915_WRITE(DSPCLK_GATE_D, val); >> >> } >> >> >> >> - intel_dsi_prepare(encoder, pipe_config); >> >> + if (!IS_GEMINILAKE(dev_priv)) >> >> + intel_dsi_prepare(encoder, pipe_config); >> >> >> >> /* Power on, try both CRC pmic gpio and VBT */ >> >> if (intel_dsi->gpio_panel) >> >> @@ -812,7 +829,7 @@ static void intel_dsi_pre_enable(struct >> intel_encoder *encoder, >> >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); >> >> >> >> /* Put device in ready state (LP-11) */ >> >> - intel_dsi_device_ready(encoder); >> >> + intel_dsi_device_ready(encoder, pipe_config); >> >> >> >> /* Send initialization commands in LP mode */ >> >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); >> >> -- >> >> 1.9.1 >> >> >> >> _______________________________________________ >> >> Intel-gfx mailing list >> >> Intel-gfx@lists.freedesktop.org >> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> >> -- >> Jani Nikula, Intel Open Source Technology Center -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI 2017-05-24 13:51 ` Jani Nikula @ 2017-05-24 18:00 ` Chauhan, Madhav 2017-05-30 7:03 ` Jani Nikula 0 siblings, 1 reply; 12+ messages in thread From: Chauhan, Madhav @ 2017-05-24 18:00 UTC (permalink / raw) To: Nikula, Jani, Ville Syrjälä Cc: Conselvan De Oliveira, Ander, intel-gfx@lists.freedesktop.org, Hiremath, Shashidhar > -----Original Message----- > From: Nikula, Jani > Sent: Wednesday, May 24, 2017 7:22 PM > To: Chauhan, Madhav <madhav.chauhan@intel.com>; Ville Syrjälä > <ville.syrjala@linux.intel.com> > Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander > <ander.conselvan.de.oliveira@intel.com>; Hiremath, Shashidhar > <shashidhar.hiremath@intel.com> > Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK > DSI > > On Mon, 15 May 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com> > wrote: > >> -----Original Message----- > >> From: Nikula, Jani > >> Sent: Monday, May 15, 2017 9:19 PM > >> To: Ville Syrjälä <ville.syrjala@linux.intel.com>; Chauhan, Madhav > >> <madhav.chauhan@intel.com> > >> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander > >> <ander.conselvan.de.oliveira@intel.com>; Hiremath, Shashidhar > >> <shashidhar.hiremath@intel.com> > >> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot > >> for GLK DSI > >> > >> On Tue, 09 May 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > >> > On Tue, May 09, 2017 at 06:59:25PM +0530, Madhav Chauhan wrote: > >> >> As per BSEPC, if device ready bit is '0' in enable IO sequence > >> >> then its a cold boot/reset scenario eg: S3/S4 resume. In these > >> >> conditions we need to program certain registers and prepare port > >> >> from the middle of DSI enable sequence otherwise feature like S3/S4 > doesn't work. > >> > > >> > Can't we just always follow the "cold boot" sequence? Less > >> > codepaths means less bugs. > >> > >> I agree. Madhav? > > > > Cold Boot scenario represents when DSI controller/IO is not initialized > even once before use eg: > > 1. Connected HDMI boot with DSI panel > > 2. S3/S4 > > While normal scenario is: > > 1. Boot with DSI panel without HDMI. DSI will be initialized once by > > GOP/BIOS > > > > If we use cold boot sequence always, normal scenario doesn’t work as > > few registers can’t be Programmed as per cold boot scenario. LP_WAKE bit > (MIPI_CTRL REG) is one of the example. > > > > Moreover, current changes works very well for all above scenarios :). > > Well, no. There's a very limited set of registers that can and must only be > programmed in the "cold boot" case. This patch moves all of > intel_dsi_prepare() for glk to only be done in the cold boot case, but there's a > load of registers that aren't restricted in this way, and need to be > programmed on enable regardless of device ready. Seems to me the change > here is too coarse grained. Actually when we do GLK_MIPIIO_ENABLE in device_ready all the registers are restored back When DSI is enabled after disable through software *IF* power is not lost(normal scenario) so we can opt out not to program during normal scenario. Found this in my testing. Will confirm this with HW team. While for cold boot scenario where power is lost during S3/S4, we need to program all these registers And unfortunately when we program *ONLY* register mentioned in BSPEC in device_ready DSI is not up and Need to program all registers here itself to make it work. > > BR, > Jani. > > > > >> > >> BR, > >> Jani. > >> > >> > >> > > >> >> > >> >> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> > >> >> --- > >> >> drivers/gpu/drm/i915/intel_dsi.c | 79 > >> >> ++++++++++++++++++++++++---------------- > >> >> 1 file changed, 48 insertions(+), 31 deletions(-) > >> >> > >> >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c > >> >> b/drivers/gpu/drm/i915/intel_dsi.c > >> >> index fc0ef49..6b68864 100644 > >> >> --- a/drivers/gpu/drm/i915/intel_dsi.c > >> >> +++ b/drivers/gpu/drm/i915/intel_dsi.c > >> >> @@ -346,12 +346,17 @@ static bool intel_dsi_compute_config(struct > >> intel_encoder *encoder, > >> >> return true; > >> >> } > >> >> > >> >> -static void glk_dsi_device_ready(struct intel_encoder *encoder) > >> >> +static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > >> >> + struct intel_crtc_state *pipe_config); > >> >> + > >> >> +static void glk_dsi_device_ready(struct intel_encoder *encoder, > >> >> + struct intel_crtc_state *pipe_config) > >> >> { > >> >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > >> >> enum port port; > >> >> u32 tmp, val; > >> >> + bool cold_boot = false; > >> >> > >> >> /* Set the MIPI mode > >> >> * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. > >> >> @@ -370,7 +375,10 @@ static void glk_dsi_device_ready(struct > >> intel_encoder *encoder) > >> >> /* Program LP Wake */ > >> >> for_each_dsi_port(port, intel_dsi->ports) { > >> >> tmp = I915_READ(MIPI_CTRL(port)); > >> >> - tmp |= GLK_LP_WAKE; > >> >> + if (!(I915_READ(MIPI_DEVICE_READY(port)) & > >> DEVICE_READY)) > >> >> + tmp &= ~GLK_LP_WAKE; > >> >> + else > >> >> + tmp |= GLK_LP_WAKE; > >> >> I915_WRITE(MIPI_CTRL(port), tmp); > >> >> } > >> >> > >> >> @@ -382,6 +390,15 @@ static void glk_dsi_device_ready(struct > >> intel_encoder *encoder) > >> >> DRM_ERROR("MIPIO port is powergated\n"); > >> >> } > >> >> > >> >> + /* Check if cold boot scenario */ > >> >> + for_each_dsi_port(port, intel_dsi->ports) { > >> >> + cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) & > >> >> + DEVICE_READY); > >> >> + } > >> >> + > >> >> + if (cold_boot) > >> >> + intel_dsi_prepare(encoder, pipe_config); > >> >> + > >> >> /* Wait for MIPI PHY status bit to set */ > >> >> for_each_dsi_port(port, intel_dsi->ports) { > >> >> if (intel_wait_for_register(dev_priv, > >> >> @@ -402,34 +419,34 @@ static void glk_dsi_device_ready(struct > >> intel_encoder *encoder) > >> >> val |= DEVICE_READY; > >> >> I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> usleep_range(10, 15); > >> >> - } > >> >> - > >> >> - /* Enter ULPS */ > >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> - val &= ~ULPS_STATE_MASK; > >> >> - val |= (ULPS_STATE_ENTER | DEVICE_READY); > >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> + } else { > >> >> + /* Enter ULPS */ > >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> + val &= ~ULPS_STATE_MASK; > >> >> + val |= (ULPS_STATE_ENTER | DEVICE_READY); > >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> > >> >> - /* Wait for ULPS active */ > >> >> - if (intel_wait_for_register(dev_priv, > >> >> + /* Wait for ULPS active */ > >> >> + if (intel_wait_for_register(dev_priv, > >> >> MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, > >> 20)) > >> >> - DRM_ERROR("ULPS not active\n"); > >> >> + DRM_ERROR("ULPS not active\n"); > >> >> > >> >> - /* Exit ULPS */ > >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> - val &= ~ULPS_STATE_MASK; > >> >> - val |= (ULPS_STATE_EXIT | DEVICE_READY); > >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> + /* Exit ULPS */ > >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> + val &= ~ULPS_STATE_MASK; > >> >> + val |= (ULPS_STATE_EXIT | DEVICE_READY); > >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> > >> >> - /* Enter Normal Mode */ > >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> - val &= ~ULPS_STATE_MASK; > >> >> - val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); > >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> + /* Enter Normal Mode */ > >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> + val &= ~ULPS_STATE_MASK; > >> >> + val |= (ULPS_STATE_NORMAL_OPERATION | > >> DEVICE_READY); > >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> > >> >> - tmp = I915_READ(MIPI_CTRL(port)); > >> >> - tmp &= ~GLK_LP_WAKE; > >> >> - I915_WRITE(MIPI_CTRL(port), tmp); > >> >> + tmp = I915_READ(MIPI_CTRL(port)); > >> >> + tmp &= ~GLK_LP_WAKE; > >> >> + I915_WRITE(MIPI_CTRL(port), tmp); > >> >> + } > >> >> } > >> >> > >> >> /* Wait for Stop state */ > >> >> @@ -515,7 +532,8 @@ static void vlv_dsi_device_ready(struct > >> intel_encoder *encoder) > >> >> } > >> >> } > >> >> > >> >> -static void intel_dsi_device_ready(struct intel_encoder *encoder) > >> >> +static void intel_dsi_device_ready(struct intel_encoder *encoder, > >> >> + struct intel_crtc_state *pipe_config) > >> >> { > >> >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> >> > >> >> @@ -524,7 +542,7 @@ static void intel_dsi_device_ready(struct > >> intel_encoder *encoder) > >> >> else if (IS_BROXTON(dev_priv)) > >> >> bxt_dsi_device_ready(encoder); > >> >> else if (IS_GEMINILAKE(dev_priv)) > >> >> - glk_dsi_device_ready(encoder); > >> >> + glk_dsi_device_ready(encoder, pipe_config); > >> >> } > >> >> > >> >> static void glk_dsi_enter_low_power_mode(struct intel_encoder > >> >> *encoder) @@ -710,8 +728,6 @@ static void > >> >> intel_dsi_port_disable(struct > >> intel_encoder *encoder) > >> >> } > >> >> } > >> >> > >> >> -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > >> >> - struct intel_crtc_state *pipe_config); > >> >> static void intel_dsi_unprepare(struct intel_encoder *encoder); > >> >> > >> >> static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int > >> >> msec) @@ -800,7 +816,8 @@ static void intel_dsi_pre_enable(struct > >> intel_encoder *encoder, > >> >> I915_WRITE(DSPCLK_GATE_D, val); > >> >> } > >> >> > >> >> - intel_dsi_prepare(encoder, pipe_config); > >> >> + if (!IS_GEMINILAKE(dev_priv)) > >> >> + intel_dsi_prepare(encoder, pipe_config); > >> >> > >> >> /* Power on, try both CRC pmic gpio and VBT */ > >> >> if (intel_dsi->gpio_panel) > >> >> @@ -812,7 +829,7 @@ static void intel_dsi_pre_enable(struct > >> intel_encoder *encoder, > >> >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); > >> >> > >> >> /* Put device in ready state (LP-11) */ > >> >> - intel_dsi_device_ready(encoder); > >> >> + intel_dsi_device_ready(encoder, pipe_config); > >> >> > >> >> /* Send initialization commands in LP mode */ > >> >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); > >> >> -- > >> >> 1.9.1 > >> >> > >> >> _______________________________________________ > >> >> Intel-gfx mailing list > >> >> Intel-gfx@lists.freedesktop.org > >> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > >> > >> -- > >> Jani Nikula, Intel Open Source Technology Center > > -- > Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI 2017-05-24 18:00 ` Chauhan, Madhav @ 2017-05-30 7:03 ` Jani Nikula 2017-05-30 9:10 ` Chauhan, Madhav 0 siblings, 1 reply; 12+ messages in thread From: Jani Nikula @ 2017-05-30 7:03 UTC (permalink / raw) To: Chauhan, Madhav, Ville Syrjälä Cc: Conselvan De Oliveira, Ander, intel-gfx@lists.freedesktop.org, Hiremath, Shashidhar On Wed, 24 May 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote: >> -----Original Message----- >> From: Nikula, Jani >> Sent: Wednesday, May 24, 2017 7:22 PM >> To: Chauhan, Madhav <madhav.chauhan@intel.com>; Ville Syrjälä >> <ville.syrjala@linux.intel.com> >> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander >> <ander.conselvan.de.oliveira@intel.com>; Hiremath, Shashidhar >> <shashidhar.hiremath@intel.com> >> Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK >> DSI >> >> On Mon, 15 May 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com> >> wrote: >> >> -----Original Message----- >> >> From: Nikula, Jani >> >> Sent: Monday, May 15, 2017 9:19 PM >> >> To: Ville Syrjälä <ville.syrjala@linux.intel.com>; Chauhan, Madhav >> >> <madhav.chauhan@intel.com> >> >> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander >> >> <ander.conselvan.de.oliveira@intel.com>; Hiremath, Shashidhar >> >> <shashidhar.hiremath@intel.com> >> >> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot >> >> for GLK DSI >> >> >> >> On Tue, 09 May 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: >> >> > On Tue, May 09, 2017 at 06:59:25PM +0530, Madhav Chauhan wrote: >> >> >> As per BSEPC, if device ready bit is '0' in enable IO sequence >> >> >> then its a cold boot/reset scenario eg: S3/S4 resume. In these >> >> >> conditions we need to program certain registers and prepare port >> >> >> from the middle of DSI enable sequence otherwise feature like S3/S4 >> doesn't work. >> >> > >> >> > Can't we just always follow the "cold boot" sequence? Less >> >> > codepaths means less bugs. >> >> >> >> I agree. Madhav? >> > >> > Cold Boot scenario represents when DSI controller/IO is not initialized >> even once before use eg: >> > 1. Connected HDMI boot with DSI panel >> > 2. S3/S4 >> > While normal scenario is: >> > 1. Boot with DSI panel without HDMI. DSI will be initialized once by >> > GOP/BIOS >> > >> > If we use cold boot sequence always, normal scenario doesn’t work as >> > few registers can’t be Programmed as per cold boot scenario. LP_WAKE bit >> (MIPI_CTRL REG) is one of the example. >> > >> > Moreover, current changes works very well for all above scenarios :). >> >> Well, no. There's a very limited set of registers that can and must only be >> programmed in the "cold boot" case. This patch moves all of >> intel_dsi_prepare() for glk to only be done in the cold boot case, but there's a >> load of registers that aren't restricted in this way, and need to be >> programmed on enable regardless of device ready. Seems to me the change >> here is too coarse grained. > > Actually when we do GLK_MIPIIO_ENABLE in device_ready all the > registers are restored back When DSI is enabled after disable through > software *IF* power is not lost(normal scenario) so we can opt out not > to program during normal scenario. Found this in my testing. Will > confirm this with HW team. > > While for cold boot scenario where power is lost during S3/S4, we need > to program all these registers And unfortunately when we program > *ONLY* register mentioned in BSPEC in device_ready DSI is not up and > Need to program all registers here itself to make it work. But this assumes that on enable, when power has not been lost, all the registers contain the correct information already. We can't rely on that. BR, Jani. > >> >> BR, >> Jani. >> >> > >> >> >> >> BR, >> >> Jani. >> >> >> >> >> >> > >> >> >> >> >> >> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> >> >> >> --- >> >> >> drivers/gpu/drm/i915/intel_dsi.c | 79 >> >> >> ++++++++++++++++++++++++---------------- >> >> >> 1 file changed, 48 insertions(+), 31 deletions(-) >> >> >> >> >> >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c >> >> >> b/drivers/gpu/drm/i915/intel_dsi.c >> >> >> index fc0ef49..6b68864 100644 >> >> >> --- a/drivers/gpu/drm/i915/intel_dsi.c >> >> >> +++ b/drivers/gpu/drm/i915/intel_dsi.c >> >> >> @@ -346,12 +346,17 @@ static bool intel_dsi_compute_config(struct >> >> intel_encoder *encoder, >> >> >> return true; >> >> >> } >> >> >> >> >> >> -static void glk_dsi_device_ready(struct intel_encoder *encoder) >> >> >> +static void intel_dsi_prepare(struct intel_encoder *intel_encoder, >> >> >> + struct intel_crtc_state *pipe_config); >> >> >> + >> >> >> +static void glk_dsi_device_ready(struct intel_encoder *encoder, >> >> >> + struct intel_crtc_state *pipe_config) >> >> >> { >> >> >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> >> >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); >> >> >> enum port port; >> >> >> u32 tmp, val; >> >> >> + bool cold_boot = false; >> >> >> >> >> >> /* Set the MIPI mode >> >> >> * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. >> >> >> @@ -370,7 +375,10 @@ static void glk_dsi_device_ready(struct >> >> intel_encoder *encoder) >> >> >> /* Program LP Wake */ >> >> >> for_each_dsi_port(port, intel_dsi->ports) { >> >> >> tmp = I915_READ(MIPI_CTRL(port)); >> >> >> - tmp |= GLK_LP_WAKE; >> >> >> + if (!(I915_READ(MIPI_DEVICE_READY(port)) & >> >> DEVICE_READY)) >> >> >> + tmp &= ~GLK_LP_WAKE; >> >> >> + else >> >> >> + tmp |= GLK_LP_WAKE; >> >> >> I915_WRITE(MIPI_CTRL(port), tmp); >> >> >> } >> >> >> >> >> >> @@ -382,6 +390,15 @@ static void glk_dsi_device_ready(struct >> >> intel_encoder *encoder) >> >> >> DRM_ERROR("MIPIO port is powergated\n"); >> >> >> } >> >> >> >> >> >> + /* Check if cold boot scenario */ >> >> >> + for_each_dsi_port(port, intel_dsi->ports) { >> >> >> + cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) & >> >> >> + DEVICE_READY); >> >> >> + } >> >> >> + >> >> >> + if (cold_boot) >> >> >> + intel_dsi_prepare(encoder, pipe_config); >> >> >> + >> >> >> /* Wait for MIPI PHY status bit to set */ >> >> >> for_each_dsi_port(port, intel_dsi->ports) { >> >> >> if (intel_wait_for_register(dev_priv, >> >> >> @@ -402,34 +419,34 @@ static void glk_dsi_device_ready(struct >> >> intel_encoder *encoder) >> >> >> val |= DEVICE_READY; >> >> >> I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> >> usleep_range(10, 15); >> >> >> - } >> >> >> - >> >> >> - /* Enter ULPS */ >> >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); >> >> >> - val &= ~ULPS_STATE_MASK; >> >> >> - val |= (ULPS_STATE_ENTER | DEVICE_READY); >> >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> >> + } else { >> >> >> + /* Enter ULPS */ >> >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); >> >> >> + val &= ~ULPS_STATE_MASK; >> >> >> + val |= (ULPS_STATE_ENTER | DEVICE_READY); >> >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> >> >> >> >> - /* Wait for ULPS active */ >> >> >> - if (intel_wait_for_register(dev_priv, >> >> >> + /* Wait for ULPS active */ >> >> >> + if (intel_wait_for_register(dev_priv, >> >> >> MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, >> >> 20)) >> >> >> - DRM_ERROR("ULPS not active\n"); >> >> >> + DRM_ERROR("ULPS not active\n"); >> >> >> >> >> >> - /* Exit ULPS */ >> >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); >> >> >> - val &= ~ULPS_STATE_MASK; >> >> >> - val |= (ULPS_STATE_EXIT | DEVICE_READY); >> >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> >> + /* Exit ULPS */ >> >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); >> >> >> + val &= ~ULPS_STATE_MASK; >> >> >> + val |= (ULPS_STATE_EXIT | DEVICE_READY); >> >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> >> >> >> >> - /* Enter Normal Mode */ >> >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); >> >> >> - val &= ~ULPS_STATE_MASK; >> >> >> - val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); >> >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> >> + /* Enter Normal Mode */ >> >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); >> >> >> + val &= ~ULPS_STATE_MASK; >> >> >> + val |= (ULPS_STATE_NORMAL_OPERATION | >> >> DEVICE_READY); >> >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); >> >> >> >> >> >> - tmp = I915_READ(MIPI_CTRL(port)); >> >> >> - tmp &= ~GLK_LP_WAKE; >> >> >> - I915_WRITE(MIPI_CTRL(port), tmp); >> >> >> + tmp = I915_READ(MIPI_CTRL(port)); >> >> >> + tmp &= ~GLK_LP_WAKE; >> >> >> + I915_WRITE(MIPI_CTRL(port), tmp); >> >> >> + } >> >> >> } >> >> >> >> >> >> /* Wait for Stop state */ >> >> >> @@ -515,7 +532,8 @@ static void vlv_dsi_device_ready(struct >> >> intel_encoder *encoder) >> >> >> } >> >> >> } >> >> >> >> >> >> -static void intel_dsi_device_ready(struct intel_encoder *encoder) >> >> >> +static void intel_dsi_device_ready(struct intel_encoder *encoder, >> >> >> + struct intel_crtc_state *pipe_config) >> >> >> { >> >> >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> >> >> >> >> >> @@ -524,7 +542,7 @@ static void intel_dsi_device_ready(struct >> >> intel_encoder *encoder) >> >> >> else if (IS_BROXTON(dev_priv)) >> >> >> bxt_dsi_device_ready(encoder); >> >> >> else if (IS_GEMINILAKE(dev_priv)) >> >> >> - glk_dsi_device_ready(encoder); >> >> >> + glk_dsi_device_ready(encoder, pipe_config); >> >> >> } >> >> >> >> >> >> static void glk_dsi_enter_low_power_mode(struct intel_encoder >> >> >> *encoder) @@ -710,8 +728,6 @@ static void >> >> >> intel_dsi_port_disable(struct >> >> intel_encoder *encoder) >> >> >> } >> >> >> } >> >> >> >> >> >> -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, >> >> >> - struct intel_crtc_state *pipe_config); >> >> >> static void intel_dsi_unprepare(struct intel_encoder *encoder); >> >> >> >> >> >> static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int >> >> >> msec) @@ -800,7 +816,8 @@ static void intel_dsi_pre_enable(struct >> >> intel_encoder *encoder, >> >> >> I915_WRITE(DSPCLK_GATE_D, val); >> >> >> } >> >> >> >> >> >> - intel_dsi_prepare(encoder, pipe_config); >> >> >> + if (!IS_GEMINILAKE(dev_priv)) >> >> >> + intel_dsi_prepare(encoder, pipe_config); >> >> >> >> >> >> /* Power on, try both CRC pmic gpio and VBT */ >> >> >> if (intel_dsi->gpio_panel) >> >> >> @@ -812,7 +829,7 @@ static void intel_dsi_pre_enable(struct >> >> intel_encoder *encoder, >> >> >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); >> >> >> >> >> >> /* Put device in ready state (LP-11) */ >> >> >> - intel_dsi_device_ready(encoder); >> >> >> + intel_dsi_device_ready(encoder, pipe_config); >> >> >> >> >> >> /* Send initialization commands in LP mode */ >> >> >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); >> >> >> -- >> >> >> 1.9.1 >> >> >> >> >> >> _______________________________________________ >> >> >> Intel-gfx mailing list >> >> >> Intel-gfx@lists.freedesktop.org >> >> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> >> >> >> -- >> >> Jani Nikula, Intel Open Source Technology Center >> >> -- >> Jani Nikula, Intel Open Source Technology Center -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI 2017-05-30 7:03 ` Jani Nikula @ 2017-05-30 9:10 ` Chauhan, Madhav 0 siblings, 0 replies; 12+ messages in thread From: Chauhan, Madhav @ 2017-05-30 9:10 UTC (permalink / raw) To: Nikula, Jani, Ville Syrjälä Cc: Conselvan De Oliveira, Ander, intel-gfx@lists.freedesktop.org, Hiremath, Shashidhar > -----Original Message----- > From: Nikula, Jani > Sent: Tuesday, May 30, 2017 12:34 PM > To: Chauhan, Madhav <madhav.chauhan@intel.com>; Ville Syrjälä > <ville.syrjala@linux.intel.com> > Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander > <ander.conselvan.de.oliveira@intel.com>; Hiremath, Shashidhar > <shashidhar.hiremath@intel.com> > Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK > DSI > > On Wed, 24 May 2017, "Chauhan, Madhav" <madhav.chauhan@intel.com> > wrote: > >> -----Original Message----- > >> From: Nikula, Jani > >> Sent: Wednesday, May 24, 2017 7:22 PM > >> To: Chauhan, Madhav <madhav.chauhan@intel.com>; Ville Syrjälä > >> <ville.syrjala@linux.intel.com> > >> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander > >> <ander.conselvan.de.oliveira@intel.com>; Hiremath, Shashidhar > >> <shashidhar.hiremath@intel.com> > >> Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot > >> for GLK DSI > >> > >> On Mon, 15 May 2017, "Chauhan, Madhav" > <madhav.chauhan@intel.com> > >> wrote: > >> >> -----Original Message----- > >> >> From: Nikula, Jani > >> >> Sent: Monday, May 15, 2017 9:19 PM > >> >> To: Ville Syrjälä <ville.syrjala@linux.intel.com>; Chauhan, Madhav > >> >> <madhav.chauhan@intel.com> > >> >> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander > >> >> <ander.conselvan.de.oliveira@intel.com>; Hiremath, Shashidhar > >> >> <shashidhar.hiremath@intel.com> > >> >> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold > >> >> boot for GLK DSI > >> >> > >> >> On Tue, 09 May 2017, Ville Syrjälä <ville.syrjala@linux.intel.com> > wrote: > >> >> > On Tue, May 09, 2017 at 06:59:25PM +0530, Madhav Chauhan wrote: > >> >> >> As per BSEPC, if device ready bit is '0' in enable IO sequence > >> >> >> then its a cold boot/reset scenario eg: S3/S4 resume. In these > >> >> >> conditions we need to program certain registers and prepare > >> >> >> port from the middle of DSI enable sequence otherwise feature > >> >> >> like S3/S4 > >> doesn't work. > >> >> > > >> >> > Can't we just always follow the "cold boot" sequence? Less > >> >> > codepaths means less bugs. > >> >> > >> >> I agree. Madhav? > >> > > >> > Cold Boot scenario represents when DSI controller/IO is not > >> > initialized > >> even once before use eg: > >> > 1. Connected HDMI boot with DSI panel 2. S3/S4 While normal > >> > scenario is: > >> > 1. Boot with DSI panel without HDMI. DSI will be initialized once > >> > by GOP/BIOS > >> > > >> > If we use cold boot sequence always, normal scenario doesn’t work > >> > as few registers can’t be Programmed as per cold boot scenario. > >> > LP_WAKE bit > >> (MIPI_CTRL REG) is one of the example. > >> > > >> > Moreover, current changes works very well for all above scenarios :). > >> > >> Well, no. There's a very limited set of registers that can and must > >> only be programmed in the "cold boot" case. This patch moves all of > >> intel_dsi_prepare() for glk to only be done in the cold boot case, > >> but there's a load of registers that aren't restricted in this way, > >> and need to be programmed on enable regardless of device ready. Seems > >> to me the change here is too coarse grained. > > > > Actually when we do GLK_MIPIIO_ENABLE in device_ready all the > > registers are restored back When DSI is enabled after disable through > > software *IF* power is not lost(normal scenario) so we can opt out not > > to program during normal scenario. Found this in my testing. Will > > confirm this with HW team. > > > > While for cold boot scenario where power is lost during S3/S4, we need > > to program all these registers And unfortunately when we program > > *ONLY* register mentioned in BSPEC in device_ready DSI is not up and > > Need to program all registers here itself to make it work. > > But this assumes that on enable, when power has not been lost, all the > registers contain the correct information already. We can't rely on that. Can we try following then?? glk_dsi_device_ready() { ----- ----- Intel_dsi_prepare(); // Call dsi_prepare for both the scenarios i.e. cold boot, normal scenario ------ ----- } > > BR, > Jani. > > > > > > >> > >> BR, > >> Jani. > >> > >> > > >> >> > >> >> BR, > >> >> Jani. > >> >> > >> >> > >> >> > > >> >> >> > >> >> >> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> > >> >> >> --- > >> >> >> drivers/gpu/drm/i915/intel_dsi.c | 79 > >> >> >> ++++++++++++++++++++++++---------------- > >> >> >> 1 file changed, 48 insertions(+), 31 deletions(-) > >> >> >> > >> >> >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c > >> >> >> b/drivers/gpu/drm/i915/intel_dsi.c > >> >> >> index fc0ef49..6b68864 100644 > >> >> >> --- a/drivers/gpu/drm/i915/intel_dsi.c > >> >> >> +++ b/drivers/gpu/drm/i915/intel_dsi.c > >> >> >> @@ -346,12 +346,17 @@ static bool > >> >> >> intel_dsi_compute_config(struct > >> >> intel_encoder *encoder, > >> >> >> return true; > >> >> >> } > >> >> >> > >> >> >> -static void glk_dsi_device_ready(struct intel_encoder > >> >> >> *encoder) > >> >> >> +static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > >> >> >> + struct intel_crtc_state *pipe_config); > >> >> >> + > >> >> >> +static void glk_dsi_device_ready(struct intel_encoder *encoder, > >> >> >> + struct intel_crtc_state *pipe_config) > >> >> >> { > >> >> >> struct drm_i915_private *dev_priv = to_i915(encoder- > >base.dev); > >> >> >> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder- > >base); > >> >> >> enum port port; > >> >> >> u32 tmp, val; > >> >> >> + bool cold_boot = false; > >> >> >> > >> >> >> /* Set the MIPI mode > >> >> >> * If MIPI_Mode is off, then writing to LP_Wake bit is not > reflecting. > >> >> >> @@ -370,7 +375,10 @@ static void glk_dsi_device_ready(struct > >> >> intel_encoder *encoder) > >> >> >> /* Program LP Wake */ > >> >> >> for_each_dsi_port(port, intel_dsi->ports) { > >> >> >> tmp = I915_READ(MIPI_CTRL(port)); > >> >> >> - tmp |= GLK_LP_WAKE; > >> >> >> + if (!(I915_READ(MIPI_DEVICE_READY(port)) & > >> >> DEVICE_READY)) > >> >> >> + tmp &= ~GLK_LP_WAKE; > >> >> >> + else > >> >> >> + tmp |= GLK_LP_WAKE; > >> >> >> I915_WRITE(MIPI_CTRL(port), tmp); > >> >> >> } > >> >> >> > >> >> >> @@ -382,6 +390,15 @@ static void glk_dsi_device_ready(struct > >> >> intel_encoder *encoder) > >> >> >> DRM_ERROR("MIPIO port is powergated\n"); > >> >> >> } > >> >> >> > >> >> >> + /* Check if cold boot scenario */ > >> >> >> + for_each_dsi_port(port, intel_dsi->ports) { > >> >> >> + cold_boot |= > !(I915_READ(MIPI_DEVICE_READY(port)) & > >> >> >> + > DEVICE_READY); > >> >> >> + } > >> >> >> + > >> >> >> + if (cold_boot) > >> >> >> + intel_dsi_prepare(encoder, pipe_config); > >> >> >> + > >> >> >> /* Wait for MIPI PHY status bit to set */ > >> >> >> for_each_dsi_port(port, intel_dsi->ports) { > >> >> >> if (intel_wait_for_register(dev_priv, > >> >> >> @@ -402,34 +419,34 @@ static void glk_dsi_device_ready(struct > >> >> intel_encoder *encoder) > >> >> >> val |= DEVICE_READY; > >> >> >> I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> >> usleep_range(10, 15); > >> >> >> - } > >> >> >> - > >> >> >> - /* Enter ULPS */ > >> >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> >> - val &= ~ULPS_STATE_MASK; > >> >> >> - val |= (ULPS_STATE_ENTER | DEVICE_READY); > >> >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> >> + } else { > >> >> >> + /* Enter ULPS */ > >> >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> >> + val &= ~ULPS_STATE_MASK; > >> >> >> + val |= (ULPS_STATE_ENTER | DEVICE_READY); > >> >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> >> > >> >> >> - /* Wait for ULPS active */ > >> >> >> - if (intel_wait_for_register(dev_priv, > >> >> >> + /* Wait for ULPS active */ > >> >> >> + if (intel_wait_for_register(dev_priv, > >> >> >> MIPI_CTRL(port), > GLK_ULPS_NOT_ACTIVE, 0, > >> >> 20)) > >> >> >> - DRM_ERROR("ULPS not active\n"); > >> >> >> + DRM_ERROR("ULPS not active\n"); > >> >> >> > >> >> >> - /* Exit ULPS */ > >> >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> >> - val &= ~ULPS_STATE_MASK; > >> >> >> - val |= (ULPS_STATE_EXIT | DEVICE_READY); > >> >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> >> + /* Exit ULPS */ > >> >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> >> + val &= ~ULPS_STATE_MASK; > >> >> >> + val |= (ULPS_STATE_EXIT | DEVICE_READY); > >> >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> >> > >> >> >> - /* Enter Normal Mode */ > >> >> >> - val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> >> - val &= ~ULPS_STATE_MASK; > >> >> >> - val |= (ULPS_STATE_NORMAL_OPERATION | > DEVICE_READY); > >> >> >> - I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> >> + /* Enter Normal Mode */ > >> >> >> + val = I915_READ(MIPI_DEVICE_READY(port)); > >> >> >> + val &= ~ULPS_STATE_MASK; > >> >> >> + val |= (ULPS_STATE_NORMAL_OPERATION | > >> >> DEVICE_READY); > >> >> >> + I915_WRITE(MIPI_DEVICE_READY(port), val); > >> >> >> > >> >> >> - tmp = I915_READ(MIPI_CTRL(port)); > >> >> >> - tmp &= ~GLK_LP_WAKE; > >> >> >> - I915_WRITE(MIPI_CTRL(port), tmp); > >> >> >> + tmp = I915_READ(MIPI_CTRL(port)); > >> >> >> + tmp &= ~GLK_LP_WAKE; > >> >> >> + I915_WRITE(MIPI_CTRL(port), tmp); > >> >> >> + } > >> >> >> } > >> >> >> > >> >> >> /* Wait for Stop state */ > >> >> >> @@ -515,7 +532,8 @@ static void vlv_dsi_device_ready(struct > >> >> intel_encoder *encoder) > >> >> >> } > >> >> >> } > >> >> >> > >> >> >> -static void intel_dsi_device_ready(struct intel_encoder > >> >> >> *encoder) > >> >> >> +static void intel_dsi_device_ready(struct intel_encoder *encoder, > >> >> >> + struct intel_crtc_state *pipe_config) > >> >> >> { > >> >> >> struct drm_i915_private *dev_priv = > >> >> >> to_i915(encoder->base.dev); > >> >> >> > >> >> >> @@ -524,7 +542,7 @@ static void intel_dsi_device_ready(struct > >> >> intel_encoder *encoder) > >> >> >> else if (IS_BROXTON(dev_priv)) > >> >> >> bxt_dsi_device_ready(encoder); > >> >> >> else if (IS_GEMINILAKE(dev_priv)) > >> >> >> - glk_dsi_device_ready(encoder); > >> >> >> + glk_dsi_device_ready(encoder, pipe_config); > >> >> >> } > >> >> >> > >> >> >> static void glk_dsi_enter_low_power_mode(struct intel_encoder > >> >> >> *encoder) @@ -710,8 +728,6 @@ static void > >> >> >> intel_dsi_port_disable(struct > >> >> intel_encoder *encoder) > >> >> >> } > >> >> >> } > >> >> >> > >> >> >> -static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > >> >> >> - struct intel_crtc_state *pipe_config); > >> >> >> static void intel_dsi_unprepare(struct intel_encoder > >> >> >> *encoder); > >> >> >> > >> >> >> static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int > >> >> >> msec) @@ -800,7 +816,8 @@ static void > >> >> >> intel_dsi_pre_enable(struct > >> >> intel_encoder *encoder, > >> >> >> I915_WRITE(DSPCLK_GATE_D, val); > >> >> >> } > >> >> >> > >> >> >> - intel_dsi_prepare(encoder, pipe_config); > >> >> >> + if (!IS_GEMINILAKE(dev_priv)) > >> >> >> + intel_dsi_prepare(encoder, pipe_config); > >> >> >> > >> >> >> /* Power on, try both CRC pmic gpio and VBT */ > >> >> >> if (intel_dsi->gpio_panel) > >> >> >> @@ -812,7 +829,7 @@ static void intel_dsi_pre_enable(struct > >> >> intel_encoder *encoder, > >> >> >> intel_dsi_vbt_exec_sequence(intel_dsi, > >> >> >> MIPI_SEQ_DEASSERT_RESET); > >> >> >> > >> >> >> /* Put device in ready state (LP-11) */ > >> >> >> - intel_dsi_device_ready(encoder); > >> >> >> + intel_dsi_device_ready(encoder, pipe_config); > >> >> >> > >> >> >> /* Send initialization commands in LP mode */ > >> >> >> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); > >> >> >> -- > >> >> >> 1.9.1 > >> >> >> > >> >> >> _______________________________________________ > >> >> >> Intel-gfx mailing list > >> >> >> Intel-gfx@lists.freedesktop.org > >> >> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > >> >> > >> >> -- > >> >> Jani Nikula, Intel Open Source Technology Center > >> > >> -- > >> Jani Nikula, Intel Open Source Technology Center > > -- > Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/glk: Calculate high/low switch count for GLK 2017-05-09 13:29 [PATCH 1/2] drm/i915/glk: Calculate high/low switch count for GLK Madhav Chauhan 2017-05-09 13:29 ` [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI Madhav Chauhan @ 2017-05-09 14:09 ` Patchwork 2017-05-15 15:48 ` [PATCH 1/2] " Jani Nikula 2 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2017-05-09 14:09 UTC (permalink / raw) To: Madhav Chauhan; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/glk: Calculate high/low switch count for GLK URL : https://patchwork.freedesktop.org/series/24173/ State : success == Summary == Series 24173v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/24173/revisions/1/mbox/ Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: fail -> PASS (fi-snb-2600) fdo#100007 Test gem_exec_suspend: Subgroup basic-s4-devices: dmesg-warn -> PASS (fi-kbl-7560u) fdo#100125 fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007 fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125 fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:439s fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:431s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:587s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:518s fi-bxt-t5700 total:278 pass:258 dwarn:0 dfail:0 fail:0 skip:20 time:546s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:488s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:488s fi-elk-e7500 total:278 pass:229 dwarn:0 dfail:0 fail:0 skip:49 time:423s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:411s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:408s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:424s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:488s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:477s fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:468s fi-kbl-7560u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:575s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:463s fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:575s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:464s fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:510s fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:439s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:539s fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:412s 417babaa12ad98dad2c39f361612f1afe6894816 drm-tip: 2017y-05m-09d-13h-13m-23s UTC integration manifest eda9051 drm/i915/glk: Enable cold boot for GLK DSI 0f29175 drm/i915/glk: Calculate high/low switch count for GLK == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4648/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915/glk: Calculate high/low switch count for GLK 2017-05-09 13:29 [PATCH 1/2] drm/i915/glk: Calculate high/low switch count for GLK Madhav Chauhan 2017-05-09 13:29 ` [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI Madhav Chauhan 2017-05-09 14:09 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/glk: Calculate high/low switch count for GLK Patchwork @ 2017-05-15 15:48 ` Jani Nikula 2 siblings, 0 replies; 12+ messages in thread From: Jani Nikula @ 2017-05-15 15:48 UTC (permalink / raw) To: Madhav Chauhan, intel-gfx Cc: ander.conselvan.de.oliveira, shashidhar.hiremath On Tue, 09 May 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote: > As per BSPEC, high/low switch count to be programmed in > terms of byteclock using exit_zero_count and prep_count. > For Geminilake exit/prep counts are already calculated > in terms of byteclock. This patch calculates high/low > switch count using counts value in byteclock, old calculation > leads to screen flicker/shift issue while resuming from S3/S4. > > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Pushed this patch to drm-intel-next-queued, thanks for the patch. BR, Jani. > --- > drivers/gpu/drm/i915/intel_dsi_vbt.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c > index 0dce779..7158c7c 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c > +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c > @@ -694,8 +694,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) > clk_zero_cnt << 8 | prepare_cnt; > > /* > - * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2 > - * + 10UI + Extra Byte Count > + * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * > + * mul + 10UI + Extra Byte Count > * > * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count > * Extra Byte Count is calculated according to number of lanes. > @@ -708,8 +708,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) > /* B044 */ > /* FIXME: > * The comment above does not match with the code */ > - lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 + > - exit_zero_cnt * 2 + 10, 8); > + lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + > + exit_zero_cnt * mul + 10, 8); > > hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/2] drm/i915/glk: Calculate high/low switch count for GLK @ 2017-05-08 15:29 Madhav Chauhan 0 siblings, 0 replies; 12+ messages in thread From: Madhav Chauhan @ 2017-05-08 15:29 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, ander.conselvan.de.oliveira, shashidhar.hiremath As per BSPEC, high/low switch count to be programmed in terms of byteclock using exit_zero_count and prep_count. For Geminilake exit/prep counts are already calculated in terms of byteclock. This patch calculates high/low switch count using counts value in byteclock, old calculation leads to screen flicker/shift issue while resuming from S3/S4. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> --- drivers/gpu/drm/i915/intel_dsi_vbt.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c index 0dce779..7158c7c 100644 --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c @@ -694,8 +694,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) clk_zero_cnt << 8 | prepare_cnt; /* - * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2 - * + 10UI + Extra Byte Count + * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * + * mul + 10UI + Extra Byte Count * * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count * Extra Byte Count is calculated according to number of lanes. @@ -708,8 +708,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) /* B044 */ /* FIXME: * The comment above does not match with the code */ - lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 + - exit_zero_cnt * 2 + 10, 8); + lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + + exit_zero_cnt * mul + 10, 8); hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-05-30 9:11 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-05-09 13:29 [PATCH 1/2] drm/i915/glk: Calculate high/low switch count for GLK Madhav Chauhan 2017-05-09 13:29 ` [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK DSI Madhav Chauhan 2017-05-09 13:58 ` Ville Syrjälä 2017-05-15 15:49 ` Jani Nikula 2017-05-15 17:42 ` Chauhan, Madhav 2017-05-24 13:51 ` Jani Nikula 2017-05-24 18:00 ` Chauhan, Madhav 2017-05-30 7:03 ` Jani Nikula 2017-05-30 9:10 ` Chauhan, Madhav 2017-05-09 14:09 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/glk: Calculate high/low switch count for GLK Patchwork 2017-05-15 15:48 ` [PATCH 1/2] " Jani Nikula -- strict thread matches above, loose matches on Subject: below -- 2017-05-08 15:29 Madhav Chauhan
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