From: Nam Cao <namcao@linutronix.de>
To: Charlie Jenkins via B4 Relay
<devnull+thecharlesjenkins.gmail.com@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,
Atish Patra <atish.patra@linux.dev>,
Conor Dooley <conor@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Andrew Morton <akpm@linux-foundation.org>,
Shuah Khan <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <thecharlesjenkins@gmail.com>
Subject: Re: [PATCH 04/16] riscv: kprobes: Use generated instruction headers
Date: Thu, 11 Jun 2026 08:14:27 +0200 [thread overview]
Message-ID: <87mrx1eh8c.fsf@yellow.woof> (raw)
In-Reply-To: <20260407-riscv_insn_table-v1-4-54b4736a1e77@gmail.com>
Charlie Jenkins via B4 Relay
<devnull+thecharlesjenkins.gmail.com@kernel.org> writes:
> bool __kprobes simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs)
> {
> - return simulate_c_jr_jalr(opcode, addr, regs, false);
> + unsigned long next_addr;
> + unsigned long *regs_ptr = (unsigned long *)regs;
> +
> + next_addr = regs_ptr[riscv_insn_c_jr_extract_xs1(opcode)];
> + instruction_pointer_set(regs, next_addr);
> +
> + regs->ra = addr + 2;
c.jr does not change ra.
> + return true;
> }
We have CONFIG_RISCV_KPROBES_KUNIT now, please try that.
Nam
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http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Nam Cao <namcao@linutronix.de>
To: Charlie Jenkins via B4 Relay
<devnull+thecharlesjenkins.gmail.com@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,
Atish Patra <atish.patra@linux.dev>,
Conor Dooley <conor@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Andrew Morton <akpm@linux-foundation.org>,
Shuah Khan <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <thecharlesjenkins@gmail.com>
Subject: Re: [PATCH 04/16] riscv: kprobes: Use generated instruction headers
Date: Thu, 11 Jun 2026 08:14:27 +0200 [thread overview]
Message-ID: <87mrx1eh8c.fsf@yellow.woof> (raw)
In-Reply-To: <20260407-riscv_insn_table-v1-4-54b4736a1e77@gmail.com>
Charlie Jenkins via B4 Relay
<devnull+thecharlesjenkins.gmail.com@kernel.org> writes:
> bool __kprobes simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs)
> {
> - return simulate_c_jr_jalr(opcode, addr, regs, false);
> + unsigned long next_addr;
> + unsigned long *regs_ptr = (unsigned long *)regs;
> +
> + next_addr = regs_ptr[riscv_insn_c_jr_extract_xs1(opcode)];
> + instruction_pointer_set(regs, next_addr);
> +
> + regs->ra = addr + 2;
c.jr does not change ra.
> + return true;
> }
We have CONFIG_RISCV_KPROBES_KUNIT now, please try that.
Nam
WARNING: multiple messages have this Message-ID (diff)
From: Nam Cao <namcao@linutronix.de>
To: Charlie Jenkins via B4 Relay
<devnull+thecharlesjenkins.gmail.com@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,
Atish Patra <atish.patra@linux.dev>,
Conor Dooley <conor@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Andrew Morton <akpm@linux-foundation.org>,
Shuah Khan <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <thecharlesjenkins@gmail.com>
Subject: Re: [PATCH 04/16] riscv: kprobes: Use generated instruction headers
Date: Thu, 11 Jun 2026 08:14:27 +0200 [thread overview]
Message-ID: <87mrx1eh8c.fsf@yellow.woof> (raw)
In-Reply-To: <20260407-riscv_insn_table-v1-4-54b4736a1e77@gmail.com>
Charlie Jenkins via B4 Relay
<devnull+thecharlesjenkins.gmail.com@kernel.org> writes:
> bool __kprobes simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs)
> {
> - return simulate_c_jr_jalr(opcode, addr, regs, false);
> + unsigned long next_addr;
> + unsigned long *regs_ptr = (unsigned long *)regs;
> +
> + next_addr = regs_ptr[riscv_insn_c_jr_extract_xs1(opcode)];
> + instruction_pointer_set(regs, next_addr);
> +
> + regs->ra = addr + 2;
c.jr does not change ra.
> + return true;
> }
We have CONFIG_RISCV_KPROBES_KUNIT now, please try that.
Nam
_______________________________________________
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next prev parent reply other threads:[~2026-06-11 6:14 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-08 4:45 [PATCH 00/16] riscv: Generate riscv instruction functions Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 01/16] riscv: Introduce instruction table generation Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-06-10 15:56 ` Nam Cao
2026-06-10 15:56 ` Nam Cao
2026-06-10 15:56 ` Nam Cao
2026-06-11 1:06 ` Charlie Jenkins
2026-06-11 1:06 ` Charlie Jenkins
2026-06-11 1:06 ` Charlie Jenkins
2026-06-11 5:21 ` Nam Cao
2026-06-11 5:21 ` Nam Cao
2026-06-11 5:21 ` Nam Cao
2026-04-08 4:45 ` [PATCH 02/16] riscv: alternatives: Use generated instruction headers for patching code Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 03/16] riscv: kgdb: Use generated instruction headers Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-06-11 6:08 ` Nam Cao
2026-06-11 6:08 ` Nam Cao
2026-06-11 6:08 ` Nam Cao
2026-04-08 4:45 ` [PATCH 04/16] riscv: kprobes: " Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-06-11 6:14 ` Nam Cao [this message]
2026-06-11 6:14 ` Nam Cao
2026-06-11 6:14 ` Nam Cao
2026-06-11 6:22 ` Nam Cao
2026-06-11 6:22 ` Nam Cao
2026-06-11 6:22 ` Nam Cao
2026-04-08 4:45 ` [PATCH 05/16] riscv: cfi: " Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 06/16] riscv: Use generated instruction headers for misaligned loads/stores Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 07/16] riscv: kvm: Use generated instruction headers for csr code Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 08/16] riscv: kvm: Fix MMIO emulation for sign-extended insns Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 09/16] KVM: device: Add test device Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 10/16] KVM: riscv: selftests: Add mmio test Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 11/16] riscv: kvm: Use generated instruction headers for mmio emulation Charlie Jenkins
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` [PATCH 12/16] riscv: kvm: Add emulated test csr Charlie Jenkins
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` [PATCH 13/16] KVM: riscv: selftests: Add csr emulation test Charlie Jenkins
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` [PATCH 14/16] riscv: kvm: Use generated instruction headers for csr emulation Charlie Jenkins
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` [PATCH 15/16] riscv: kexec: Use generated instruction headers for kexec relocations Charlie Jenkins
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` [PATCH 16/16] riscv: Remove unused instruction headers Charlie Jenkins
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` Charlie Jenkins via B4 Relay
2026-04-08 17:58 ` [PATCH 1/16] riscv: Introduce instruction table generation Charlie Jenkins
2026-04-08 17:58 ` Charlie Jenkins
2026-04-08 17:58 ` Charlie Jenkins
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