* [PATCH 0/2] drm/i915: VLV clock gating fixes @ 2013-05-21 15:01 ville.syrjala 2013-05-21 15:01 ` [PATCH 1/2] drm/i915: VLV doesn't have the ILK+ style LP watermark registers ville.syrjala 2013-05-21 15:01 ` [PATCH 2/2] drm/i915: Fix DSPCLK_GATE_D for VLV ville.syrjala 0 siblings, 2 replies; 6+ messages in thread From: ville.syrjala @ 2013-05-21 15:01 UTC (permalink / raw) To: intel-gfx I spotted a few invalid register accesses in valleyview_init_clock_gating() while trawling through the clock gating code. This series tries to fix them. Compile tested only. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] drm/i915: VLV doesn't have the ILK+ style LP watermark registers 2013-05-21 15:01 [PATCH 0/2] drm/i915: VLV clock gating fixes ville.syrjala @ 2013-05-21 15:01 ` ville.syrjala 2013-06-05 7:57 ` Jani Nikula 2013-05-21 15:01 ` [PATCH 2/2] drm/i915: Fix DSPCLK_GATE_D for VLV ville.syrjala 1 sibling, 1 reply; 6+ messages in thread From: ville.syrjala @ 2013-05-21 15:01 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> The LP watermark registers don't exist on VLV, so don't touch them. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8a90cf3..a1a931c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4284,10 +4284,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; int pipe; - I915_WRITE(WM3_LP_ILK, 0); - I915_WRITE(WM2_LP_ILK, 0); - I915_WRITE(WM1_LP_ILK, 0); - I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); /* WaDisableEarlyCull:vlv */ -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: VLV doesn't have the ILK+ style LP watermark registers 2013-05-21 15:01 ` [PATCH 1/2] drm/i915: VLV doesn't have the ILK+ style LP watermark registers ville.syrjala @ 2013-06-05 7:57 ` Jani Nikula 0 siblings, 0 replies; 6+ messages in thread From: Jani Nikula @ 2013-06-05 7:57 UTC (permalink / raw) To: ville.syrjala, intel-gfx On Tue, 21 May 2013, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The LP watermark registers don't exist on VLV, so don't touch them. Reviewed-by: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 8a90cf3..a1a931c 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4284,10 +4284,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > int pipe; > > - I915_WRITE(WM3_LP_ILK, 0); > - I915_WRITE(WM2_LP_ILK, 0); > - I915_WRITE(WM1_LP_ILK, 0); > - > I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); > > /* WaDisableEarlyCull:vlv */ > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915: Fix DSPCLK_GATE_D for VLV 2013-05-21 15:01 [PATCH 0/2] drm/i915: VLV clock gating fixes ville.syrjala 2013-05-21 15:01 ` [PATCH 1/2] drm/i915: VLV doesn't have the ILK+ style LP watermark registers ville.syrjala @ 2013-05-21 15:01 ` ville.syrjala 2013-06-05 7:46 ` Jani Nikula 1 sibling, 1 reply; 6+ messages in thread From: ville.syrjala @ 2013-05-21 15:01 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Fix the DSPCLK_GATE_D access for VLV. The code incorrectly tried to poke at the ILK+ version of the register which is at the wrong offset. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 55caedb..4e8aabd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1208,7 +1208,7 @@ #define DSTATE_PLL_D3_OFF (1<<3) #define DSTATE_GFX_CLOCK_GATING (1<<1) #define DSTATE_DOT_CLOCK_GATING (1<<0) -#define DSPCLK_GATE_D 0x6200 +#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200) # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a1a931c..4c8ce90 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4284,7 +4284,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; int pipe; - I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); + I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); /* WaDisableEarlyCull:vlv */ I915_WRITE(_3D_CHICKEN3, -- 1.8.1.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Fix DSPCLK_GATE_D for VLV 2013-05-21 15:01 ` [PATCH 2/2] drm/i915: Fix DSPCLK_GATE_D for VLV ville.syrjala @ 2013-06-05 7:46 ` Jani Nikula 2013-06-05 8:01 ` Daniel Vetter 0 siblings, 1 reply; 6+ messages in thread From: Jani Nikula @ 2013-06-05 7:46 UTC (permalink / raw) To: ville.syrjala, intel-gfx On Tue, 21 May 2013, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Fix the DSPCLK_GATE_D access for VLV. The code incorrectly tried to > poke at the ILK+ version of the register which is at the wrong offset. Reviewed-by: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 55caedb..4e8aabd 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1208,7 +1208,7 @@ > #define DSTATE_PLL_D3_OFF (1<<3) > #define DSTATE_GFX_CLOCK_GATING (1<<1) > #define DSTATE_DOT_CLOCK_GATING (1<<0) > -#define DSPCLK_GATE_D 0x6200 > +#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200) > # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ > # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ > # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index a1a931c..4c8ce90 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4284,7 +4284,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > int pipe; > > - I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); > + I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > > /* WaDisableEarlyCull:vlv */ > I915_WRITE(_3D_CHICKEN3, > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Fix DSPCLK_GATE_D for VLV 2013-06-05 7:46 ` Jani Nikula @ 2013-06-05 8:01 ` Daniel Vetter 0 siblings, 0 replies; 6+ messages in thread From: Daniel Vetter @ 2013-06-05 8:01 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Wed, Jun 05, 2013 at 10:46:41AM +0300, Jani Nikula wrote: > On Tue, 21 May 2013, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Fix the DSPCLK_GATE_D access for VLV. The code incorrectly tried to > > poke at the ILK+ version of the register which is at the wrong offset. > > Reviewed-by: Jani Nikula <jani.nikula@intel.com> Both merged, thanks. -Daniel > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 2 +- > > drivers/gpu/drm/i915/intel_pm.c | 2 +- > > 2 files changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 55caedb..4e8aabd 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1208,7 +1208,7 @@ > > #define DSTATE_PLL_D3_OFF (1<<3) > > #define DSTATE_GFX_CLOCK_GATING (1<<1) > > #define DSTATE_DOT_CLOCK_GATING (1<<0) > > -#define DSPCLK_GATE_D 0x6200 > > +#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200) > > # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ > > # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ > > # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index a1a931c..4c8ce90 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4284,7 +4284,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > > struct drm_i915_private *dev_priv = dev->dev_private; > > int pipe; > > > > - I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); > > + I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > > > > /* WaDisableEarlyCull:vlv */ > > I915_WRITE(_3D_CHICKEN3, > > -- > > 1.8.1.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Technology Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2013-06-05 8:01 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-05-21 15:01 [PATCH 0/2] drm/i915: VLV clock gating fixes ville.syrjala 2013-05-21 15:01 ` [PATCH 1/2] drm/i915: VLV doesn't have the ILK+ style LP watermark registers ville.syrjala 2013-06-05 7:57 ` Jani Nikula 2013-05-21 15:01 ` [PATCH 2/2] drm/i915: Fix DSPCLK_GATE_D for VLV ville.syrjala 2013-06-05 7:46 ` Jani Nikula 2013-06-05 8:01 ` Daniel Vetter
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.