Re: [PATCH v4 0/4] drm/bridge: nwl-dsi: Various fixes

[Esben Haabendal <esben@geanix.com>]

"Esben Haabendal" <esben@geanix.com> writes:

> This series brings a few patches fixing horizontal sync timing, EOTP packet
> behavior and hsync/vsync polarity selection when using DCSS endpoint, as
> well as a small fix to properly handle if/when nwl_dsi_mode_set() fails.
>
> The 3rd commit ("Correct auto-insert EOTP behavior") is taken directly from
> NXP vendor tree, so I have kept Author unchanged, although I have modified
> the commit message. Let me know if I should change Author for that.
>
> Signed-off-by: Esben Haabendal <esben@geanix.com>

Is there anything I can or should do to get this patch series merged or
at least some review feedback that I can work on?

/Esben

> ---
> Changes in v4:
> - Change calculation of hfp/hbp/hsa to use the raw clock rates directly to
>   eliminate intermediate rounding errors.
> - Drop patch 4 (will be included in follow-up patch series, together with
>   a patch addressing the unblanced resource teardown and PM runtime
>   underflow problems in the error path).
> - Link to v3: https://patch.msgid.link/20260810-nwl-dsi-fixes-v3-0-256da9d672e1@geanix.com
>
> Changes in v3:
> - Added Fixes and Cc: stable tags.
> - Split patch 1 into two, with change of endpoint mux control in a separate
>   patch.
> - Fixed mux_control_try_select() state argument.
> - Link to v2: https://patch.msgid.link/20260803-nwl-dsi-fixes-v2-0-1809a0ac453f@geanix.com
>
> Changes in v2:
> - Added safeguard against small horizontal sync timings, protecting against
>   division by zero and integer underflow.
> - Added error handling of nwl_dsi_mode_set() call.
> - Link to v1: https://patch.msgid.link/20260710-nwl-dsi-fixes-v1-0-927d918a86ad@geanix.com
>
> To: Andrzej Hajda <andrzej.hajda@intel.com>
> To: Neil Armstrong <neil.armstrong@linaro.org>
> To: Robert Foss <rfoss@kernel.org>
> To: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> To: Jonas Karlman <jonas@kwiboo.se>
> To: Jernej Skrabec <jernej.skrabec@gmail.com>
> To: Luca Ceresoli <luca.ceresoli@bootlin.com>
> To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> To: Maxime Ripard <mripard@kernel.org>
> To: Thomas Zimmermann <tzimmermann@suse.de>
> To: David Airlie <airlied@gmail.com>
> To: Simona Vetter <simona@ffwll.ch>
> To: Guido Günther <agx@sigxcpu.org>
> To: Fabio Estevam <festevam@gmail.com>
> To: Robert Chiras <robert.chiras@nxp.com>
> To: Sam Ravnborg <sam@ravnborg.org>
> Cc: dri-devel@lists.freedesktop.org
> Cc: linux-kernel@vger.kernel.org
>
> ---
> Esben Haabendal (3):
>       drm/bridge: nwl-dsi: Cleanup endpoint mux control selection
>       drm/bridge: nwl-dsi: Limit LCDIF specific sync override
>       drm/bridge: nwl-dsi: Correct MIPI DSI horizontal sync timing
>
> Robert Chiras (1):
>       drm/bridge: nwl-dsi: Correct auto-insert EOTP behavior
>
>  drivers/gpu/drm/bridge/nwl-dsi.c | 87 ++++++++++++++++++++++++++++++++++------
>  1 file changed, 74 insertions(+), 13 deletions(-)
> ---
> base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
> change-id: 20260710-nwl-dsi-fixes-c148b0adb685
>
> Best regards,
> --
> Esben Haabendal <esben@geanix.com>