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From: Marc Zyngier <maz@kernel.org>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v7 06/12] arm64: tlb: Refactor the core flush algorithm of __flush_tlb_range
Date: Thu, 27 Jul 2023 11:58:50 +0100	[thread overview]
Message-ID: <87r0otr579.wl-maz@kernel.org> (raw)
In-Reply-To: <20230722022251.3446223-7-rananta@google.com>

On Sat, 22 Jul 2023 03:22:45 +0100,
Raghavendra Rao Ananta <rananta@google.com> wrote:
> 
> Currently, the core TLB flush functionality of __flush_tlb_range()
> hardcodes vae1is (and variants) for the flush operation. In the
> upcoming patches, the KVM code reuses this core algorithm with
> ipas2e1is for range based TLB invalidations based on the IPA.
> Hence, extract the core flush functionality of __flush_tlb_range()
> into its own macro that accepts an 'op' argument to pass any
> TLBI operation, such that other callers (KVM) can benefit.
> 
> No functional changes intended.
> 
> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> Reviewed-by: Gavin Shan <gshan@redhat.com>
> Reviewed-by: Shaoqin Huang <shahuang@redhat.com>
> ---
>  arch/arm64/include/asm/tlbflush.h | 109 +++++++++++++++---------------
>  1 file changed, 56 insertions(+), 53 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index 412a3b9a3c25..f7fafba25add 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -278,14 +278,62 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
>   */
>  #define MAX_TLBI_OPS	PTRS_PER_PTE
>  
> +/* When the CPU does not support TLB range operations, flush the TLB
> + * entries one by one at the granularity of 'stride'. If the TLB
> + * range ops are supported, then:

Comment format (the original was correct).

> + *
> + * 1. If 'pages' is odd, flush the first page through non-range
> + *    operations;
> + *
> + * 2. For remaining pages: the minimum range granularity is decided
> + *    by 'scale', so multiple range TLBI operations may be required.
> + *    Start from scale = 0, flush the corresponding number of pages
> + *    ((num+1)*2^(5*scale+1) starting from 'addr'), then increase it
> + *    until no pages left.
> + *
> + * Note that certain ranges can be represented by either num = 31 and
> + * scale or num = 0 and scale + 1. The loop below favours the latter
> + * since num is limited to 30 by the __TLBI_RANGE_NUM() macro.
> + */
> +#define __flush_tlb_range_op(op, start, pages, stride,			\
> +				asid, tlb_level, tlbi_user)		\

If you make this a common macro, please document the parameters, and
what the constraints are. For example, what does tlbi_user mean for an
IPA invalidation?

	M.

-- 
Without deviation from the norm, progress is not possible.


WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Raghavendra Rao Ananta <rananta@google.com>
Cc: Oliver Upton <oliver.upton@linux.dev>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	Huacai Chen <chenhuacai@kernel.org>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Jing Zhang <jingzhangos@google.com>,
	Reiji Watanabe <reijiw@google.com>,
	Colton Lewis <coltonlewis@google.com>,
	David Matlack <dmatlack@google.com>,
	linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
	linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	kvm@vger.kernel.org, Catalin Marinas <catalin.marinas@arm.com>,
	Gavin Shan <gshan@redhat.com>,
	Shaoqin Huang <shahuang@redhat.com>
Subject: Re: [PATCH v7 06/12] arm64: tlb: Refactor the core flush algorithm of __flush_tlb_range
Date: Thu, 27 Jul 2023 11:58:50 +0100	[thread overview]
Message-ID: <87r0otr579.wl-maz@kernel.org> (raw)
In-Reply-To: <20230722022251.3446223-7-rananta@google.com>

On Sat, 22 Jul 2023 03:22:45 +0100,
Raghavendra Rao Ananta <rananta@google.com> wrote:
> 
> Currently, the core TLB flush functionality of __flush_tlb_range()
> hardcodes vae1is (and variants) for the flush operation. In the
> upcoming patches, the KVM code reuses this core algorithm with
> ipas2e1is for range based TLB invalidations based on the IPA.
> Hence, extract the core flush functionality of __flush_tlb_range()
> into its own macro that accepts an 'op' argument to pass any
> TLBI operation, such that other callers (KVM) can benefit.
> 
> No functional changes intended.
> 
> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> Reviewed-by: Gavin Shan <gshan@redhat.com>
> Reviewed-by: Shaoqin Huang <shahuang@redhat.com>
> ---
>  arch/arm64/include/asm/tlbflush.h | 109 +++++++++++++++---------------
>  1 file changed, 56 insertions(+), 53 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index 412a3b9a3c25..f7fafba25add 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -278,14 +278,62 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
>   */
>  #define MAX_TLBI_OPS	PTRS_PER_PTE
>  
> +/* When the CPU does not support TLB range operations, flush the TLB
> + * entries one by one at the granularity of 'stride'. If the TLB
> + * range ops are supported, then:

Comment format (the original was correct).

> + *
> + * 1. If 'pages' is odd, flush the first page through non-range
> + *    operations;
> + *
> + * 2. For remaining pages: the minimum range granularity is decided
> + *    by 'scale', so multiple range TLBI operations may be required.
> + *    Start from scale = 0, flush the corresponding number of pages
> + *    ((num+1)*2^(5*scale+1) starting from 'addr'), then increase it
> + *    until no pages left.
> + *
> + * Note that certain ranges can be represented by either num = 31 and
> + * scale or num = 0 and scale + 1. The loop below favours the latter
> + * since num is limited to 30 by the __TLBI_RANGE_NUM() macro.
> + */
> +#define __flush_tlb_range_op(op, start, pages, stride,			\
> +				asid, tlb_level, tlbi_user)		\

If you make this a common macro, please document the parameters, and
what the constraints are. For example, what does tlbi_user mean for an
IPA invalidation?

	M.

-- 
Without deviation from the norm, progress is not possible.

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Raghavendra Rao Ananta <rananta@google.com>
Cc: Oliver Upton <oliver.upton@linux.dev>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	Huacai Chen <chenhuacai@kernel.org>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Jing Zhang <jingzhangos@google.com>,
	Reiji Watanabe <reijiw@google.com>,
	Colton Lewis <coltonlewis@google.com>,
	David Matlack <dmatlack@google.com>,
	linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
	linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	kvm@vger.kernel.org, Catalin Marinas <catalin.marinas@arm.com>,
	Gavin Shan <gshan@redhat.com>,
	Shaoqin Huang <shahuang@redhat.com>
Subject: Re: [PATCH v7 06/12] arm64: tlb: Refactor the core flush algorithm of __flush_tlb_range
Date: Thu, 27 Jul 2023 11:58:50 +0100	[thread overview]
Message-ID: <87r0otr579.wl-maz@kernel.org> (raw)
In-Reply-To: <20230722022251.3446223-7-rananta@google.com>

On Sat, 22 Jul 2023 03:22:45 +0100,
Raghavendra Rao Ananta <rananta@google.com> wrote:
> 
> Currently, the core TLB flush functionality of __flush_tlb_range()
> hardcodes vae1is (and variants) for the flush operation. In the
> upcoming patches, the KVM code reuses this core algorithm with
> ipas2e1is for range based TLB invalidations based on the IPA.
> Hence, extract the core flush functionality of __flush_tlb_range()
> into its own macro that accepts an 'op' argument to pass any
> TLBI operation, such that other callers (KVM) can benefit.
> 
> No functional changes intended.
> 
> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> Reviewed-by: Gavin Shan <gshan@redhat.com>
> Reviewed-by: Shaoqin Huang <shahuang@redhat.com>
> ---
>  arch/arm64/include/asm/tlbflush.h | 109 +++++++++++++++---------------
>  1 file changed, 56 insertions(+), 53 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index 412a3b9a3c25..f7fafba25add 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -278,14 +278,62 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
>   */
>  #define MAX_TLBI_OPS	PTRS_PER_PTE
>  
> +/* When the CPU does not support TLB range operations, flush the TLB
> + * entries one by one at the granularity of 'stride'. If the TLB
> + * range ops are supported, then:

Comment format (the original was correct).

> + *
> + * 1. If 'pages' is odd, flush the first page through non-range
> + *    operations;
> + *
> + * 2. For remaining pages: the minimum range granularity is decided
> + *    by 'scale', so multiple range TLBI operations may be required.
> + *    Start from scale = 0, flush the corresponding number of pages
> + *    ((num+1)*2^(5*scale+1) starting from 'addr'), then increase it
> + *    until no pages left.
> + *
> + * Note that certain ranges can be represented by either num = 31 and
> + * scale or num = 0 and scale + 1. The loop below favours the latter
> + * since num is limited to 30 by the __TLBI_RANGE_NUM() macro.
> + */
> +#define __flush_tlb_range_op(op, start, pages, stride,			\
> +				asid, tlb_level, tlbi_user)		\

If you make this a common macro, please document the parameters, and
what the constraints are. For example, what does tlbi_user mean for an
IPA invalidation?

	M.

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Raghavendra Rao Ananta <rananta@google.com>
Cc: Oliver Upton <oliver.upton@linux.dev>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	Huacai Chen <chenhuacai@kernel.org>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Jing Zhang <jingzhangos@google.com>,
	Reiji Watanabe <reijiw@google.com>,
	Colton Lewis <coltonlewis@google.com>,
	David Matlack <dmatlack@google.com>,
	linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
	linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	kvm@vger.kernel.org, Catalin Marinas <catalin.marinas@arm.com>,
	Gavin Shan <gshan@redhat.com>,
	Shaoqin Huang <shahuang@redhat.com>
Subject: Re: [PATCH v7 06/12] arm64: tlb: Refactor the core flush algorithm of __flush_tlb_range
Date: Thu, 27 Jul 2023 11:58:50 +0100	[thread overview]
Message-ID: <87r0otr579.wl-maz@kernel.org> (raw)
In-Reply-To: <20230722022251.3446223-7-rananta@google.com>

On Sat, 22 Jul 2023 03:22:45 +0100,
Raghavendra Rao Ananta <rananta@google.com> wrote:
> 
> Currently, the core TLB flush functionality of __flush_tlb_range()
> hardcodes vae1is (and variants) for the flush operation. In the
> upcoming patches, the KVM code reuses this core algorithm with
> ipas2e1is for range based TLB invalidations based on the IPA.
> Hence, extract the core flush functionality of __flush_tlb_range()
> into its own macro that accepts an 'op' argument to pass any
> TLBI operation, such that other callers (KVM) can benefit.
> 
> No functional changes intended.
> 
> Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> Reviewed-by: Gavin Shan <gshan@redhat.com>
> Reviewed-by: Shaoqin Huang <shahuang@redhat.com>
> ---
>  arch/arm64/include/asm/tlbflush.h | 109 +++++++++++++++---------------
>  1 file changed, 56 insertions(+), 53 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index 412a3b9a3c25..f7fafba25add 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -278,14 +278,62 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
>   */
>  #define MAX_TLBI_OPS	PTRS_PER_PTE
>  
> +/* When the CPU does not support TLB range operations, flush the TLB
> + * entries one by one at the granularity of 'stride'. If the TLB
> + * range ops are supported, then:

Comment format (the original was correct).

> + *
> + * 1. If 'pages' is odd, flush the first page through non-range
> + *    operations;
> + *
> + * 2. For remaining pages: the minimum range granularity is decided
> + *    by 'scale', so multiple range TLBI operations may be required.
> + *    Start from scale = 0, flush the corresponding number of pages
> + *    ((num+1)*2^(5*scale+1) starting from 'addr'), then increase it
> + *    until no pages left.
> + *
> + * Note that certain ranges can be represented by either num = 31 and
> + * scale or num = 0 and scale + 1. The loop below favours the latter
> + * since num is limited to 30 by the __TLBI_RANGE_NUM() macro.
> + */
> +#define __flush_tlb_range_op(op, start, pages, stride,			\
> +				asid, tlb_level, tlbi_user)		\

If you make this a common macro, please document the parameters, and
what the constraints are. For example, what does tlbi_user mean for an
IPA invalidation?

	M.

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2023-07-27 10:58 UTC|newest]

Thread overview: 228+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-22  2:22 [PATCH v7 00/12] KVM: arm64: Add support for FEAT_TLBIRANGE Raghavendra Rao Ananta
2023-07-22  2:22 ` Raghavendra Rao Ananta
2023-07-22  2:22 ` Raghavendra Rao Ananta
2023-07-22  2:22 ` Raghavendra Rao Ananta
2023-07-22  2:22 ` [PATCH v7 01/12] KVM: Rename kvm_arch_flush_remote_tlb() to kvm_arch_flush_remote_tlbs() Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-27 10:24   ` Marc Zyngier
2023-07-27 10:24     ` Marc Zyngier
2023-07-27 10:24     ` Marc Zyngier
2023-07-27 10:24     ` Marc Zyngier
2023-07-31 17:21     ` Raghavendra Rao Ananta
2023-07-31 17:21       ` Raghavendra Rao Ananta
2023-07-31 17:21       ` Raghavendra Rao Ananta
2023-07-31 17:21       ` Raghavendra Rao Ananta
2023-07-31 21:42       ` Sean Christopherson
2023-07-31 21:42         ` Sean Christopherson
2023-07-31 21:42         ` Sean Christopherson
2023-07-31 21:42         ` Sean Christopherson
2023-08-01  0:42         ` Raghavendra Rao Ananta
2023-08-01  0:42           ` Raghavendra Rao Ananta
2023-08-01  0:42           ` Raghavendra Rao Ananta
2023-08-01  0:42           ` Raghavendra Rao Ananta
2023-08-02 15:54           ` Marc Zyngier
2023-08-02 15:54             ` Marc Zyngier
2023-08-02 15:54             ` Marc Zyngier
2023-08-02 15:54             ` Marc Zyngier
2023-08-02 16:10             ` Sean Christopherson
2023-08-02 16:10               ` Sean Christopherson
2023-08-02 16:10               ` Sean Christopherson
2023-08-02 16:10               ` Sean Christopherson
2023-08-02 23:30               ` Raghavendra Rao Ananta
2023-08-02 23:30                 ` Raghavendra Rao Ananta
2023-08-02 23:30                 ` Raghavendra Rao Ananta
2023-08-02 23:30                 ` Raghavendra Rao Ananta
2023-07-22  2:22 ` [PATCH v7 02/12] KVM: arm64: Use kvm_arch_flush_remote_tlbs() Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-24  9:13   ` Shaoqin Huang
2023-07-24  9:13     ` Shaoqin Huang
2023-07-24  9:13     ` Shaoqin Huang
2023-07-27 10:25   ` Marc Zyngier
2023-07-27 10:25     ` Marc Zyngier
2023-07-27 10:25     ` Marc Zyngier
2023-07-27 10:25     ` Marc Zyngier
2023-07-31 21:50     ` Sean Christopherson
2023-07-31 21:50       ` Sean Christopherson
2023-07-31 21:50       ` Sean Christopherson
2023-07-31 21:50       ` Sean Christopherson
2023-08-02 15:55       ` Marc Zyngier
2023-08-02 15:55         ` Marc Zyngier
2023-08-02 15:55         ` Marc Zyngier
2023-08-02 15:55         ` Marc Zyngier
2023-08-02 23:28         ` Raghavendra Rao Ananta
2023-08-02 23:28           ` Raghavendra Rao Ananta
2023-08-02 23:28           ` Raghavendra Rao Ananta
2023-08-02 23:28           ` Raghavendra Rao Ananta
2023-08-04 18:19           ` Raghavendra Rao Ananta
2023-08-04 18:19             ` Raghavendra Rao Ananta
2023-08-04 18:19             ` Raghavendra Rao Ananta
2023-08-04 18:19             ` Raghavendra Rao Ananta
2023-08-08 15:07             ` Sean Christopherson
2023-08-08 15:07               ` Sean Christopherson
2023-08-08 15:07               ` Sean Christopherson
2023-08-08 15:07               ` Sean Christopherson
2023-08-08 16:19               ` Raghavendra Rao Ananta
2023-08-08 16:19                 ` Raghavendra Rao Ananta
2023-08-08 16:19                 ` Raghavendra Rao Ananta
2023-08-08 16:19                 ` Raghavendra Rao Ananta
2023-08-08 16:43                 ` Marc Zyngier
2023-08-08 16:43                   ` Marc Zyngier
2023-08-08 16:43                   ` Marc Zyngier
2023-08-08 16:43                   ` Marc Zyngier
2023-08-08 16:46                   ` Raghavendra Rao Ananta
2023-08-08 16:46                     ` Raghavendra Rao Ananta
2023-08-08 16:46                     ` Raghavendra Rao Ananta
2023-08-08 16:46                     ` Raghavendra Rao Ananta
2023-07-22  2:22 ` [PATCH v7 03/12] KVM: Remove CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-24  9:13   ` Shaoqin Huang
2023-07-24  9:13     ` Shaoqin Huang
2023-07-24  9:13     ` Shaoqin Huang
2023-07-22  2:22 ` [PATCH v7 04/12] KVM: Allow range-based TLB invalidation from common code Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-31 21:55   ` Sean Christopherson
2023-07-31 21:55     ` Sean Christopherson
2023-07-31 21:55     ` Sean Christopherson
2023-07-31 21:55     ` Sean Christopherson
2023-08-01  0:39     ` Raghavendra Rao Ananta
2023-08-01  0:39       ` Raghavendra Rao Ananta
2023-08-01  0:39       ` Raghavendra Rao Ananta
2023-08-01  0:39       ` Raghavendra Rao Ananta
2023-08-07  4:06   ` Anup Patel
2023-08-07  4:06     ` Anup Patel
2023-08-07  4:06     ` Anup Patel
2023-08-07  4:06     ` Anup Patel
2023-07-22  2:22 ` [PATCH v7 05/12] KVM: Move kvm_arch_flush_remote_tlbs_memslot() to " Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-27 10:53   ` Marc Zyngier
2023-07-27 10:53     ` Marc Zyngier
2023-07-27 10:53     ` Marc Zyngier
2023-07-27 10:53     ` Marc Zyngier
2023-07-31 17:30     ` Raghavendra Rao Ananta
2023-07-31 17:30       ` Raghavendra Rao Ananta
2023-07-31 17:30       ` Raghavendra Rao Ananta
2023-07-31 17:30       ` Raghavendra Rao Ananta
2023-08-07  4:06   ` Anup Patel
2023-08-07  4:06     ` Anup Patel
2023-08-07  4:06     ` Anup Patel
2023-08-07  4:06     ` Anup Patel
2023-07-22  2:22 ` [PATCH v7 06/12] arm64: tlb: Refactor the core flush algorithm of __flush_tlb_range Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-27 10:58   ` Marc Zyngier [this message]
2023-07-27 10:58     ` Marc Zyngier
2023-07-27 10:58     ` Marc Zyngier
2023-07-27 10:58     ` Marc Zyngier
2023-07-31 17:36     ` Raghavendra Rao Ananta
2023-07-31 17:36       ` Raghavendra Rao Ananta
2023-07-31 17:36       ` Raghavendra Rao Ananta
2023-07-31 17:36       ` Raghavendra Rao Ananta
2023-08-02 15:58       ` Marc Zyngier
2023-08-02 15:58         ` Marc Zyngier
2023-08-02 15:58         ` Marc Zyngier
2023-08-02 15:58         ` Marc Zyngier
2023-08-02 23:31         ` Raghavendra Rao Ananta
2023-08-02 23:31           ` Raghavendra Rao Ananta
2023-08-02 23:31           ` Raghavendra Rao Ananta
2023-08-02 23:31           ` Raghavendra Rao Ananta
2023-07-22  2:22 ` [PATCH v7 07/12] KVM: arm64: Implement __kvm_tlb_flush_vmid_range() Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-24  9:21   ` Shaoqin Huang
2023-07-24  9:21     ` Shaoqin Huang
2023-07-24  9:21     ` Shaoqin Huang
2023-07-27 12:40   ` Marc Zyngier
2023-07-27 12:40     ` Marc Zyngier
2023-07-27 12:40     ` Marc Zyngier
2023-07-27 12:40     ` Marc Zyngier
2023-07-31 17:45     ` Raghavendra Rao Ananta
2023-07-31 17:45       ` Raghavendra Rao Ananta
2023-07-31 17:45       ` Raghavendra Rao Ananta
2023-07-31 17:45       ` Raghavendra Rao Ananta
2023-07-22  2:22 ` [PATCH v7 08/12] KVM: arm64: Define kvm_tlb_flush_vmid_range() Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-27 12:47   ` Marc Zyngier
2023-07-27 12:47     ` Marc Zyngier
2023-07-27 12:47     ` Marc Zyngier
2023-07-27 12:47     ` Marc Zyngier
2023-07-27 13:01     ` Marc Zyngier
2023-07-27 13:01       ` Marc Zyngier
2023-07-27 13:01       ` Marc Zyngier
2023-07-27 13:01       ` Marc Zyngier
2023-07-31 18:01       ` Raghavendra Rao Ananta
2023-07-31 18:01         ` Raghavendra Rao Ananta
2023-07-31 18:01         ` Raghavendra Rao Ananta
2023-07-31 18:01         ` Raghavendra Rao Ananta
2023-08-02 23:25         ` Marc Zyngier
2023-08-02 23:25           ` Marc Zyngier
2023-08-02 23:25           ` Marc Zyngier
2023-08-02 23:25           ` Marc Zyngier
2023-07-22  2:22 ` [PATCH v7 09/12] KVM: arm64: Implement kvm_arch_flush_remote_tlbs_range() Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-27 12:48   ` Marc Zyngier
2023-07-27 12:48     ` Marc Zyngier
2023-07-27 12:48     ` Marc Zyngier
2023-07-27 12:48     ` Marc Zyngier
2023-07-22  2:22 ` [PATCH v7 10/12] KVM: arm64: Flush only the memslot after write-protect Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22 ` [PATCH v7 11/12] KVM: arm64: Invalidate the table entries upon a range Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22 ` [PATCH v7 12/12] KVM: arm64: Use TLBI range-based intructions for unmap Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-22  2:22   ` Raghavendra Rao Ananta
2023-07-24  9:34   ` Shaoqin Huang
2023-07-24  9:34     ` Shaoqin Huang
2023-07-24  9:34     ` Shaoqin Huang
2023-07-24 16:47     ` Raghavendra Rao Ananta
2023-07-24 16:47       ` Raghavendra Rao Ananta
2023-07-24 16:47       ` Raghavendra Rao Ananta
2023-07-25  2:32       ` Shaoqin Huang
2023-07-25  2:32         ` Shaoqin Huang
2023-07-25  2:32         ` Shaoqin Huang
2023-07-25 17:23         ` Raghavendra Rao Ananta
2023-07-25 17:23           ` Raghavendra Rao Ananta
2023-07-25 17:23           ` Raghavendra Rao Ananta
2023-07-26  4:06           ` Shaoqin Huang
2023-07-26  4:06             ` Shaoqin Huang
2023-07-26  4:06             ` Shaoqin Huang
2023-07-27 13:12   ` Marc Zyngier
2023-07-27 13:12     ` Marc Zyngier
2023-07-27 13:12     ` Marc Zyngier
2023-07-27 13:12     ` Marc Zyngier
2023-07-31 18:26     ` Raghavendra Rao Ananta
2023-07-31 18:26       ` Raghavendra Rao Ananta
2023-07-31 18:26       ` Raghavendra Rao Ananta
2023-07-31 18:26       ` Raghavendra Rao Ananta
2023-08-02 23:28       ` Marc Zyngier
2023-08-02 23:28         ` Marc Zyngier
2023-08-02 23:28         ` Marc Zyngier
2023-08-02 23:28         ` Marc Zyngier
2023-08-02 23:33         ` Raghavendra Rao Ananta
2023-08-02 23:33           ` Raghavendra Rao Ananta
2023-08-02 23:33           ` Raghavendra Rao Ananta
2023-08-02 23:33           ` Raghavendra Rao Ananta
2023-07-31 21:57 ` [PATCH v7 00/12] KVM: arm64: Add support for FEAT_TLBIRANGE Sean Christopherson
2023-07-31 21:57   ` Sean Christopherson
2023-07-31 21:57   ` Sean Christopherson
2023-07-31 21:57   ` Sean Christopherson

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