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From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Pierre Gondois <pierre.gondois@arm.com>, linux-kernel@vger.kernel.org
Cc: pierre.gondois@arm.com, Rob.Herring@arm.com,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Andrew Lunn <andrew@lunn.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Vadym Kochan <vadym.kochan@plvision.eu>,
	Chris Packham <chris.packham@alliedtelesis.co.nz>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 10/20] arm64: dts: Update cache properties for marvell
Date: Mon, 28 Nov 2022 01:09:48 +0100	[thread overview]
Message-ID: <87r0xo7xdf.fsf@BL-laptop> (raw)
In-Reply-To: <20221031092020.532456-1-pierre.gondois@arm.com>

Pierre Gondois <pierre.gondois@arm.com> writes:

> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>

Applied on mvebu/dt64

Thanks,

Gregory
> ---
>  arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi      | 1 +
>  arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
>  arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
>  arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
>  4 files changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> index 80b44c7df56a..d4770acec6ac 100644
> --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> @@ -49,6 +49,7 @@ cpu1: cpu@1 {
>  
>  		l2: l2-cache {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  	};
>  
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> index fcab5173fe67..990f70303fe6 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> @@ -51,6 +51,7 @@ l2: l2-cache {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  	};
>  
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> index 3db427122f9e..a7b8e001cc9c 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  
>  		l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  	};
>  };
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> index 68782f161f12..7740098fd108 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  
>  		l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  	};
>  };
> -- 
> 2.25.1
>

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Pierre Gondois <pierre.gondois@arm.com>, linux-kernel@vger.kernel.org
Cc: pierre.gondois@arm.com, Rob.Herring@arm.com,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Andrew Lunn <andrew@lunn.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Vadym Kochan <vadym.kochan@plvision.eu>,
	Chris Packham <chris.packham@alliedtelesis.co.nz>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 10/20] arm64: dts: Update cache properties for marvell
Date: Mon, 28 Nov 2022 01:09:48 +0100	[thread overview]
Message-ID: <87r0xo7xdf.fsf@BL-laptop> (raw)
In-Reply-To: <20221031092020.532456-1-pierre.gondois@arm.com>

Pierre Gondois <pierre.gondois@arm.com> writes:

> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>

Applied on mvebu/dt64

Thanks,

Gregory
> ---
>  arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi      | 1 +
>  arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
>  arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
>  arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
>  4 files changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> index 80b44c7df56a..d4770acec6ac 100644
> --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> @@ -49,6 +49,7 @@ cpu1: cpu@1 {
>  
>  		l2: l2-cache {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  	};
>  
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> index fcab5173fe67..990f70303fe6 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> @@ -51,6 +51,7 @@ l2: l2-cache {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  	};
>  
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> index 3db427122f9e..a7b8e001cc9c 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  
>  		l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  	};
>  };
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> index 68782f161f12..7740098fd108 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  
>  		l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
>  			cache-size = <0x80000>;
>  			cache-line-size = <64>;
>  			cache-sets = <512>;
> +			cache-level = <2>;
>  		};
>  	};
>  };
> -- 
> 2.25.1
>

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com

  parent reply	other threads:[~2022-11-28  0:10 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-31  9:20 [PATCH 10/20] arm64: dts: Update cache properties for marvell Pierre Gondois
2022-10-31  9:20 ` Pierre Gondois
2022-10-31 20:12 ` Chris Packham
2022-10-31 20:12   ` Chris Packham
2022-11-02 20:47 ` Krzysztof Kozlowski
2022-11-02 20:47   ` Krzysztof Kozlowski
2022-11-28  0:09 ` Gregory CLEMENT [this message]
2022-11-28  0:09   ` Gregory CLEMENT

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