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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Pranith Kumar <bobby.prani@gmail.com>
Cc: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org,
	fred.konrad@greensocs.com, a.rigo@virtualopensystems.com,
	cota@braap.org, nikunj@linux.vnet.ibm.com,
	mark.burton@greensocs.com, pbonzini@redhat.com,
	jan.kiszka@siemens.com, serge.fdrv@gmail.com, rth@twiddle.net,
	peter.maydell@linaro.org, claudio.fontana@huawei.com,
	bamvor.zhangjian@linaro.org,
	"open list\:ARM" <qemu-arm@nongnu.org>
Subject: Re: [PATCH v7 26/27] tcg: enable MTTCG by default for ARM on x86 hosts
Date: Fri, 20 Jan 2017 10:53:35 +0000	[thread overview]
Message-ID: <87r33ydmts.fsf@linaro.org> (raw)
In-Reply-To: <87a8amr3sj.fsf@gmail.com>


Pranith Kumar <bobby.prani@gmail.com> writes:

> Alex Bennée writes:
>
>> This enables the multi-threaded system emulation by default for ARMv7
>> and ARMv8 guests using the x86_64 TCG backend. This is because on the
>> guest side:
>>
>>   - The ARM translate.c/translate-64.c have been converted to
>>     - use MTTCG safe atomic primitives
>>     - emit the appropriate barrier ops
>>   - The ARM machine has been updated to
>>     - hold the BQL when modifying shared cross-vCPU state
>>     - defer cpu_reset to async safe work
>>
>> All the host backends support the barrier and atomic primitives but
>> need to provide same-or-better support for normal load/store
>> operations.
>>
>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>
> <snip>
>
>>
>> +/* This defines the natural memory order supported by this
>> + * architecture before guarantees made by various barrier
>> + * instructions.
>> + *
>> + * The x86 has a pretty strong memory ordering which only really
>> + * allows for some stores to be re-ordered after loads.
>> + */
>> +#include "tcg-mo.h"
>> +
>> +static inline int get_tcg_target_mo(void)
>> +{
>> +    return TCG_MO_ALL & ~TCG_MO_LD_ST;
>> +}
>> +
>
> Shouldn't this be TCG_MO_ALL & ~TCG_MO_ST_LD?

The case that x86 doesn't handle normally is store-after-load which is
what I assumed TCG_MO_LD_ST was. Perhaps we need some better comments
for each of the enums?

>
> Thanks,


--
Alex Bennée

WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org>
To: Pranith Kumar <bobby.prani@gmail.com>
Cc: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org,
	fred.konrad@greensocs.com, a.rigo@virtualopensystems.com,
	cota@braap.org, nikunj@linux.vnet.ibm.com,
	mark.burton@greensocs.com, pbonzini@redhat.com,
	jan.kiszka@siemens.com, serge.fdrv@gmail.com, rth@twiddle.net,
	peter.maydell@linaro.org, claudio.fontana@huawei.com,
	bamvor.zhangjian@linaro.org,
	"open list:ARM" <qemu-arm@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v7 26/27] tcg: enable MTTCG by default for ARM on x86 hosts
Date: Fri, 20 Jan 2017 10:53:35 +0000	[thread overview]
Message-ID: <87r33ydmts.fsf@linaro.org> (raw)
In-Reply-To: <87a8amr3sj.fsf@gmail.com>


Pranith Kumar <bobby.prani@gmail.com> writes:

> Alex Bennée writes:
>
>> This enables the multi-threaded system emulation by default for ARMv7
>> and ARMv8 guests using the x86_64 TCG backend. This is because on the
>> guest side:
>>
>>   - The ARM translate.c/translate-64.c have been converted to
>>     - use MTTCG safe atomic primitives
>>     - emit the appropriate barrier ops
>>   - The ARM machine has been updated to
>>     - hold the BQL when modifying shared cross-vCPU state
>>     - defer cpu_reset to async safe work
>>
>> All the host backends support the barrier and atomic primitives but
>> need to provide same-or-better support for normal load/store
>> operations.
>>
>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>
> <snip>
>
>>
>> +/* This defines the natural memory order supported by this
>> + * architecture before guarantees made by various barrier
>> + * instructions.
>> + *
>> + * The x86 has a pretty strong memory ordering which only really
>> + * allows for some stores to be re-ordered after loads.
>> + */
>> +#include "tcg-mo.h"
>> +
>> +static inline int get_tcg_target_mo(void)
>> +{
>> +    return TCG_MO_ALL & ~TCG_MO_LD_ST;
>> +}
>> +
>
> Shouldn't this be TCG_MO_ALL & ~TCG_MO_ST_LD?

The case that x86 doesn't handle normally is store-after-load which is
what I assumed TCG_MO_LD_ST was. Perhaps we need some better comments
for each of the enums?

>
> Thanks,


--
Alex Bennée

  reply	other threads:[~2017-01-20 10:53 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-19 17:04 [Qemu-devel] [PATCH v7 00/27] Remaining MTTCG Base patches and ARM enablement Alex Bennée
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 01/27] docs: new design document multi-thread-tcg.txt Alex Bennée
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 02/27] mttcg: translate-all: Enable locking debug in a debug build Alex Bennée
2017-01-23 18:57   ` Richard Henderson
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 03/27] mttcg: Add missing tb_lock/unlock() in cpu_exec_step() Alex Bennée
2017-01-23 18:57   ` Richard Henderson
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 04/27] tcg: move TCG_MO/BAR types into own file Alex Bennée
2017-01-23 18:59   ` Richard Henderson
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 05/27] tcg: add options for enabling MTTCG Alex Bennée
2017-01-20  1:28   ` Pranith Kumar
2017-01-20 14:50     ` Alex Bennée
2017-01-20 15:03       ` Pranith Kumar
2017-01-23 19:06   ` Richard Henderson
2017-01-24 20:25     ` Alex Bennée
2017-01-24 20:48       ` Richard Henderson
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 06/27] tcg: add kick timer for single-threaded vCPU emulation Alex Bennée
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 07/27] tcg: rename tcg_current_cpu to tcg_current_rr_cpu Alex Bennée
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 08/27] tcg: drop global lock during TCG code execution Alex Bennée
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 09/27] tcg: remove global exit_request Alex Bennée
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 10/27] tcg: enable tb_lock() for SoftMMU Alex Bennée
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 11/27] tcg: enable thread-per-vCPU Alex Bennée
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 12/27] tcg: handle EXCP_ATOMIC exception for system emulation Alex Bennée
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 13/27] cputlb: add assert_cpu_is_self checks Alex Bennée
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 14/27] cputlb: tweak qemu_ram_addr_from_host_nofail reporting Alex Bennée
2017-01-23 19:07   ` Richard Henderson
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 15/27] cputlb: introduce tlb_flush_* async work Alex Bennée
2017-01-23 19:10   ` Richard Henderson
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 16/27] cputlb: add tlb_flush_by_mmuidx async routines Alex Bennée
2017-01-23 19:11   ` Richard Henderson
2017-01-24 20:31     ` Alex Bennée
2017-01-24 20:44       ` Richard Henderson
2017-01-25 14:09         ` Alex Bennée
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 17/27] cputlb: atomically update tlb fields used by tlb_reset_dirty Alex Bennée
2017-01-23 19:17   ` Richard Henderson
2017-01-19 17:04 ` [Qemu-devel] [PATCH v7 18/27] cputlb: introduce tlb_flush_*_all_cpus Alex Bennée
2017-01-23 19:21   ` Richard Henderson
2017-01-24 20:34     ` Alex Bennée
2017-01-24 20:47       ` Richard Henderson
2017-01-25 14:21         ` Alex Bennée
2017-01-19 17:04 ` [PATCH v7 19/27] target-arm/powerctl: defer cpu reset work to CPU context Alex Bennée
2017-01-19 17:04   ` [Qemu-devel] " Alex Bennée
2017-01-19 17:05 ` [PATCH v7 20/27] target-arm: ensure BQL taken for ARM_CP_IO register access Alex Bennée
2017-01-19 17:05   ` [Qemu-devel] " Alex Bennée
2017-01-19 17:05 ` [PATCH v7 21/27] target-arm: helpers which may affect global state need the BQL Alex Bennée
2017-01-19 17:05   ` [Qemu-devel] " Alex Bennée
2017-01-19 17:05 ` [PATCH v7 22/27] target-arm: don't generate WFE/YIELD calls for MTTCG Alex Bennée
2017-01-19 17:05   ` [Qemu-devel] " Alex Bennée
2017-01-19 17:05 ` [PATCH v7 23/27] target-arm/cpu.h: make ARM_CP defined consistent Alex Bennée
2017-01-19 17:05   ` [Qemu-devel] " Alex Bennée
2017-01-19 17:05 ` [PATCH v7 24/27] target-arm: introduce ARM_CP_EXIT_PC Alex Bennée
2017-01-19 17:05   ` [Qemu-devel] " Alex Bennée
2017-01-19 17:05 ` [PATCH v7 25/27] target-arm: ensure all cross vCPUs TLB flushes complete Alex Bennée
2017-01-19 17:05   ` [Qemu-devel] " Alex Bennée
2017-01-19 17:05 ` [PATCH v7 26/27] tcg: enable MTTCG by default for ARM on x86 hosts Alex Bennée
2017-01-19 17:05   ` [Qemu-devel] " Alex Bennée
2017-01-20  0:08   ` Pranith Kumar
2017-01-20  0:08     ` [Qemu-devel] " Pranith Kumar
2017-01-20 10:53     ` Alex Bennée [this message]
2017-01-20 10:53       ` Alex Bennée
2017-01-20 14:30       ` Pranith Kumar
2017-01-20 14:30         ` [Qemu-devel] " Pranith Kumar
2017-01-19 17:05 ` [Qemu-devel] [PATCH v7 27/27] target-ppc: take global mutex for set_irq Alex Bennée

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