[PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor

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* [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor
@ 2011-05-15 21:45 ` Vladimir Zapolskiy
  0 siblings, 0 replies; 16+ messages in thread
From: Vladimir Zapolskiy @ 2011-05-15 21:45 UTC (permalink / raw)
  To: Tony Lindgren, Benoit Cousson
  Cc: linux-omap, linux-arm-kernel, Vladimir Zapolskiy

This change shows a possibility to utilize C preprocessor to remove
redundant data from clock definitions for OMAP4 architecture.

If the change is evaluated as a positive one, the same approach could
be applied in reducing LOCs from other files, which contain monotonous
data enumeration.

Vladimir Zapolskiy (2):
  OMAP4: clock data: shrink clock data utilizing preprocessor.
  OMAP4: clock data: shrink more clock data.

 arch/arm/mach-omap2/clock44xx_data.c | 3313 +++++++++-------------------------
 1 files changed, 848 insertions(+), 2465 deletions(-)

-- 
1.7.2.3

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor
@ 2011-05-15 21:45 ` Vladimir Zapolskiy
  0 siblings, 0 replies; 16+ messages in thread
From: Vladimir Zapolskiy @ 2011-05-15 21:45 UTC (permalink / raw)
  To: linux-arm-kernel

This change shows a possibility to utilize C preprocessor to remove
redundant data from clock definitions for OMAP4 architecture.

If the change is evaluated as a positive one, the same approach could
be applied in reducing LOCs from other files, which contain monotonous
data enumeration.

Vladimir Zapolskiy (2):
  OMAP4: clock data: shrink clock data utilizing preprocessor.
  OMAP4: clock data: shrink more clock data.

 arch/arm/mach-omap2/clock44xx_data.c | 3313 +++++++++-------------------------
 1 files changed, 848 insertions(+), 2465 deletions(-)

-- 
1.7.2.3

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCHv2 1/2] [RFC] OMAP4: clock data: shrink clock data utilizing preprocessor.
  2011-05-15 21:45 ` Vladimir Zapolskiy
@ 2011-05-15 21:45   ` Vladimir Zapolskiy
  -1 siblings, 0 replies; 16+ messages in thread
From: Vladimir Zapolskiy @ 2011-05-15 21:45 UTC (permalink / raw)
  To: Tony Lindgren, Benoit Cousson
  Cc: linux-omap, linux-arm-kernel, Vladimir Zapolskiy

This mass change reduces homogeneous data chunks along clock
definitions. No semantical difference is added in the change.

Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com>
---
 arch/arm/mach-omap2/clock44xx_data.c | 1638 ++++++++++------------------------
 1 files changed, 470 insertions(+), 1168 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 8c96567..423f180 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -7,6 +7,7 @@
  * Paul Walmsley (paul@pwsan.com)
  * Rajendra Nayak (rnayak@ti.com)
  * Benoit Cousson (b-cousson@ti.com)
+ * Vladimir Zapolskiy (vzapolskiy@gmail.com)
  *
  * This file is automatically generated from the OMAP hardware databases.
  * We respectfully ask that any modifications to this file be coordinated
@@ -42,129 +43,218 @@
 #define OMAP4430_MODULEMODE_HWCTRL			0
 #define OMAP4430_MODULEMODE_SWCTRL			1
 
-/* Root clocks */
-
-static struct clk extalt_clkin_ck = {
-	.name		= "extalt_clkin_ck",
-	.rate		= 59000000,
-	.ops		= &clkops_null,
-};
-
-static struct clk pad_clks_ck = {
-	.name		= "pad_clks_ck",
-	.rate		= 12000000,
-	.ops            = &clkops_omap2_dflt,
-	.enable_reg     = OMAP4430_CM_CLKSEL_ABE,
-	.enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
-};
-
-static struct clk pad_slimbus_core_clks_ck = {
-	.name		= "pad_slimbus_core_clks_ck",
-	.rate		= 12000000,
-	.ops		= &clkops_null,
-};
-
-static struct clk secure_32k_clk_src_ck = {
-	.name		= "secure_32k_clk_src_ck",
-	.rate		= 32768,
-	.ops		= &clkops_null,
-};
-
-static struct clk slimbus_clk = {
-	.name		= "slimbus_clk",
-	.rate		= 12000000,
-	.ops            = &clkops_omap2_dflt,
-	.enable_reg     = OMAP4430_CM_CLKSEL_ABE,
-	.enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
-};
-
-static struct clk sys_32k_ck = {
-	.name		= "sys_32k_ck",
-	.rate		= 32768,
-	.ops		= &clkops_null,
-};
-
-static struct clk virt_12000000_ck = {
-	.name		= "virt_12000000_ck",
-	.ops		= &clkops_null,
-	.rate		= 12000000,
-};
-
-static struct clk virt_13000000_ck = {
-	.name		= "virt_13000000_ck",
-	.ops		= &clkops_null,
-	.rate		= 13000000,
-};
-
-static struct clk virt_16800000_ck = {
-	.name		= "virt_16800000_ck",
-	.ops		= &clkops_null,
-	.rate		= 16800000,
-};
-
-static struct clk virt_19200000_ck = {
-	.name		= "virt_19200000_ck",
-	.ops		= &clkops_null,
-	.rate		= 19200000,
-};
-
-static struct clk virt_26000000_ck = {
-	.name		= "virt_26000000_ck",
-	.ops		= &clkops_null,
-	.rate		= 26000000,
-};
+#define CLOCK_FLAGS_ENABLE(...)						\
+	.flags		= ENABLE_ON_INIT,				\
+	##__VA_ARGS__
+
+#define CLOCK_OPS(_ops, ...)						\
+	.ops		= &_ops,					\
+	##__VA_ARGS__
+
+#define CLOCK_OPS_NULL(...)						\
+	CLOCK_OPS(clkops_null, ##__VA_ARGS__)
+
+#define CLOCK_OPS_DPLL(...)						\
+	CLOCK_OPS(clkops_omap4_dpllmx_ops, ##__VA_ARGS__)
+
+#define CLOCK_OPS_DFLT0(_reg, _bit, ...)				\
+	.ops		= &clkops_omap2_dflt,				\
+	.enable_reg	= OMAP4430_##_reg,				\
+	.enable_bit	= OMAP4430_##_bit##_SHIFT,			\
+	##__VA_ARGS__
+
+#define CLOCK_OPS_DFLT(_reg, _bit, ...)					\
+	.ops		= &clkops_omap2_dflt,				\
+	.enable_reg	= OMAP4430_##_reg##_CLKCTRL,			\
+	.enable_bit	= OMAP4430_##_bit##_SHIFT,			\
+	##__VA_ARGS__
+
+#define CLOCK_OPS_DFLT_SW(_reg, ...)					\
+	.ops		= &clkops_omap2_dflt,				\
+	.enable_reg	= OMAP4430_##_reg##_CLKCTRL,			\
+	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,			\
+	##__VA_ARGS__
+
+#define CLOCK_OPS_DFLT_HW(_reg, ...)					\
+	.ops		= &clkops_omap2_dflt,				\
+	.enable_reg	= OMAP4430_##_reg##_CLKCTRL,			\
+	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,			\
+	##__VA_ARGS__
+
+#define CLOCK_OPS_DFLT2(_reg, ...)					\
+	.ops		= &clkops_omap2_dflt,				\
+	.enable_reg	= OMAP4_##_reg,					\
+	.enable_bit	= OMAP4_ENABLE_SHIFT,				\
+	##__VA_ARGS__
+
+#define CLOCK_RECALC(_recalc, ...)					\
+	.recalc		= &_recalc,					\
+	##__VA_ARGS__
+
+#define CLOCK_RECALC_FOLLOWPARENT(...)					\
+	CLOCK_RECALC(followparent_recalc, ##__VA_ARGS__)
+
+#define CLOCK_RECALC_CLKSEL(...)					\
+	CLOCK_RECALC(omap2_clksel_recalc, ##__VA_ARGS__)
+
+#define CLOCK_RECALC_CLKOUTX2(...)					\
+	.flags		= CLOCK_CLKOUTX2,				\
+	CLOCK_RECALC(omap3_clkoutx2_recalc, ##__VA_ARGS__)
+
+#define CLOCK_RECALC_RATE(_recalc, _round_rate, _set_rate, ...)		\
+	.recalc		= &_recalc,					\
+	.round_rate	= &_round_rate,					\
+	.set_rate	= &_set_rate,					\
+	##__VA_ARGS__
+
+#define CLOCK_RECALC_FIXED(_div, ...)					\
+	.recalc		= &omap_fixed_divisor_recalc,			\
+	.fixed_div	= _div,						\
+	CLOCK_OPS_NULL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_RECALC_RATE_CLKSEL(...)					\
+	CLOCK_RECALC_RATE(omap2_clksel_recalc,				\
+			  omap2_clksel_round_rate,			\
+			  omap2_clksel_set_rate, ##__VA_ARGS__)
+
+#define CLOCK_RECALC_RATE_DPLL(_dpll_data, ...)				\
+	.init		= &omap2_init_dpll_parent,			\
+	.dpll_data	= &_dpll_data,					\
+	CLOCK_RECALC_RATE(omap3_dpll_recalc,				\
+			  omap2_dpll_round_rate,			\
+			  omap3_noncore_dpll_set_rate),			\
+	CLOCK_OPS(clkops_omap3_noncore_dpll_ops),			\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL_DPLL(_reg, ...)					\
+	.clksel_reg	= OMAP4430_##_reg,				\
+	CLOCK_OPS_DPLL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL_INIT(_sel, _reg, _mask, ...)			\
+	.init		= &omap2_init_clksel_parent,			\
+	.clksel		= _sel,						\
+	.clksel_reg	= OMAP4430_##_reg,				\
+	.clksel_mask	= OMAP4430_##_mask##_MASK,			\
+	CLOCK_OPS_NULL(),						\
+	CLOCK_RECALC_CLKSEL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL_INIT_SW(_sel, _reg, _mask, ...)			\
+	.init		= &omap2_init_clksel_parent,			\
+	.clksel		= _sel,						\
+	.clksel_reg	= OMAP4430_##_reg##_CLKCTRL,			\
+	.clksel_mask	= OMAP4430_##_mask##_MASK,			\
+	CLOCK_OPS_DFLT_SW(_reg),					\
+	CLOCK_RECALC_CLKSEL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL_INIT2(_sel, _reg, _mask, ...)			\
+	.init		= &omap2_init_clksel_parent,			\
+	.clksel		= _sel,						\
+	.clksel_reg	= OMAP4_##_reg,					\
+	.clksel_mask	= OMAP4_##_mask##_MASK,				\
+	CLOCK_RECALC_CLKSEL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL0(_sel, _reg, _mask, ...)				\
+	.clksel		= _sel,						\
+	.clksel_reg	= OMAP4430_##_reg,				\
+	.clksel_mask	= OMAP4430_##_mask##_MASK,			\
+	CLOCK_RECALC_CLKSEL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL(_sel, _reg, _mask, ...)				\
+	.clksel		= _sel,						\
+	.clksel_reg	= OMAP4430_##_reg,				\
+	.clksel_mask	= OMAP4430_##_mask##_MASK,			\
+	CLOCK_RECALC_RATE_CLKSEL(),					\
+	##__VA_ARGS__
+
+#define DEFINE_ROOT_CLOCK(_name, _rate, ...)				\
+	static struct clk _name = {					\
+		.name		= #_name,				\
+		.rate		= _rate,				\
+		##__VA_ARGS__						\
+	}
 
-static struct clk virt_27000000_ck = {
-	.name		= "virt_27000000_ck",
-	.ops		= &clkops_null,
-	.rate		= 27000000,
-};
+#define DEFINE_CLOCK(_name, _parent, ...)				\
+	static struct clk _name = {					\
+		.name		= #_name,				\
+		.parent		= &_parent,				\
+		##__VA_ARGS__						\
+	}
 
-static struct clk virt_38400000_ck = {
-	.name		= "virt_38400000_ck",
-	.ops		= &clkops_null,
-	.rate		= 38400000,
-};
+#define DEFINE_CLOCK_DM(_name, _parent, _clkdm, ...)			\
+	DEFINE_CLOCK(_name, _parent,					\
+		     .clkdm_name	= #_clkdm, ##__VA_ARGS__)
 
-static const struct clksel_rate div_1_0_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+#define DEFINE_CLKSEL(_name, _parent, _rates)				\
+	static const struct clksel _name[] = {				\
+		{ .parent = &_parent, .rates = _rates },		\
+		{ .parent = NULL },					\
+	}
 
-static const struct clksel_rate div_1_1_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+#define DEFINE_CLKSEL2(_name, _parent0, _parent1)			\
+	static const struct clksel _name[] = {				\
+		{ .parent = &_parent0, .rates = div_1_0_rates },	\
+		{ .parent = &_parent1, .rates = div_1_1_rates },	\
+		{ .parent = NULL },					\
+	}
 
-static const struct clksel_rate div_1_2_rates[] = {
-	{ .div = 1, .val = 2, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+#define DEFINE_CLKSEL3(_name, _parent0, _parent1, _parent2)		\
+	static const struct clksel _name[] = {				\
+		{ .parent = &_parent0, .rates = div_1_0_rates },	\
+		{ .parent = &_parent1, .rates = div_1_1_rates },	\
+		{ .parent = &_parent2, .rates = div_1_2_rates },	\
+		{ .parent = NULL },					\
+	}
 
-static const struct clksel_rate div_1_3_rates[] = {
-	{ .div = 1, .val = 3, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+#define DEFINE_CLKSEL_RATE(n)						\
+	static const struct clksel_rate div_1_##n##_rates[] = {		\
+		{ .div = 1, .val = n, .flags = RATE_IN_4430 },		\
+		{ .div = 0 },						\
+	}
 
-static const struct clksel_rate div_1_4_rates[] = {
-	{ .div = 1, .val = 4, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+#define DEFINE_CLKSEL_RATE2(_range, _div0, _div1)			\
+	static const struct clksel_rate div2_##_range##_rates[] = {	\
+		{ .div = _div0, .val = 0, .flags = RATE_IN_4430 },	\
+		{ .div = _div1, .val = 1, .flags = RATE_IN_4430 },	\
+		{ .div = 0 },						\
+	}
 
-static const struct clksel_rate div_1_5_rates[] = {
-	{ .div = 1, .val = 5, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+/*
+#define DEFINE_DPLL_DATA(_name, )
+*/
 
-static const struct clksel_rate div_1_6_rates[] = {
-	{ .div = 1, .val = 6, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+/* Root clocks */
 
-static const struct clksel_rate div_1_7_rates[] = {
-	{ .div = 1, .val = 7, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_ROOT_CLOCK(extalt_clkin_ck,		59000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(pad_slimbus_core_clks_ck,	12000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(secure_32k_clk_src_ck,	32768,    CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(sys_32k_ck,			32768,    CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_12000000_ck,		12000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_13000000_ck,		13000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_16800000_ck,		16800000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_19200000_ck,		19200000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_26000000_ck,		26000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_27000000_ck,		27000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_38400000_ck,		38400000, CLOCK_OPS_NULL());
+
+DEFINE_ROOT_CLOCK(pad_clks_ck,			12000000,
+		  CLOCK_OPS_DFLT0(CM_CLKSEL_ABE, PAD_CLKS_GATE));
+DEFINE_ROOT_CLOCK(slimbus_clk,			12000000,
+		  CLOCK_OPS_DFLT0(CM_CLKSEL_ABE, SLIMBUS_CLK_GATE));
+
+DEFINE_CLKSEL_RATE(0);
+DEFINE_CLKSEL_RATE(1);
+DEFINE_CLKSEL_RATE(2);
+DEFINE_CLKSEL_RATE(3);
+DEFINE_CLKSEL_RATE(4);
+DEFINE_CLKSEL_RATE(5);
+DEFINE_CLKSEL_RATE(6);
+DEFINE_CLKSEL_RATE(7);
 
 static const struct clksel sys_clkin_sel[] = {
 	{ .parent = &virt_12000000_ck, .rates = div_1_1_rates },
@@ -177,72 +267,24 @@ static const struct clksel sys_clkin_sel[] = {
 	{ .parent = NULL },
 };
 
-static struct clk sys_clkin_ck = {
-	.name		= "sys_clkin_ck",
-	.rate		= 38400000,
-	.clksel		= sys_clkin_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_SYS_CLKSEL,
-	.clksel_mask	= OMAP4430_SYS_CLKSEL_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
-
-static struct clk tie_low_clock_ck = {
-	.name		= "tie_low_clock_ck",
-	.rate		= 0,
-	.ops		= &clkops_null,
-};
-
-static struct clk utmi_phy_clkout_ck = {
-	.name		= "utmi_phy_clkout_ck",
-	.rate		= 60000000,
-	.ops		= &clkops_null,
-};
-
-static struct clk xclk60mhsp1_ck = {
-	.name		= "xclk60mhsp1_ck",
-	.rate		= 60000000,
-	.ops		= &clkops_null,
-};
-
-static struct clk xclk60mhsp2_ck = {
-	.name		= "xclk60mhsp2_ck",
-	.rate		= 60000000,
-	.ops		= &clkops_null,
-};
+DEFINE_ROOT_CLOCK(sys_clkin_ck, 38400000,
+		  CLOCK_CLKSEL_INIT(sys_clkin_sel, CM_SYS_CLKSEL, SYS_CLKSEL));
 
-static struct clk xclk60motg_ck = {
-	.name		= "xclk60motg_ck",
-	.rate		= 60000000,
-	.ops		= &clkops_null,
-};
+DEFINE_ROOT_CLOCK(tie_low_clock_ck,   0,        CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(utmi_phy_clkout_ck, 60000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(xclk60mhsp1_ck,     60000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(xclk60mhsp2_ck,     60000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(xclk60motg_ck,      60000000, CLOCK_OPS_NULL());
 
 /* Module clocks and DPLL outputs */
 
-static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk abe_dpll_bypass_clk_mux_ck = {
-	.name		= "abe_dpll_bypass_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLKSEL2(abe_dpll_bypass_clk_mux_sel, sys_clkin_ck, sys_32k_ck);
 
-static struct clk abe_dpll_refclk_mux_ck = {
-	.name		= "abe_dpll_refclk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_ABE_PLL_REF_CLKSEL,
-	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(abe_dpll_bypass_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
+DEFINE_CLOCK(abe_dpll_refclk_mux_ck, sys_clkin_ck,
+	     CLOCK_CLKSEL_INIT(abe_dpll_bypass_clk_mux_sel,
+			       CM_ABE_PLL_REF_CLKSEL, CLKSEL_0_0));
 
 /* DPLL_ABE */
 static struct dpll_data dpll_abe_dd = {
@@ -263,26 +305,11 @@ static struct dpll_data dpll_abe_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_abe_ck, abe_dpll_refclk_mux_ck,
+	     CLOCK_RECALC_RATE_DPLL(dpll_abe_dd));
 
-static struct clk dpll_abe_ck = {
-	.name		= "dpll_abe_ck",
-	.parent		= &abe_dpll_refclk_mux_ck,
-	.dpll_data	= &dpll_abe_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk dpll_abe_x2_ck = {
-	.name		= "dpll_abe_x2_ck",
-	.parent		= &dpll_abe_ck,
-	.flags		= CLOCK_CLKOUTX2,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap3_clkoutx2_recalc,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
-};
+DEFINE_CLOCK(dpll_abe_x2_ck, dpll_abe_ck,
+	     CLOCK_CLKSEL_DPLL(CM_DIV_M2_DPLL_ABE), CLOCK_RECALC_CLKOUTX2());
 
 static const struct clksel_rate div31_1to31_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
@@ -319,30 +346,13 @@ static const struct clksel_rate div31_1to31_rates[] = {
 	{ .div = 0 },
 };
 
-static const struct clksel dpll_abe_m2x2_div[] = {
-	{ .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_abe_m2x2_div, dpll_abe_x2_ck, div31_1to31_rates);
 
-static struct clk dpll_abe_m2x2_ck = {
-	.name		= "dpll_abe_m2x2_ck",
-	.parent		= &dpll_abe_x2_ck,
-	.clksel		= dpll_abe_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_abe_m2x2_ck, dpll_abe_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_abe_m2x2_div,
+			  CM_DIV_M2_DPLL_ABE, DPLL_CLKOUT_DIV));
 
-static struct clk abe_24m_fclk = {
-	.name		= "abe_24m_fclk",
-	.parent		= &dpll_abe_m2x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 8,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(abe_24m_fclk, dpll_abe_m2x2_ck, CLOCK_RECALC_FIXED(8));
 
 static const struct clksel_rate div3_1to4_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
@@ -351,74 +361,28 @@ static const struct clksel_rate div3_1to4_rates[] = {
 	{ .div = 0 },
 };
 
-static const struct clksel abe_clk_div[] = {
-	{ .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(abe_clk_div, dpll_abe_m2x2_ck, div3_1to4_rates);
 
-static struct clk abe_clk = {
-	.name		= "abe_clk",
-	.parent		= &dpll_abe_m2x2_ck,
-	.clksel		= abe_clk_div,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_ABE,
-	.clksel_mask	= OMAP4430_CLKSEL_OPP_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(abe_clk, dpll_abe_m2x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(abe_clk_div, CM_CLKSEL_ABE, CLKSEL_OPP));
 
-static const struct clksel_rate div2_1to2_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_CLKSEL_RATE2(1to2, 1, 2);
 
-static const struct clksel aess_fclk_div[] = {
-	{ .parent = &abe_clk, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(aess_fclk_div, abe_clk, div2_1to2_rates);
 
-static struct clk aess_fclk = {
-	.name		= "aess_fclk",
-	.parent		= &abe_clk,
-	.clksel		= aess_fclk_div,
-	.clksel_reg	= OMAP4430_CM1_ABE_AESS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_AESS_FCLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(aess_fclk, abe_clk, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(aess_fclk_div,
+			  CM1_ABE_AESS_CLKCTRL, CLKSEL_AESS_FCLK));
 
-static struct clk dpll_abe_m3x2_ck = {
-	.name		= "dpll_abe_m3x2_ck",
-	.parent		= &dpll_abe_x2_ck,
-	.clksel		= dpll_abe_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M3_DPLL_ABE,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_abe_m3x2_ck, dpll_abe_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_abe_m2x2_div,
+			  CM_DIV_M3_DPLL_ABE, DPLL_CLKOUTHIF_DIV));
 
-static const struct clksel core_hsd_byp_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(core_hsd_byp_clk_mux_sel, sys_clkin_ck, dpll_abe_m3x2_ck);
 
-static struct clk core_hsd_byp_clk_mux_ck = {
-	.name		= "core_hsd_byp_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= core_hsd_byp_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_DPLL_CORE,
-	.clksel_mask	= OMAP4430_DPLL_BYP_CLKSEL_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(core_hsd_byp_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_CLKSEL_INIT(core_hsd_byp_clk_mux_sel,
+			       CM_CLKSEL_DPLL_CORE, DPLL_BYP_CLKSEL));
 
 /* DPLL_CORE */
 static struct dpll_data dpll_core_dd = {
@@ -439,107 +403,39 @@ static struct dpll_data dpll_core_dd = {
 	.min_divider	= 1,
 };
 
+/* originally round_rate/set_rate were NOT defined for dpll_core_ck */
+DEFINE_CLOCK(dpll_core_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_core_dd));
 
-static struct clk dpll_core_ck = {
-	.name		= "dpll_core_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_core_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_core_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-};
-
-static struct clk dpll_core_x2_ck = {
-	.name		= "dpll_core_x2_ck",
-	.parent		= &dpll_core_ck,
-	.flags		= CLOCK_CLKOUTX2,
-	.ops		= &clkops_null,
-	.recalc		= &omap3_clkoutx2_recalc,
-};
+DEFINE_CLOCK(dpll_core_x2_ck, dpll_core_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_CLKOUTX2());
 
-static const struct clksel dpll_core_m6x2_div[] = {
-	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_core_m6x2_div, dpll_core_x2_ck, div31_1to31_rates);
 
-static struct clk dpll_core_m6x2_ck = {
-	.name		= "dpll_core_m6x2_ck",
-	.parent		= &dpll_core_x2_ck,
-	.clksel		= dpll_core_m6x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M6_DPLL_CORE,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m6x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_core_m6x2_div,
+			  CM_DIV_M6_DPLL_CORE, HSDIVIDER_CLKOUT3_DIV));
 
-static const struct clksel dbgclk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(dbgclk_mux_sel, sys_clkin_ck, dpll_core_m6x2_ck);
 
-static struct clk dbgclk_mux_ck = {
-	.name		= "dbgclk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(dbgclk_mux_ck, sys_clkin_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static const struct clksel dpll_core_m2_div[] = {
-	{ .parent = &dpll_core_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_core_m2_div, dpll_core_ck, div31_1to31_rates);
 
-static struct clk dpll_core_m2_ck = {
-	.name		= "dpll_core_m2_ck",
-	.parent		= &dpll_core_ck,
-	.clksel		= dpll_core_m2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_CORE,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m2_ck, dpll_core_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_core_m2_div,
+			  CM_DIV_M2_DPLL_CORE, DPLL_CLKOUT_DIV));
 
-static struct clk ddrphy_ck = {
-	.name		= "ddrphy_ck",
-	.parent		= &dpll_core_m2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 2,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(ddrphy_ck, dpll_core_m2_ck, CLOCK_RECALC_FIXED(2));
 
-static struct clk dpll_core_m5x2_ck = {
-	.name		= "dpll_core_m5x2_ck",
-	.parent		= &dpll_core_x2_ck,
-	.clksel		= dpll_core_m6x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_CORE,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m5x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_core_m6x2_div,
+			  CM_DIV_M5_DPLL_CORE, HSDIVIDER_CLKOUT2_DIV));
 
-static const struct clksel div_core_div[] = {
-	{ .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(div_core_div, dpll_core_m5x2_ck, div2_1to2_rates);
 
-static struct clk div_core_ck = {
-	.name		= "div_core_ck",
-	.parent		= &dpll_core_m5x2_ck,
-	.clksel		= div_core_div,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
-	.clksel_mask	= OMAP4430_CLKSEL_CORE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(div_core_ck, dpll_core_m5x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(div_core_div, CM_CLKSEL_CORE, CLKSEL_CORE));
 
 static const struct clksel_rate div4_1to8_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
@@ -549,114 +445,40 @@ static const struct clksel_rate div4_1to8_rates[] = {
 	{ .div = 0 },
 };
 
-static const struct clksel div_iva_hs_clk_div[] = {
-	{ .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(div_iva_hs_clk_div, dpll_core_m5x2_ck, div4_1to8_rates);
 
-static struct clk div_iva_hs_clk = {
-	.name		= "div_iva_hs_clk",
-	.parent		= &dpll_core_m5x2_ck,
-	.clksel		= div_iva_hs_clk_div,
-	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_IVA,
-	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(div_iva_hs_clk, dpll_core_m5x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(div_iva_hs_clk_div, CM_BYPCLK_DPLL_IVA, CLKSEL_0_1));
 
-static struct clk div_mpu_hs_clk = {
-	.name		= "div_mpu_hs_clk",
-	.parent		= &dpll_core_m5x2_ck,
-	.clksel		= div_iva_hs_clk_div,
-	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_MPU,
-	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(div_mpu_hs_clk, dpll_core_m5x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(div_iva_hs_clk_div, CM_BYPCLK_DPLL_MPU, CLKSEL_0_1));
 
-static struct clk dpll_core_m4x2_ck = {
-	.name		= "dpll_core_m4x2_ck",
-	.parent		= &dpll_core_x2_ck,
-	.clksel		= dpll_core_m6x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_CORE,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m4x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_core_m6x2_div,
+			  CM_DIV_M4_DPLL_CORE, HSDIVIDER_CLKOUT1_DIV));
 
-static struct clk dll_clk_div_ck = {
-	.name		= "dll_clk_div_ck",
-	.parent		= &dpll_core_m4x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 2,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(dll_clk_div_ck, dpll_core_m4x2_ck, CLOCK_RECALC_FIXED(2));
 
-static const struct clksel dpll_abe_m2_div[] = {
-	{ .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_abe_m2_div, dpll_abe_ck, div31_1to31_rates);
 
-static struct clk dpll_abe_m2_ck = {
-	.name		= "dpll_abe_m2_ck",
-	.parent		= &dpll_abe_ck,
-	.clksel		= dpll_abe_m2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_abe_m2_ck, dpll_abe_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_abe_m2_div,
+			  CM_DIV_M2_DPLL_ABE, DPLL_CLKOUT_DIV));
 
-static struct clk dpll_core_m3x2_ck = {
-	.name		= "dpll_core_m3x2_ck",
-	.parent		= &dpll_core_x2_ck,
-	.clksel		= dpll_core_m6x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M3_DPLL_CORE,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DIV_M3_DPLL_CORE,
-	.enable_bit	= OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m3x2_ck, dpll_core_x2_ck,
+	     CLOCK_OPS_DFLT0(CM_DIV_M3_DPLL_CORE, DPLL_CLKOUTHIF_GATE_CTRL),
+	     CLOCK_CLKSEL(dpll_core_m6x2_div,
+			  CM_DIV_M3_DPLL_CORE, DPLL_CLKOUTHIF_DIV));
 
-static struct clk dpll_core_m7x2_ck = {
-	.name		= "dpll_core_m7x2_ck",
-	.parent		= &dpll_core_x2_ck,
-	.clksel		= dpll_core_m6x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M7_DPLL_CORE,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m7x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_core_m6x2_div,
+			  CM_DIV_M7_DPLL_CORE, HSDIVIDER_CLKOUT4_DIV));
 
-static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(iva_hsd_byp_clk_mux_sel, sys_clkin_ck, div_iva_hs_clk);
 
-static struct clk iva_hsd_byp_clk_mux_ck = {
-	.name		= "iva_hsd_byp_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= iva_hsd_byp_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_DPLL_IVA,
-	.clksel_mask	= OMAP4430_DPLL_BYP_CLKSEL_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(iva_hsd_byp_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_CLKSEL_INIT(iva_hsd_byp_clk_mux_sel,
+			       CM_CLKSEL_DPLL_IVA, DPLL_BYP_CLKSEL));
 
 /* DPLL_IVA */
 static struct dpll_data dpll_iva_dd = {
@@ -677,54 +499,21 @@ static struct dpll_data dpll_iva_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_iva_ck, sys_clkin_ck,
+	     CLOCK_RECALC_RATE_DPLL(dpll_iva_dd));
 
-static struct clk dpll_iva_ck = {
-	.name		= "dpll_iva_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_iva_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk dpll_iva_x2_ck = {
-	.name		= "dpll_iva_x2_ck",
-	.parent		= &dpll_iva_ck,
-	.flags		= CLOCK_CLKOUTX2,
-	.ops		= &clkops_null,
-	.recalc		= &omap3_clkoutx2_recalc,
-};
+DEFINE_CLOCK(dpll_iva_x2_ck, dpll_iva_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_CLKOUTX2());
 
-static const struct clksel dpll_iva_m4x2_div[] = {
-	{ .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_iva_m4x2_div, dpll_iva_x2_ck, div31_1to31_rates);
 
-static struct clk dpll_iva_m4x2_ck = {
-	.name		= "dpll_iva_m4x2_ck",
-	.parent		= &dpll_iva_x2_ck,
-	.clksel		= dpll_iva_m4x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_IVA,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_iva_m4x2_ck, dpll_iva_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_iva_m4x2_div,
+			  CM_DIV_M4_DPLL_IVA, HSDIVIDER_CLKOUT1_DIV));
 
-static struct clk dpll_iva_m5x2_ck = {
-	.name		= "dpll_iva_m5x2_ck",
-	.parent		= &dpll_iva_x2_ck,
-	.clksel		= dpll_iva_m4x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_IVA,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_iva_m5x2_ck, dpll_iva_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_iva_m4x2_div,
+			  CM_DIV_M5_DPLL_IVA, HSDIVIDER_CLKOUT2_DIV));
 
 /* DPLL_MPU */
 static struct dpll_data dpll_mpu_dd = {
@@ -745,59 +534,21 @@ static struct dpll_data dpll_mpu_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_mpu_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_mpu_dd));
 
-static struct clk dpll_mpu_ck = {
-	.name		= "dpll_mpu_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_mpu_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static const struct clksel dpll_mpu_m2_div[] = {
-	{ .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_mpu_m2_div, dpll_mpu_ck, div31_1to31_rates);
 
-static struct clk dpll_mpu_m2_ck = {
-	.name		= "dpll_mpu_m2_ck",
-	.parent		= &dpll_mpu_ck,
-	.clksel		= dpll_mpu_m2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_MPU,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_mpu_m2_ck, dpll_mpu_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_mpu_m2_div,
+			  CM_DIV_M2_DPLL_MPU, DPLL_CLKOUT_DIV));
 
-static struct clk per_hs_clk_div_ck = {
-	.name		= "per_hs_clk_div_ck",
-	.parent		= &dpll_abe_m3x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 2,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(per_hs_clk_div_ck, dpll_abe_m3x2_ck, CLOCK_RECALC_FIXED(2));
 
-static const struct clksel per_hsd_byp_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(per_hsd_byp_clk_mux_sel, sys_clkin_ck, per_hs_clk_div_ck);
 
-static struct clk per_hsd_byp_clk_mux_ck = {
-	.name		= "per_hsd_byp_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= per_hsd_byp_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_DPLL_PER,
-	.clksel_mask	= OMAP4430_DPLL_BYP_CLKSEL_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(per_hsd_byp_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_CLKSEL_INIT(per_hsd_byp_clk_mux_sel,
+			       CM_CLKSEL_DPLL_PER, DPLL_BYP_CLKSEL));
 
 /* DPLL_PER */
 static struct dpll_data dpll_per_dd = {
@@ -818,122 +569,43 @@ static struct dpll_data dpll_per_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_per_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_per_dd));
 
-static struct clk dpll_per_ck = {
-	.name		= "dpll_per_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_per_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
+DEFINE_CLKSEL(dpll_per_m2_div, dpll_per_ck, div31_1to31_rates);
 
-static const struct clksel dpll_per_m2_div[] = {
-	{ .parent = &dpll_per_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(dpll_per_m2_ck, dpll_per_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2_div,
+			  CM_DIV_M2_DPLL_PER, DPLL_CLKOUT_DIV));
 
-static struct clk dpll_per_m2_ck = {
-	.name		= "dpll_per_m2_ck",
-	.parent		= &dpll_per_ck,
-	.clksel		= dpll_per_m2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_x2_ck, dpll_per_ck,
+	     CLOCK_CLKSEL_DPLL(CM_DIV_M2_DPLL_PER), CLOCK_RECALC_CLKOUTX2());
 
-static struct clk dpll_per_x2_ck = {
-	.name		= "dpll_per_x2_ck",
-	.parent		= &dpll_per_ck,
-	.flags		= CLOCK_CLKOUTX2,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap3_clkoutx2_recalc,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
-};
+DEFINE_CLKSEL(dpll_per_m2x2_div, dpll_per_x2_ck, div31_1to31_rates);
 
-static const struct clksel dpll_per_m2x2_div[] = {
-	{ .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(dpll_per_m2x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M2_DPLL_PER, DPLL_CLKOUT_DIV));
 
-static struct clk dpll_per_m2x2_ck = {
-	.name		= "dpll_per_m2x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_m3x2_ck, dpll_per_x2_ck,
+	     CLOCK_OPS_DFLT0(CM_DIV_M3_DPLL_PER, DPLL_CLKOUTHIF_GATE_CTRL),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M3_DPLL_PER, DPLL_CLKOUTHIF_DIV));
 
-static struct clk dpll_per_m3x2_ck = {
-	.name		= "dpll_per_m3x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M3_DPLL_PER,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DIV_M3_DPLL_PER,
-	.enable_bit	= OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
-
-static struct clk dpll_per_m4x2_ck = {
-	.name		= "dpll_per_m4x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_PER,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_m4x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M4_DPLL_PER, HSDIVIDER_CLKOUT1_DIV));
 
-static struct clk dpll_per_m5x2_ck = {
-	.name		= "dpll_per_m5x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_PER,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_m5x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M5_DPLL_PER, HSDIVIDER_CLKOUT2_DIV));
 
-static struct clk dpll_per_m6x2_ck = {
-	.name		= "dpll_per_m6x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M6_DPLL_PER,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_m6x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M6_DPLL_PER, HSDIVIDER_CLKOUT3_DIV));
 
-static struct clk dpll_per_m7x2_ck = {
-	.name		= "dpll_per_m7x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M7_DPLL_PER,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_m7x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M7_DPLL_PER, HSDIVIDER_CLKOUT4_DIV));
 
 /* DPLL_UNIPRO */
 static struct dpll_data dpll_unipro_dd = {
@@ -955,50 +627,19 @@ static struct dpll_data dpll_unipro_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_unipro_ck, sys_clkin_ck,
+	     CLOCK_RECALC_RATE_DPLL(dpll_unipro_dd));
 
-static struct clk dpll_unipro_ck = {
-	.name		= "dpll_unipro_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_unipro_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk dpll_unipro_x2_ck = {
-	.name		= "dpll_unipro_x2_ck",
-	.parent		= &dpll_unipro_ck,
-	.flags		= CLOCK_CLKOUTX2,
-	.ops		= &clkops_null,
-	.recalc		= &omap3_clkoutx2_recalc,
-};
+DEFINE_CLOCK(dpll_unipro_x2_ck, dpll_unipro_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_CLKOUTX2());
 
-static const struct clksel dpll_unipro_m2x2_div[] = {
-	{ .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_unipro_m2x2_div, dpll_unipro_x2_ck, div31_1to31_rates);
 
-static struct clk dpll_unipro_m2x2_ck = {
-	.name		= "dpll_unipro_m2x2_ck",
-	.parent		= &dpll_unipro_x2_ck,
-	.clksel		= dpll_unipro_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_unipro_m2x2_ck, dpll_unipro_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_unipro_m2x2_div,
+			  CM_DIV_M2_DPLL_UNIPRO, DPLL_CLKOUT_DIV));
 
-static struct clk usb_hs_clk_div_ck = {
-	.name		= "usb_hs_clk_div_ck",
-	.parent		= &dpll_abe_m3x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 3,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(usb_hs_clk_div_ck, dpll_abe_m3x2_ck, CLOCK_RECALC_FIXED(3));
 
 /* DPLL_USB */
 static struct dpll_data dpll_usb_dd = {
@@ -1020,528 +661,189 @@ static struct dpll_data dpll_usb_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_usb_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_usb_dd));
 
-static struct clk dpll_usb_ck = {
-	.name		= "dpll_usb_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_usb_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
+DEFINE_CLOCK(dpll_usb_clkdcoldo_ck, dpll_usb_ck,
+	     CLOCK_CLKSEL_DPLL(CM_CLKDCOLDO_DPLL_USB),
+	     CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk dpll_usb_clkdcoldo_ck = {
-	.name		= "dpll_usb_clkdcoldo_ck",
-	.parent		= &dpll_usb_ck,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.clksel_reg	= OMAP4430_CM_CLKDCOLDO_DPLL_USB,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLKSEL(dpll_usb_m2_div, dpll_usb_ck, div31_1to31_rates);
 
-static const struct clksel dpll_usb_m2_div[] = {
-	{ .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(dpll_usb_m2_ck, dpll_usb_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_usb_m2_div,
+			  CM_DIV_M2_DPLL_USB, DPLL_CLKOUT_DIV_0_6));
 
-static struct clk dpll_usb_m2_ck = {
-	.name		= "dpll_usb_m2_ck",
-	.parent		= &dpll_usb_ck,
-	.clksel		= dpll_usb_m2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_USB,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLKSEL2(ducati_clk_mux_sel, div_core_ck, dpll_per_m6x2_ck);
 
-static const struct clksel ducati_clk_mux_sel[] = {
-	{ .parent = &div_core_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(ducati_clk_mux_ck, div_core_ck,
+	     CLOCK_CLKSEL_INIT(ducati_clk_mux_sel,
+			       CM_CLKSEL_DUCATI_ISS_ROOT, CLKSEL_0_0));
 
-static struct clk ducati_clk_mux_ck = {
-	.name		= "ducati_clk_mux_ck",
-	.parent		= &div_core_ck,
-	.clksel		= ducati_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
-	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(func_12m_fclk, dpll_per_m2x2_ck, CLOCK_RECALC_FIXED(16));
 
-static struct clk func_12m_fclk = {
-	.name		= "func_12m_fclk",
-	.parent		= &dpll_per_m2x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 16,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(func_24m_clk, dpll_per_m2_ck, CLOCK_RECALC_FIXED(4));
 
-static struct clk func_24m_clk = {
-	.name		= "func_24m_clk",
-	.parent		= &dpll_per_m2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 4,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(func_24mc_fclk, dpll_per_m2x2_ck, CLOCK_RECALC_FIXED(8));
 
-static struct clk func_24mc_fclk = {
-	.name		= "func_24mc_fclk",
-	.parent		= &dpll_per_m2x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 8,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLKSEL_RATE2(4to8, 4, 8);
 
-static const struct clksel_rate div2_4to8_rates[] = {
-	{ .div = 4, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 8, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_CLKSEL(func_48m_fclk_div, dpll_per_m2x2_ck, div2_4to8_rates);
 
-static const struct clksel func_48m_fclk_div[] = {
-	{ .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(func_48m_fclk, dpll_per_m2x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(func_48m_fclk_div, CM_SCALE_FCLK, SCALE_FCLK));
 
-static struct clk func_48m_fclk = {
-	.name		= "func_48m_fclk",
-	.parent		= &dpll_per_m2x2_ck,
-	.clksel		= func_48m_fclk_div,
-	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
-	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(func_48mc_fclk, dpll_per_m2x2_ck, CLOCK_RECALC_FIXED(4));
 
-static struct clk func_48mc_fclk = {
-	.name		= "func_48mc_fclk",
-	.parent		= &dpll_per_m2x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 4,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLKSEL_RATE2(2to4, 2, 4);
 
-static const struct clksel_rate div2_2to4_rates[] = {
-	{ .div = 2, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 4, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_CLKSEL(func_64m_fclk_div, dpll_per_m4x2_ck, div2_2to4_rates);
 
-static const struct clksel func_64m_fclk_div[] = {
-	{ .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(func_64m_fclk, dpll_per_m4x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(func_64m_fclk_div, CM_SCALE_FCLK, SCALE_FCLK));
 
-static struct clk func_64m_fclk = {
-	.name		= "func_64m_fclk",
-	.parent		= &dpll_per_m4x2_ck,
-	.clksel		= func_64m_fclk_div,
-	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
-	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
-
-static const struct clksel func_96m_fclk_div[] = {
-	{ .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(func_96m_fclk_div, dpll_per_m2x2_ck, div2_2to4_rates);
 
-static struct clk func_96m_fclk = {
-	.name		= "func_96m_fclk",
-	.parent		= &dpll_per_m2x2_ck,
-	.clksel		= func_96m_fclk_div,
-	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
-	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(func_96m_fclk, dpll_per_m2x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(func_96m_fclk_div, CM_SCALE_FCLK, SCALE_FCLK));
 
-static const struct clksel hsmmc6_fclk_sel[] = {
-	{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
-	{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(hsmmc6_fclk_sel, func_64m_fclk, func_96m_fclk);
 
-static struct clk hsmmc6_fclk = {
-	.name		= "hsmmc6_fclk",
-	.parent		= &func_64m_fclk,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(hsmmc6_fclk, func_64m_fclk,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static const struct clksel_rate div2_1to8_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 8, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_CLKSEL_RATE2(1to8, 1, 8);
 
-static const struct clksel init_60m_fclk_div[] = {
-	{ .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(init_60m_fclk_div, dpll_usb_m2_ck, div2_1to8_rates);
 
-static struct clk init_60m_fclk = {
-	.name		= "init_60m_fclk",
-	.parent		= &dpll_usb_m2_ck,
-	.clksel		= init_60m_fclk_div,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_USB_60MHZ,
-	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(init_60m_fclk, dpll_usb_m2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(init_60m_fclk_div, CM_CLKSEL_USB_60MHZ, CLKSEL_0_0));
 
-static const struct clksel l3_div_div[] = {
-	{ .parent = &div_core_ck, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(l3_div_div, div_core_ck, div2_1to2_rates);
 
-static struct clk l3_div_ck = {
-	.name		= "l3_div_ck",
-	.parent		= &div_core_ck,
-	.clksel		= l3_div_div,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
-	.clksel_mask	= OMAP4430_CLKSEL_L3_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(l3_div_ck, div_core_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(l3_div_div, CM_CLKSEL_CORE, CLKSEL_L3));
 
-static const struct clksel l4_div_div[] = {
-	{ .parent = &l3_div_ck, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(l4_div_div, l3_div_ck, div2_1to2_rates);
 
-static struct clk l4_div_ck = {
-	.name		= "l4_div_ck",
-	.parent		= &l3_div_ck,
-	.clksel		= l4_div_div,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
-	.clksel_mask	= OMAP4430_CLKSEL_L4_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(l4_div_ck, l3_div_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(l4_div_div, CM_CLKSEL_CORE, CLKSEL_L4));
 
-static struct clk lp_clk_div_ck = {
-	.name		= "lp_clk_div_ck",
-	.parent		= &dpll_abe_m2x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 16,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(lp_clk_div_ck, dpll_abe_m2x2_ck, CLOCK_RECALC_FIXED(16));
 
-static const struct clksel l4_wkup_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(l4_wkup_clk_mux_sel, sys_clkin_ck, lp_clk_div_ck);
 
-static struct clk l4_wkup_clk_mux_ck = {
-	.name		= "l4_wkup_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= l4_wkup_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4_WKUP_CLKSEL,
-	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(l4_wkup_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_CLKSEL_INIT(l4_wkup_clk_mux_sel,
+			       CM_L4_WKUP_CLKSEL, CLKSEL_0_0));
 
-static const struct clksel per_abe_nc_fclk_div[] = {
-	{ .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(per_abe_nc_fclk_div, dpll_abe_m2_ck, div2_1to2_rates);
 
-static struct clk per_abe_nc_fclk = {
-	.name		= "per_abe_nc_fclk",
-	.parent		= &dpll_abe_m2_ck,
-	.clksel		= per_abe_nc_fclk_div,
-	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
-	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(per_abe_nc_fclk, dpll_abe_m2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(per_abe_nc_fclk_div, CM_SCALE_FCLK, SCALE_FCLK));
 
-static const struct clksel mcasp2_fclk_sel[] = {
-	{ .parent = &func_96m_fclk, .rates = div_1_0_rates },
-	{ .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(mcasp2_fclk_sel, func_96m_fclk, per_abe_nc_fclk);
 
-static struct clk mcasp2_fclk = {
-	.name		= "mcasp2_fclk",
-	.parent		= &func_96m_fclk,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(mcasp2_fclk, func_96m_fclk,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk mcasp3_fclk = {
-	.name		= "mcasp3_fclk",
-	.parent		= &func_96m_fclk,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(mcasp3_fclk, func_96m_fclk,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk ocp_abe_iclk = {
-	.name		= "ocp_abe_iclk",
-	.parent		= &aess_fclk,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(ocp_abe_iclk, aess_fclk,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk per_abe_24m_fclk = {
-	.name		= "per_abe_24m_fclk",
-	.parent		= &dpll_abe_m2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 4,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(per_abe_24m_fclk, dpll_abe_m2_ck, CLOCK_RECALC_FIXED(4));
 
-static const struct clksel pmd_stm_clock_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
-	{ .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(pmd_stm_clock_mux_sel,
+	       sys_clkin_ck, dpll_core_m6x2_ck, tie_low_clock_ck);
 
-static struct clk pmd_stm_clock_mux_ck = {
-	.name		= "pmd_stm_clock_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(pmd_stm_clock_mux_ck, sys_clkin_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk pmd_trace_clk_mux_ck = {
-	.name		= "pmd_trace_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(pmd_trace_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static const struct clksel syc_clk_div_div[] = {
-	{ .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(syc_clk_div_div, sys_clkin_ck, div2_1to2_rates);
 
-static struct clk syc_clk_div_ck = {
-	.name		= "syc_clk_div_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= syc_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
-	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(syc_clk_div_ck, sys_clkin_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(syc_clk_div_div, CM_ABE_DSS_SYS_CLKSEL, CLKSEL_0_0));
 
 /* Leaf clocks controlled by modules */
 
-static struct clk aes1_fck = {
-	.name		= "aes1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_AES1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(aes1_fck, l3_div_ck, l4_secure_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4SEC_AES1));
 
-static struct clk aes2_fck = {
-	.name		= "aes2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_AES2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(aes2_fck, l3_div_ck, l4_secure_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4SEC_AES2));
 
-static struct clk aess_fck = {
-	.name		= "aess_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_AESS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &aess_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(aess_fck, aess_fclk, abe_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM1_ABE_AESS));
 
-static struct clk bandgap_fclk = {
-	.name		= "bandgap_fclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(bandgap_fclk, sys_32k_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4SEC_AES2, OPTFCLKEN_BGAP_32K));
 
-static struct clk des3des_fck = {
-	.name		= "des3des_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(des3des_fck, l4_div_ck, l4_secure_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4SEC_DES3DES));
 
-static const struct clksel dmic_sync_mux_sel[] = {
-	{ .parent = &abe_24m_fclk, .rates = div_1_0_rates },
-	{ .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
-	{ .parent = &func_24m_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(dmic_sync_mux_sel,
+	       abe_24m_fclk, syc_clk_div_ck, func_24m_clk);
 
-static struct clk dmic_sync_mux_ck = {
-	.name		= "dmic_sync_mux_ck",
-	.parent		= &abe_24m_fclk,
-	.clksel		= dmic_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(dmic_sync_mux_ck, abe_24m_fclk,
+	     CLOCK_CLKSEL_INIT(dmic_sync_mux_sel,
+			       CM1_ABE_DMIC_CLKCTRL, CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
-	{ .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(func_dmic_abe_gfclk_sel,
+	       dmic_sync_mux_ck, pad_clks_ck, slimbus_clk);
 
 /* Merged func_dmic_abe_gfclk into dmic */
-static struct clk dmic_fck = {
-	.name		= "dmic_fck",
-	.parent		= &dmic_sync_mux_ck,
-	.clksel		= func_dmic_abe_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(dmic_fck, dmic_sync_mux_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(func_dmic_abe_gfclk_sel,
+				     CM1_ABE_DMIC, CLKSEL_SOURCE));
 
-static struct clk dsp_fck = {
-	.name		= "dsp_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_TESLA_TESLA_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "tesla_clkdm",
-	.parent		= &dpll_iva_m4x2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dsp_fck, dpll_iva_m4x2_ck, tesla_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_TESLA_TESLA));
 
-static struct clk dss_sys_clk = {
-	.name		= "dss_sys_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &syc_clk_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dss_sys_clk, syc_clk_div_ck, l3_dss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_SYS_CLK));
 
-static struct clk dss_tv_clk = {
-	.name		= "dss_tv_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &extalt_clkin_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dss_tv_clk, extalt_clkin_ck, l3_dss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_TV_CLK));
 
-static struct clk dss_dss_clk = {
-	.name		= "dss_dss_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &dpll_per_m5x2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dss_dss_clk, dpll_per_m5x2_ck, l3_dss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_DSSCLK));
 
-static struct clk dss_48mhz_clk = {
-	.name		= "dss_48mhz_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &func_48mc_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dss_48mhz_clk, func_48mc_fclk, l3_dss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_48MHZ_CLK));
 
-static struct clk dss_fck = {
-	.name		= "dss_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dss_fck, l3_div_ck, l3_dss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_DSS_DSS));
 
-static struct clk efuse_ctrl_cust_fck = {
-	.name		= "efuse_ctrl_cust_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_cefuse_clkdm",
-	.parent		= &sys_clkin_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(efuse_ctrl_cust_fck, sys_clkin_ck, l4_cefuse_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_CEFUSE_CEFUSE));
 
-static struct clk emif1_fck = {
-	.name		= "emif1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.flags		= ENABLE_ON_INIT,
-	.clkdm_name	= "l3_emif_clkdm",
-	.parent		= &ddrphy_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(emif1_fck, ddrphy_ck, l3_emif_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_MEMIF_EMIF_1),
+		CLOCK_FLAGS_ENABLE());
 
-static struct clk emif2_fck = {
-	.name		= "emif2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.flags		= ENABLE_ON_INIT,
-	.clkdm_name	= "l3_emif_clkdm",
-	.parent		= &ddrphy_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(emif2_fck, ddrphy_ck, l3_emif_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_MEMIF_EMIF_2),
+		CLOCK_FLAGS_ENABLE());
 
-static const struct clksel fdif_fclk_div[] = {
-	{ .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(fdif_fclk_div, dpll_per_m4x2_ck, div3_1to4_rates);
 
 /* Merged fdif_fclk into fdif */
 static struct clk fdif_fck = {
-- 
1.7.2.3


^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [PATCHv2 1/2] [RFC] OMAP4: clock data: shrink clock data utilizing preprocessor.
@ 2011-05-15 21:45   ` Vladimir Zapolskiy
  0 siblings, 0 replies; 16+ messages in thread
From: Vladimir Zapolskiy @ 2011-05-15 21:45 UTC (permalink / raw)
  To: linux-arm-kernel

This mass change reduces homogeneous data chunks along clock
definitions. No semantical difference is added in the change.

Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com>
---
 arch/arm/mach-omap2/clock44xx_data.c | 1638 ++++++++++------------------------
 1 files changed, 470 insertions(+), 1168 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 8c96567..423f180 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -7,6 +7,7 @@
  * Paul Walmsley (paul at pwsan.com)
  * Rajendra Nayak (rnayak at ti.com)
  * Benoit Cousson (b-cousson at ti.com)
+ * Vladimir Zapolskiy (vzapolskiy at gmail.com)
  *
  * This file is automatically generated from the OMAP hardware databases.
  * We respectfully ask that any modifications to this file be coordinated
@@ -42,129 +43,218 @@
 #define OMAP4430_MODULEMODE_HWCTRL			0
 #define OMAP4430_MODULEMODE_SWCTRL			1
 
-/* Root clocks */
-
-static struct clk extalt_clkin_ck = {
-	.name		= "extalt_clkin_ck",
-	.rate		= 59000000,
-	.ops		= &clkops_null,
-};
-
-static struct clk pad_clks_ck = {
-	.name		= "pad_clks_ck",
-	.rate		= 12000000,
-	.ops            = &clkops_omap2_dflt,
-	.enable_reg     = OMAP4430_CM_CLKSEL_ABE,
-	.enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
-};
-
-static struct clk pad_slimbus_core_clks_ck = {
-	.name		= "pad_slimbus_core_clks_ck",
-	.rate		= 12000000,
-	.ops		= &clkops_null,
-};
-
-static struct clk secure_32k_clk_src_ck = {
-	.name		= "secure_32k_clk_src_ck",
-	.rate		= 32768,
-	.ops		= &clkops_null,
-};
-
-static struct clk slimbus_clk = {
-	.name		= "slimbus_clk",
-	.rate		= 12000000,
-	.ops            = &clkops_omap2_dflt,
-	.enable_reg     = OMAP4430_CM_CLKSEL_ABE,
-	.enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
-};
-
-static struct clk sys_32k_ck = {
-	.name		= "sys_32k_ck",
-	.rate		= 32768,
-	.ops		= &clkops_null,
-};
-
-static struct clk virt_12000000_ck = {
-	.name		= "virt_12000000_ck",
-	.ops		= &clkops_null,
-	.rate		= 12000000,
-};
-
-static struct clk virt_13000000_ck = {
-	.name		= "virt_13000000_ck",
-	.ops		= &clkops_null,
-	.rate		= 13000000,
-};
-
-static struct clk virt_16800000_ck = {
-	.name		= "virt_16800000_ck",
-	.ops		= &clkops_null,
-	.rate		= 16800000,
-};
-
-static struct clk virt_19200000_ck = {
-	.name		= "virt_19200000_ck",
-	.ops		= &clkops_null,
-	.rate		= 19200000,
-};
-
-static struct clk virt_26000000_ck = {
-	.name		= "virt_26000000_ck",
-	.ops		= &clkops_null,
-	.rate		= 26000000,
-};
+#define CLOCK_FLAGS_ENABLE(...)						\
+	.flags		= ENABLE_ON_INIT,				\
+	##__VA_ARGS__
+
+#define CLOCK_OPS(_ops, ...)						\
+	.ops		= &_ops,					\
+	##__VA_ARGS__
+
+#define CLOCK_OPS_NULL(...)						\
+	CLOCK_OPS(clkops_null, ##__VA_ARGS__)
+
+#define CLOCK_OPS_DPLL(...)						\
+	CLOCK_OPS(clkops_omap4_dpllmx_ops, ##__VA_ARGS__)
+
+#define CLOCK_OPS_DFLT0(_reg, _bit, ...)				\
+	.ops		= &clkops_omap2_dflt,				\
+	.enable_reg	= OMAP4430_##_reg,				\
+	.enable_bit	= OMAP4430_##_bit##_SHIFT,			\
+	##__VA_ARGS__
+
+#define CLOCK_OPS_DFLT(_reg, _bit, ...)					\
+	.ops		= &clkops_omap2_dflt,				\
+	.enable_reg	= OMAP4430_##_reg##_CLKCTRL,			\
+	.enable_bit	= OMAP4430_##_bit##_SHIFT,			\
+	##__VA_ARGS__
+
+#define CLOCK_OPS_DFLT_SW(_reg, ...)					\
+	.ops		= &clkops_omap2_dflt,				\
+	.enable_reg	= OMAP4430_##_reg##_CLKCTRL,			\
+	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,			\
+	##__VA_ARGS__
+
+#define CLOCK_OPS_DFLT_HW(_reg, ...)					\
+	.ops		= &clkops_omap2_dflt,				\
+	.enable_reg	= OMAP4430_##_reg##_CLKCTRL,			\
+	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,			\
+	##__VA_ARGS__
+
+#define CLOCK_OPS_DFLT2(_reg, ...)					\
+	.ops		= &clkops_omap2_dflt,				\
+	.enable_reg	= OMAP4_##_reg,					\
+	.enable_bit	= OMAP4_ENABLE_SHIFT,				\
+	##__VA_ARGS__
+
+#define CLOCK_RECALC(_recalc, ...)					\
+	.recalc		= &_recalc,					\
+	##__VA_ARGS__
+
+#define CLOCK_RECALC_FOLLOWPARENT(...)					\
+	CLOCK_RECALC(followparent_recalc, ##__VA_ARGS__)
+
+#define CLOCK_RECALC_CLKSEL(...)					\
+	CLOCK_RECALC(omap2_clksel_recalc, ##__VA_ARGS__)
+
+#define CLOCK_RECALC_CLKOUTX2(...)					\
+	.flags		= CLOCK_CLKOUTX2,				\
+	CLOCK_RECALC(omap3_clkoutx2_recalc, ##__VA_ARGS__)
+
+#define CLOCK_RECALC_RATE(_recalc, _round_rate, _set_rate, ...)		\
+	.recalc		= &_recalc,					\
+	.round_rate	= &_round_rate,					\
+	.set_rate	= &_set_rate,					\
+	##__VA_ARGS__
+
+#define CLOCK_RECALC_FIXED(_div, ...)					\
+	.recalc		= &omap_fixed_divisor_recalc,			\
+	.fixed_div	= _div,						\
+	CLOCK_OPS_NULL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_RECALC_RATE_CLKSEL(...)					\
+	CLOCK_RECALC_RATE(omap2_clksel_recalc,				\
+			  omap2_clksel_round_rate,			\
+			  omap2_clksel_set_rate, ##__VA_ARGS__)
+
+#define CLOCK_RECALC_RATE_DPLL(_dpll_data, ...)				\
+	.init		= &omap2_init_dpll_parent,			\
+	.dpll_data	= &_dpll_data,					\
+	CLOCK_RECALC_RATE(omap3_dpll_recalc,				\
+			  omap2_dpll_round_rate,			\
+			  omap3_noncore_dpll_set_rate),			\
+	CLOCK_OPS(clkops_omap3_noncore_dpll_ops),			\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL_DPLL(_reg, ...)					\
+	.clksel_reg	= OMAP4430_##_reg,				\
+	CLOCK_OPS_DPLL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL_INIT(_sel, _reg, _mask, ...)			\
+	.init		= &omap2_init_clksel_parent,			\
+	.clksel		= _sel,						\
+	.clksel_reg	= OMAP4430_##_reg,				\
+	.clksel_mask	= OMAP4430_##_mask##_MASK,			\
+	CLOCK_OPS_NULL(),						\
+	CLOCK_RECALC_CLKSEL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL_INIT_SW(_sel, _reg, _mask, ...)			\
+	.init		= &omap2_init_clksel_parent,			\
+	.clksel		= _sel,						\
+	.clksel_reg	= OMAP4430_##_reg##_CLKCTRL,			\
+	.clksel_mask	= OMAP4430_##_mask##_MASK,			\
+	CLOCK_OPS_DFLT_SW(_reg),					\
+	CLOCK_RECALC_CLKSEL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL_INIT2(_sel, _reg, _mask, ...)			\
+	.init		= &omap2_init_clksel_parent,			\
+	.clksel		= _sel,						\
+	.clksel_reg	= OMAP4_##_reg,					\
+	.clksel_mask	= OMAP4_##_mask##_MASK,				\
+	CLOCK_RECALC_CLKSEL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL0(_sel, _reg, _mask, ...)				\
+	.clksel		= _sel,						\
+	.clksel_reg	= OMAP4430_##_reg,				\
+	.clksel_mask	= OMAP4430_##_mask##_MASK,			\
+	CLOCK_RECALC_CLKSEL(),						\
+	##__VA_ARGS__
+
+#define CLOCK_CLKSEL(_sel, _reg, _mask, ...)				\
+	.clksel		= _sel,						\
+	.clksel_reg	= OMAP4430_##_reg,				\
+	.clksel_mask	= OMAP4430_##_mask##_MASK,			\
+	CLOCK_RECALC_RATE_CLKSEL(),					\
+	##__VA_ARGS__
+
+#define DEFINE_ROOT_CLOCK(_name, _rate, ...)				\
+	static struct clk _name = {					\
+		.name		= #_name,				\
+		.rate		= _rate,				\
+		##__VA_ARGS__						\
+	}
 
-static struct clk virt_27000000_ck = {
-	.name		= "virt_27000000_ck",
-	.ops		= &clkops_null,
-	.rate		= 27000000,
-};
+#define DEFINE_CLOCK(_name, _parent, ...)				\
+	static struct clk _name = {					\
+		.name		= #_name,				\
+		.parent		= &_parent,				\
+		##__VA_ARGS__						\
+	}
 
-static struct clk virt_38400000_ck = {
-	.name		= "virt_38400000_ck",
-	.ops		= &clkops_null,
-	.rate		= 38400000,
-};
+#define DEFINE_CLOCK_DM(_name, _parent, _clkdm, ...)			\
+	DEFINE_CLOCK(_name, _parent,					\
+		     .clkdm_name	= #_clkdm, ##__VA_ARGS__)
 
-static const struct clksel_rate div_1_0_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+#define DEFINE_CLKSEL(_name, _parent, _rates)				\
+	static const struct clksel _name[] = {				\
+		{ .parent = &_parent, .rates = _rates },		\
+		{ .parent = NULL },					\
+	}
 
-static const struct clksel_rate div_1_1_rates[] = {
-	{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+#define DEFINE_CLKSEL2(_name, _parent0, _parent1)			\
+	static const struct clksel _name[] = {				\
+		{ .parent = &_parent0, .rates = div_1_0_rates },	\
+		{ .parent = &_parent1, .rates = div_1_1_rates },	\
+		{ .parent = NULL },					\
+	}
 
-static const struct clksel_rate div_1_2_rates[] = {
-	{ .div = 1, .val = 2, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+#define DEFINE_CLKSEL3(_name, _parent0, _parent1, _parent2)		\
+	static const struct clksel _name[] = {				\
+		{ .parent = &_parent0, .rates = div_1_0_rates },	\
+		{ .parent = &_parent1, .rates = div_1_1_rates },	\
+		{ .parent = &_parent2, .rates = div_1_2_rates },	\
+		{ .parent = NULL },					\
+	}
 
-static const struct clksel_rate div_1_3_rates[] = {
-	{ .div = 1, .val = 3, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+#define DEFINE_CLKSEL_RATE(n)						\
+	static const struct clksel_rate div_1_##n##_rates[] = {		\
+		{ .div = 1, .val = n, .flags = RATE_IN_4430 },		\
+		{ .div = 0 },						\
+	}
 
-static const struct clksel_rate div_1_4_rates[] = {
-	{ .div = 1, .val = 4, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+#define DEFINE_CLKSEL_RATE2(_range, _div0, _div1)			\
+	static const struct clksel_rate div2_##_range##_rates[] = {	\
+		{ .div = _div0, .val = 0, .flags = RATE_IN_4430 },	\
+		{ .div = _div1, .val = 1, .flags = RATE_IN_4430 },	\
+		{ .div = 0 },						\
+	}
 
-static const struct clksel_rate div_1_5_rates[] = {
-	{ .div = 1, .val = 5, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+/*
+#define DEFINE_DPLL_DATA(_name, )
+*/
 
-static const struct clksel_rate div_1_6_rates[] = {
-	{ .div = 1, .val = 6, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+/* Root clocks */
 
-static const struct clksel_rate div_1_7_rates[] = {
-	{ .div = 1, .val = 7, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_ROOT_CLOCK(extalt_clkin_ck,		59000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(pad_slimbus_core_clks_ck,	12000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(secure_32k_clk_src_ck,	32768,    CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(sys_32k_ck,			32768,    CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_12000000_ck,		12000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_13000000_ck,		13000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_16800000_ck,		16800000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_19200000_ck,		19200000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_26000000_ck,		26000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_27000000_ck,		27000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(virt_38400000_ck,		38400000, CLOCK_OPS_NULL());
+
+DEFINE_ROOT_CLOCK(pad_clks_ck,			12000000,
+		  CLOCK_OPS_DFLT0(CM_CLKSEL_ABE, PAD_CLKS_GATE));
+DEFINE_ROOT_CLOCK(slimbus_clk,			12000000,
+		  CLOCK_OPS_DFLT0(CM_CLKSEL_ABE, SLIMBUS_CLK_GATE));
+
+DEFINE_CLKSEL_RATE(0);
+DEFINE_CLKSEL_RATE(1);
+DEFINE_CLKSEL_RATE(2);
+DEFINE_CLKSEL_RATE(3);
+DEFINE_CLKSEL_RATE(4);
+DEFINE_CLKSEL_RATE(5);
+DEFINE_CLKSEL_RATE(6);
+DEFINE_CLKSEL_RATE(7);
 
 static const struct clksel sys_clkin_sel[] = {
 	{ .parent = &virt_12000000_ck, .rates = div_1_1_rates },
@@ -177,72 +267,24 @@ static const struct clksel sys_clkin_sel[] = {
 	{ .parent = NULL },
 };
 
-static struct clk sys_clkin_ck = {
-	.name		= "sys_clkin_ck",
-	.rate		= 38400000,
-	.clksel		= sys_clkin_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_SYS_CLKSEL,
-	.clksel_mask	= OMAP4430_SYS_CLKSEL_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
-
-static struct clk tie_low_clock_ck = {
-	.name		= "tie_low_clock_ck",
-	.rate		= 0,
-	.ops		= &clkops_null,
-};
-
-static struct clk utmi_phy_clkout_ck = {
-	.name		= "utmi_phy_clkout_ck",
-	.rate		= 60000000,
-	.ops		= &clkops_null,
-};
-
-static struct clk xclk60mhsp1_ck = {
-	.name		= "xclk60mhsp1_ck",
-	.rate		= 60000000,
-	.ops		= &clkops_null,
-};
-
-static struct clk xclk60mhsp2_ck = {
-	.name		= "xclk60mhsp2_ck",
-	.rate		= 60000000,
-	.ops		= &clkops_null,
-};
+DEFINE_ROOT_CLOCK(sys_clkin_ck, 38400000,
+		  CLOCK_CLKSEL_INIT(sys_clkin_sel, CM_SYS_CLKSEL, SYS_CLKSEL));
 
-static struct clk xclk60motg_ck = {
-	.name		= "xclk60motg_ck",
-	.rate		= 60000000,
-	.ops		= &clkops_null,
-};
+DEFINE_ROOT_CLOCK(tie_low_clock_ck,   0,        CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(utmi_phy_clkout_ck, 60000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(xclk60mhsp1_ck,     60000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(xclk60mhsp2_ck,     60000000, CLOCK_OPS_NULL());
+DEFINE_ROOT_CLOCK(xclk60motg_ck,      60000000, CLOCK_OPS_NULL());
 
 /* Module clocks and DPLL outputs */
 
-static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
-
-static struct clk abe_dpll_bypass_clk_mux_ck = {
-	.name		= "abe_dpll_bypass_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLKSEL2(abe_dpll_bypass_clk_mux_sel, sys_clkin_ck, sys_32k_ck);
 
-static struct clk abe_dpll_refclk_mux_ck = {
-	.name		= "abe_dpll_refclk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_ABE_PLL_REF_CLKSEL,
-	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(abe_dpll_bypass_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
+DEFINE_CLOCK(abe_dpll_refclk_mux_ck, sys_clkin_ck,
+	     CLOCK_CLKSEL_INIT(abe_dpll_bypass_clk_mux_sel,
+			       CM_ABE_PLL_REF_CLKSEL, CLKSEL_0_0));
 
 /* DPLL_ABE */
 static struct dpll_data dpll_abe_dd = {
@@ -263,26 +305,11 @@ static struct dpll_data dpll_abe_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_abe_ck, abe_dpll_refclk_mux_ck,
+	     CLOCK_RECALC_RATE_DPLL(dpll_abe_dd));
 
-static struct clk dpll_abe_ck = {
-	.name		= "dpll_abe_ck",
-	.parent		= &abe_dpll_refclk_mux_ck,
-	.dpll_data	= &dpll_abe_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk dpll_abe_x2_ck = {
-	.name		= "dpll_abe_x2_ck",
-	.parent		= &dpll_abe_ck,
-	.flags		= CLOCK_CLKOUTX2,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap3_clkoutx2_recalc,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
-};
+DEFINE_CLOCK(dpll_abe_x2_ck, dpll_abe_ck,
+	     CLOCK_CLKSEL_DPLL(CM_DIV_M2_DPLL_ABE), CLOCK_RECALC_CLKOUTX2());
 
 static const struct clksel_rate div31_1to31_rates[] = {
 	{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
@@ -319,30 +346,13 @@ static const struct clksel_rate div31_1to31_rates[] = {
 	{ .div = 0 },
 };
 
-static const struct clksel dpll_abe_m2x2_div[] = {
-	{ .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_abe_m2x2_div, dpll_abe_x2_ck, div31_1to31_rates);
 
-static struct clk dpll_abe_m2x2_ck = {
-	.name		= "dpll_abe_m2x2_ck",
-	.parent		= &dpll_abe_x2_ck,
-	.clksel		= dpll_abe_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_abe_m2x2_ck, dpll_abe_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_abe_m2x2_div,
+			  CM_DIV_M2_DPLL_ABE, DPLL_CLKOUT_DIV));
 
-static struct clk abe_24m_fclk = {
-	.name		= "abe_24m_fclk",
-	.parent		= &dpll_abe_m2x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 8,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(abe_24m_fclk, dpll_abe_m2x2_ck, CLOCK_RECALC_FIXED(8));
 
 static const struct clksel_rate div3_1to4_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
@@ -351,74 +361,28 @@ static const struct clksel_rate div3_1to4_rates[] = {
 	{ .div = 0 },
 };
 
-static const struct clksel abe_clk_div[] = {
-	{ .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(abe_clk_div, dpll_abe_m2x2_ck, div3_1to4_rates);
 
-static struct clk abe_clk = {
-	.name		= "abe_clk",
-	.parent		= &dpll_abe_m2x2_ck,
-	.clksel		= abe_clk_div,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_ABE,
-	.clksel_mask	= OMAP4430_CLKSEL_OPP_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(abe_clk, dpll_abe_m2x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(abe_clk_div, CM_CLKSEL_ABE, CLKSEL_OPP));
 
-static const struct clksel_rate div2_1to2_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_CLKSEL_RATE2(1to2, 1, 2);
 
-static const struct clksel aess_fclk_div[] = {
-	{ .parent = &abe_clk, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(aess_fclk_div, abe_clk, div2_1to2_rates);
 
-static struct clk aess_fclk = {
-	.name		= "aess_fclk",
-	.parent		= &abe_clk,
-	.clksel		= aess_fclk_div,
-	.clksel_reg	= OMAP4430_CM1_ABE_AESS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_AESS_FCLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(aess_fclk, abe_clk, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(aess_fclk_div,
+			  CM1_ABE_AESS_CLKCTRL, CLKSEL_AESS_FCLK));
 
-static struct clk dpll_abe_m3x2_ck = {
-	.name		= "dpll_abe_m3x2_ck",
-	.parent		= &dpll_abe_x2_ck,
-	.clksel		= dpll_abe_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M3_DPLL_ABE,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_abe_m3x2_ck, dpll_abe_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_abe_m2x2_div,
+			  CM_DIV_M3_DPLL_ABE, DPLL_CLKOUTHIF_DIV));
 
-static const struct clksel core_hsd_byp_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(core_hsd_byp_clk_mux_sel, sys_clkin_ck, dpll_abe_m3x2_ck);
 
-static struct clk core_hsd_byp_clk_mux_ck = {
-	.name		= "core_hsd_byp_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= core_hsd_byp_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_DPLL_CORE,
-	.clksel_mask	= OMAP4430_DPLL_BYP_CLKSEL_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(core_hsd_byp_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_CLKSEL_INIT(core_hsd_byp_clk_mux_sel,
+			       CM_CLKSEL_DPLL_CORE, DPLL_BYP_CLKSEL));
 
 /* DPLL_CORE */
 static struct dpll_data dpll_core_dd = {
@@ -439,107 +403,39 @@ static struct dpll_data dpll_core_dd = {
 	.min_divider	= 1,
 };
 
+/* originally round_rate/set_rate were NOT defined for dpll_core_ck */
+DEFINE_CLOCK(dpll_core_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_core_dd));
 
-static struct clk dpll_core_ck = {
-	.name		= "dpll_core_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_core_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_core_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-};
-
-static struct clk dpll_core_x2_ck = {
-	.name		= "dpll_core_x2_ck",
-	.parent		= &dpll_core_ck,
-	.flags		= CLOCK_CLKOUTX2,
-	.ops		= &clkops_null,
-	.recalc		= &omap3_clkoutx2_recalc,
-};
+DEFINE_CLOCK(dpll_core_x2_ck, dpll_core_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_CLKOUTX2());
 
-static const struct clksel dpll_core_m6x2_div[] = {
-	{ .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_core_m6x2_div, dpll_core_x2_ck, div31_1to31_rates);
 
-static struct clk dpll_core_m6x2_ck = {
-	.name		= "dpll_core_m6x2_ck",
-	.parent		= &dpll_core_x2_ck,
-	.clksel		= dpll_core_m6x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M6_DPLL_CORE,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m6x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_core_m6x2_div,
+			  CM_DIV_M6_DPLL_CORE, HSDIVIDER_CLKOUT3_DIV));
 
-static const struct clksel dbgclk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(dbgclk_mux_sel, sys_clkin_ck, dpll_core_m6x2_ck);
 
-static struct clk dbgclk_mux_ck = {
-	.name		= "dbgclk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(dbgclk_mux_ck, sys_clkin_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static const struct clksel dpll_core_m2_div[] = {
-	{ .parent = &dpll_core_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_core_m2_div, dpll_core_ck, div31_1to31_rates);
 
-static struct clk dpll_core_m2_ck = {
-	.name		= "dpll_core_m2_ck",
-	.parent		= &dpll_core_ck,
-	.clksel		= dpll_core_m2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_CORE,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m2_ck, dpll_core_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_core_m2_div,
+			  CM_DIV_M2_DPLL_CORE, DPLL_CLKOUT_DIV));
 
-static struct clk ddrphy_ck = {
-	.name		= "ddrphy_ck",
-	.parent		= &dpll_core_m2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 2,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(ddrphy_ck, dpll_core_m2_ck, CLOCK_RECALC_FIXED(2));
 
-static struct clk dpll_core_m5x2_ck = {
-	.name		= "dpll_core_m5x2_ck",
-	.parent		= &dpll_core_x2_ck,
-	.clksel		= dpll_core_m6x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_CORE,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m5x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_core_m6x2_div,
+			  CM_DIV_M5_DPLL_CORE, HSDIVIDER_CLKOUT2_DIV));
 
-static const struct clksel div_core_div[] = {
-	{ .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(div_core_div, dpll_core_m5x2_ck, div2_1to2_rates);
 
-static struct clk div_core_ck = {
-	.name		= "div_core_ck",
-	.parent		= &dpll_core_m5x2_ck,
-	.clksel		= div_core_div,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
-	.clksel_mask	= OMAP4430_CLKSEL_CORE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(div_core_ck, dpll_core_m5x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(div_core_div, CM_CLKSEL_CORE, CLKSEL_CORE));
 
 static const struct clksel_rate div4_1to8_rates[] = {
 	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
@@ -549,114 +445,40 @@ static const struct clksel_rate div4_1to8_rates[] = {
 	{ .div = 0 },
 };
 
-static const struct clksel div_iva_hs_clk_div[] = {
-	{ .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(div_iva_hs_clk_div, dpll_core_m5x2_ck, div4_1to8_rates);
 
-static struct clk div_iva_hs_clk = {
-	.name		= "div_iva_hs_clk",
-	.parent		= &dpll_core_m5x2_ck,
-	.clksel		= div_iva_hs_clk_div,
-	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_IVA,
-	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(div_iva_hs_clk, dpll_core_m5x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(div_iva_hs_clk_div, CM_BYPCLK_DPLL_IVA, CLKSEL_0_1));
 
-static struct clk div_mpu_hs_clk = {
-	.name		= "div_mpu_hs_clk",
-	.parent		= &dpll_core_m5x2_ck,
-	.clksel		= div_iva_hs_clk_div,
-	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_MPU,
-	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(div_mpu_hs_clk, dpll_core_m5x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(div_iva_hs_clk_div, CM_BYPCLK_DPLL_MPU, CLKSEL_0_1));
 
-static struct clk dpll_core_m4x2_ck = {
-	.name		= "dpll_core_m4x2_ck",
-	.parent		= &dpll_core_x2_ck,
-	.clksel		= dpll_core_m6x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_CORE,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m4x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_core_m6x2_div,
+			  CM_DIV_M4_DPLL_CORE, HSDIVIDER_CLKOUT1_DIV));
 
-static struct clk dll_clk_div_ck = {
-	.name		= "dll_clk_div_ck",
-	.parent		= &dpll_core_m4x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 2,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(dll_clk_div_ck, dpll_core_m4x2_ck, CLOCK_RECALC_FIXED(2));
 
-static const struct clksel dpll_abe_m2_div[] = {
-	{ .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_abe_m2_div, dpll_abe_ck, div31_1to31_rates);
 
-static struct clk dpll_abe_m2_ck = {
-	.name		= "dpll_abe_m2_ck",
-	.parent		= &dpll_abe_ck,
-	.clksel		= dpll_abe_m2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_abe_m2_ck, dpll_abe_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_abe_m2_div,
+			  CM_DIV_M2_DPLL_ABE, DPLL_CLKOUT_DIV));
 
-static struct clk dpll_core_m3x2_ck = {
-	.name		= "dpll_core_m3x2_ck",
-	.parent		= &dpll_core_x2_ck,
-	.clksel		= dpll_core_m6x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M3_DPLL_CORE,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DIV_M3_DPLL_CORE,
-	.enable_bit	= OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m3x2_ck, dpll_core_x2_ck,
+	     CLOCK_OPS_DFLT0(CM_DIV_M3_DPLL_CORE, DPLL_CLKOUTHIF_GATE_CTRL),
+	     CLOCK_CLKSEL(dpll_core_m6x2_div,
+			  CM_DIV_M3_DPLL_CORE, DPLL_CLKOUTHIF_DIV));
 
-static struct clk dpll_core_m7x2_ck = {
-	.name		= "dpll_core_m7x2_ck",
-	.parent		= &dpll_core_x2_ck,
-	.clksel		= dpll_core_m6x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M7_DPLL_CORE,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_core_m7x2_ck, dpll_core_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_core_m6x2_div,
+			  CM_DIV_M7_DPLL_CORE, HSDIVIDER_CLKOUT4_DIV));
 
-static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(iva_hsd_byp_clk_mux_sel, sys_clkin_ck, div_iva_hs_clk);
 
-static struct clk iva_hsd_byp_clk_mux_ck = {
-	.name		= "iva_hsd_byp_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= iva_hsd_byp_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_DPLL_IVA,
-	.clksel_mask	= OMAP4430_DPLL_BYP_CLKSEL_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(iva_hsd_byp_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_CLKSEL_INIT(iva_hsd_byp_clk_mux_sel,
+			       CM_CLKSEL_DPLL_IVA, DPLL_BYP_CLKSEL));
 
 /* DPLL_IVA */
 static struct dpll_data dpll_iva_dd = {
@@ -677,54 +499,21 @@ static struct dpll_data dpll_iva_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_iva_ck, sys_clkin_ck,
+	     CLOCK_RECALC_RATE_DPLL(dpll_iva_dd));
 
-static struct clk dpll_iva_ck = {
-	.name		= "dpll_iva_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_iva_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk dpll_iva_x2_ck = {
-	.name		= "dpll_iva_x2_ck",
-	.parent		= &dpll_iva_ck,
-	.flags		= CLOCK_CLKOUTX2,
-	.ops		= &clkops_null,
-	.recalc		= &omap3_clkoutx2_recalc,
-};
+DEFINE_CLOCK(dpll_iva_x2_ck, dpll_iva_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_CLKOUTX2());
 
-static const struct clksel dpll_iva_m4x2_div[] = {
-	{ .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_iva_m4x2_div, dpll_iva_x2_ck, div31_1to31_rates);
 
-static struct clk dpll_iva_m4x2_ck = {
-	.name		= "dpll_iva_m4x2_ck",
-	.parent		= &dpll_iva_x2_ck,
-	.clksel		= dpll_iva_m4x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_IVA,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_iva_m4x2_ck, dpll_iva_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_iva_m4x2_div,
+			  CM_DIV_M4_DPLL_IVA, HSDIVIDER_CLKOUT1_DIV));
 
-static struct clk dpll_iva_m5x2_ck = {
-	.name		= "dpll_iva_m5x2_ck",
-	.parent		= &dpll_iva_x2_ck,
-	.clksel		= dpll_iva_m4x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_IVA,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_iva_m5x2_ck, dpll_iva_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_iva_m4x2_div,
+			  CM_DIV_M5_DPLL_IVA, HSDIVIDER_CLKOUT2_DIV));
 
 /* DPLL_MPU */
 static struct dpll_data dpll_mpu_dd = {
@@ -745,59 +534,21 @@ static struct dpll_data dpll_mpu_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_mpu_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_mpu_dd));
 
-static struct clk dpll_mpu_ck = {
-	.name		= "dpll_mpu_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_mpu_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static const struct clksel dpll_mpu_m2_div[] = {
-	{ .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_mpu_m2_div, dpll_mpu_ck, div31_1to31_rates);
 
-static struct clk dpll_mpu_m2_ck = {
-	.name		= "dpll_mpu_m2_ck",
-	.parent		= &dpll_mpu_ck,
-	.clksel		= dpll_mpu_m2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_MPU,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_mpu_m2_ck, dpll_mpu_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_mpu_m2_div,
+			  CM_DIV_M2_DPLL_MPU, DPLL_CLKOUT_DIV));
 
-static struct clk per_hs_clk_div_ck = {
-	.name		= "per_hs_clk_div_ck",
-	.parent		= &dpll_abe_m3x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 2,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(per_hs_clk_div_ck, dpll_abe_m3x2_ck, CLOCK_RECALC_FIXED(2));
 
-static const struct clksel per_hsd_byp_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(per_hsd_byp_clk_mux_sel, sys_clkin_ck, per_hs_clk_div_ck);
 
-static struct clk per_hsd_byp_clk_mux_ck = {
-	.name		= "per_hsd_byp_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= per_hsd_byp_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_DPLL_PER,
-	.clksel_mask	= OMAP4430_DPLL_BYP_CLKSEL_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(per_hsd_byp_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_CLKSEL_INIT(per_hsd_byp_clk_mux_sel,
+			       CM_CLKSEL_DPLL_PER, DPLL_BYP_CLKSEL));
 
 /* DPLL_PER */
 static struct dpll_data dpll_per_dd = {
@@ -818,122 +569,43 @@ static struct dpll_data dpll_per_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_per_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_per_dd));
 
-static struct clk dpll_per_ck = {
-	.name		= "dpll_per_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_per_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
+DEFINE_CLKSEL(dpll_per_m2_div, dpll_per_ck, div31_1to31_rates);
 
-static const struct clksel dpll_per_m2_div[] = {
-	{ .parent = &dpll_per_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(dpll_per_m2_ck, dpll_per_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2_div,
+			  CM_DIV_M2_DPLL_PER, DPLL_CLKOUT_DIV));
 
-static struct clk dpll_per_m2_ck = {
-	.name		= "dpll_per_m2_ck",
-	.parent		= &dpll_per_ck,
-	.clksel		= dpll_per_m2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_x2_ck, dpll_per_ck,
+	     CLOCK_CLKSEL_DPLL(CM_DIV_M2_DPLL_PER), CLOCK_RECALC_CLKOUTX2());
 
-static struct clk dpll_per_x2_ck = {
-	.name		= "dpll_per_x2_ck",
-	.parent		= &dpll_per_ck,
-	.flags		= CLOCK_CLKOUTX2,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap3_clkoutx2_recalc,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
-};
+DEFINE_CLKSEL(dpll_per_m2x2_div, dpll_per_x2_ck, div31_1to31_rates);
 
-static const struct clksel dpll_per_m2x2_div[] = {
-	{ .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(dpll_per_m2x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M2_DPLL_PER, DPLL_CLKOUT_DIV));
 
-static struct clk dpll_per_m2x2_ck = {
-	.name		= "dpll_per_m2x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_m3x2_ck, dpll_per_x2_ck,
+	     CLOCK_OPS_DFLT0(CM_DIV_M3_DPLL_PER, DPLL_CLKOUTHIF_GATE_CTRL),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M3_DPLL_PER, DPLL_CLKOUTHIF_DIV));
 
-static struct clk dpll_per_m3x2_ck = {
-	.name		= "dpll_per_m3x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M3_DPLL_PER,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DIV_M3_DPLL_PER,
-	.enable_bit	= OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
-
-static struct clk dpll_per_m4x2_ck = {
-	.name		= "dpll_per_m4x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_PER,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_m4x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M4_DPLL_PER, HSDIVIDER_CLKOUT1_DIV));
 
-static struct clk dpll_per_m5x2_ck = {
-	.name		= "dpll_per_m5x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_PER,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_m5x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M5_DPLL_PER, HSDIVIDER_CLKOUT2_DIV));
 
-static struct clk dpll_per_m6x2_ck = {
-	.name		= "dpll_per_m6x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M6_DPLL_PER,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_m6x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M6_DPLL_PER, HSDIVIDER_CLKOUT3_DIV));
 
-static struct clk dpll_per_m7x2_ck = {
-	.name		= "dpll_per_m7x2_ck",
-	.parent		= &dpll_per_x2_ck,
-	.clksel		= dpll_per_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M7_DPLL_PER,
-	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_per_m7x2_ck, dpll_per_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_per_m2x2_div,
+			  CM_DIV_M7_DPLL_PER, HSDIVIDER_CLKOUT4_DIV));
 
 /* DPLL_UNIPRO */
 static struct dpll_data dpll_unipro_dd = {
@@ -955,50 +627,19 @@ static struct dpll_data dpll_unipro_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_unipro_ck, sys_clkin_ck,
+	     CLOCK_RECALC_RATE_DPLL(dpll_unipro_dd));
 
-static struct clk dpll_unipro_ck = {
-	.name		= "dpll_unipro_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_unipro_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk dpll_unipro_x2_ck = {
-	.name		= "dpll_unipro_x2_ck",
-	.parent		= &dpll_unipro_ck,
-	.flags		= CLOCK_CLKOUTX2,
-	.ops		= &clkops_null,
-	.recalc		= &omap3_clkoutx2_recalc,
-};
+DEFINE_CLOCK(dpll_unipro_x2_ck, dpll_unipro_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_CLKOUTX2());
 
-static const struct clksel dpll_unipro_m2x2_div[] = {
-	{ .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_unipro_m2x2_div, dpll_unipro_x2_ck, div31_1to31_rates);
 
-static struct clk dpll_unipro_m2x2_ck = {
-	.name		= "dpll_unipro_m2x2_ck",
-	.parent		= &dpll_unipro_x2_ck,
-	.clksel		= dpll_unipro_m2x2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(dpll_unipro_m2x2_ck, dpll_unipro_x2_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_unipro_m2x2_div,
+			  CM_DIV_M2_DPLL_UNIPRO, DPLL_CLKOUT_DIV));
 
-static struct clk usb_hs_clk_div_ck = {
-	.name		= "usb_hs_clk_div_ck",
-	.parent		= &dpll_abe_m3x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 3,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(usb_hs_clk_div_ck, dpll_abe_m3x2_ck, CLOCK_RECALC_FIXED(3));
 
 /* DPLL_USB */
 static struct dpll_data dpll_usb_dd = {
@@ -1020,528 +661,189 @@ static struct dpll_data dpll_usb_dd = {
 	.min_divider	= 1,
 };
 
+DEFINE_CLOCK(dpll_usb_ck, sys_clkin_ck, CLOCK_RECALC_RATE_DPLL(dpll_usb_dd));
 
-static struct clk dpll_usb_ck = {
-	.name		= "dpll_usb_ck",
-	.parent		= &sys_clkin_ck,
-	.dpll_data	= &dpll_usb_dd,
-	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_omap3_noncore_dpll_ops,
-	.recalc		= &omap3_dpll_recalc,
-	.round_rate	= &omap2_dpll_round_rate,
-	.set_rate	= &omap3_noncore_dpll_set_rate,
-};
+DEFINE_CLOCK(dpll_usb_clkdcoldo_ck, dpll_usb_ck,
+	     CLOCK_CLKSEL_DPLL(CM_CLKDCOLDO_DPLL_USB),
+	     CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk dpll_usb_clkdcoldo_ck = {
-	.name		= "dpll_usb_clkdcoldo_ck",
-	.parent		= &dpll_usb_ck,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.clksel_reg	= OMAP4430_CM_CLKDCOLDO_DPLL_USB,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLKSEL(dpll_usb_m2_div, dpll_usb_ck, div31_1to31_rates);
 
-static const struct clksel dpll_usb_m2_div[] = {
-	{ .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(dpll_usb_m2_ck, dpll_usb_ck, CLOCK_OPS_DPLL(),
+	     CLOCK_CLKSEL(dpll_usb_m2_div,
+			  CM_DIV_M2_DPLL_USB, DPLL_CLKOUT_DIV_0_6));
 
-static struct clk dpll_usb_m2_ck = {
-	.name		= "dpll_usb_m2_ck",
-	.parent		= &dpll_usb_ck,
-	.clksel		= dpll_usb_m2_div,
-	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_USB,
-	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
-	.ops		= &clkops_omap4_dpllmx_ops,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLKSEL2(ducati_clk_mux_sel, div_core_ck, dpll_per_m6x2_ck);
 
-static const struct clksel ducati_clk_mux_sel[] = {
-	{ .parent = &div_core_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(ducati_clk_mux_ck, div_core_ck,
+	     CLOCK_CLKSEL_INIT(ducati_clk_mux_sel,
+			       CM_CLKSEL_DUCATI_ISS_ROOT, CLKSEL_0_0));
 
-static struct clk ducati_clk_mux_ck = {
-	.name		= "ducati_clk_mux_ck",
-	.parent		= &div_core_ck,
-	.clksel		= ducati_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
-	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(func_12m_fclk, dpll_per_m2x2_ck, CLOCK_RECALC_FIXED(16));
 
-static struct clk func_12m_fclk = {
-	.name		= "func_12m_fclk",
-	.parent		= &dpll_per_m2x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 16,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(func_24m_clk, dpll_per_m2_ck, CLOCK_RECALC_FIXED(4));
 
-static struct clk func_24m_clk = {
-	.name		= "func_24m_clk",
-	.parent		= &dpll_per_m2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 4,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(func_24mc_fclk, dpll_per_m2x2_ck, CLOCK_RECALC_FIXED(8));
 
-static struct clk func_24mc_fclk = {
-	.name		= "func_24mc_fclk",
-	.parent		= &dpll_per_m2x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 8,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLKSEL_RATE2(4to8, 4, 8);
 
-static const struct clksel_rate div2_4to8_rates[] = {
-	{ .div = 4, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 8, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_CLKSEL(func_48m_fclk_div, dpll_per_m2x2_ck, div2_4to8_rates);
 
-static const struct clksel func_48m_fclk_div[] = {
-	{ .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(func_48m_fclk, dpll_per_m2x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(func_48m_fclk_div, CM_SCALE_FCLK, SCALE_FCLK));
 
-static struct clk func_48m_fclk = {
-	.name		= "func_48m_fclk",
-	.parent		= &dpll_per_m2x2_ck,
-	.clksel		= func_48m_fclk_div,
-	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
-	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(func_48mc_fclk, dpll_per_m2x2_ck, CLOCK_RECALC_FIXED(4));
 
-static struct clk func_48mc_fclk = {
-	.name		= "func_48mc_fclk",
-	.parent		= &dpll_per_m2x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 4,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLKSEL_RATE2(2to4, 2, 4);
 
-static const struct clksel_rate div2_2to4_rates[] = {
-	{ .div = 2, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 4, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_CLKSEL(func_64m_fclk_div, dpll_per_m4x2_ck, div2_2to4_rates);
 
-static const struct clksel func_64m_fclk_div[] = {
-	{ .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(func_64m_fclk, dpll_per_m4x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(func_64m_fclk_div, CM_SCALE_FCLK, SCALE_FCLK));
 
-static struct clk func_64m_fclk = {
-	.name		= "func_64m_fclk",
-	.parent		= &dpll_per_m4x2_ck,
-	.clksel		= func_64m_fclk_div,
-	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
-	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
-
-static const struct clksel func_96m_fclk_div[] = {
-	{ .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(func_96m_fclk_div, dpll_per_m2x2_ck, div2_2to4_rates);
 
-static struct clk func_96m_fclk = {
-	.name		= "func_96m_fclk",
-	.parent		= &dpll_per_m2x2_ck,
-	.clksel		= func_96m_fclk_div,
-	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
-	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(func_96m_fclk, dpll_per_m2x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(func_96m_fclk_div, CM_SCALE_FCLK, SCALE_FCLK));
 
-static const struct clksel hsmmc6_fclk_sel[] = {
-	{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
-	{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(hsmmc6_fclk_sel, func_64m_fclk, func_96m_fclk);
 
-static struct clk hsmmc6_fclk = {
-	.name		= "hsmmc6_fclk",
-	.parent		= &func_64m_fclk,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(hsmmc6_fclk, func_64m_fclk,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static const struct clksel_rate div2_1to8_rates[] = {
-	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 8, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_CLKSEL_RATE2(1to8, 1, 8);
 
-static const struct clksel init_60m_fclk_div[] = {
-	{ .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(init_60m_fclk_div, dpll_usb_m2_ck, div2_1to8_rates);
 
-static struct clk init_60m_fclk = {
-	.name		= "init_60m_fclk",
-	.parent		= &dpll_usb_m2_ck,
-	.clksel		= init_60m_fclk_div,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_USB_60MHZ,
-	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(init_60m_fclk, dpll_usb_m2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(init_60m_fclk_div, CM_CLKSEL_USB_60MHZ, CLKSEL_0_0));
 
-static const struct clksel l3_div_div[] = {
-	{ .parent = &div_core_ck, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(l3_div_div, div_core_ck, div2_1to2_rates);
 
-static struct clk l3_div_ck = {
-	.name		= "l3_div_ck",
-	.parent		= &div_core_ck,
-	.clksel		= l3_div_div,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
-	.clksel_mask	= OMAP4430_CLKSEL_L3_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(l3_div_ck, div_core_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(l3_div_div, CM_CLKSEL_CORE, CLKSEL_L3));
 
-static const struct clksel l4_div_div[] = {
-	{ .parent = &l3_div_ck, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(l4_div_div, l3_div_ck, div2_1to2_rates);
 
-static struct clk l4_div_ck = {
-	.name		= "l4_div_ck",
-	.parent		= &l3_div_ck,
-	.clksel		= l4_div_div,
-	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
-	.clksel_mask	= OMAP4430_CLKSEL_L4_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(l4_div_ck, l3_div_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(l4_div_div, CM_CLKSEL_CORE, CLKSEL_L4));
 
-static struct clk lp_clk_div_ck = {
-	.name		= "lp_clk_div_ck",
-	.parent		= &dpll_abe_m2x2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 16,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(lp_clk_div_ck, dpll_abe_m2x2_ck, CLOCK_RECALC_FIXED(16));
 
-static const struct clksel l4_wkup_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(l4_wkup_clk_mux_sel, sys_clkin_ck, lp_clk_div_ck);
 
-static struct clk l4_wkup_clk_mux_ck = {
-	.name		= "l4_wkup_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= l4_wkup_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4_WKUP_CLKSEL,
-	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(l4_wkup_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_CLKSEL_INIT(l4_wkup_clk_mux_sel,
+			       CM_L4_WKUP_CLKSEL, CLKSEL_0_0));
 
-static const struct clksel per_abe_nc_fclk_div[] = {
-	{ .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(per_abe_nc_fclk_div, dpll_abe_m2_ck, div2_1to2_rates);
 
-static struct clk per_abe_nc_fclk = {
-	.name		= "per_abe_nc_fclk",
-	.parent		= &dpll_abe_m2_ck,
-	.clksel		= per_abe_nc_fclk_div,
-	.clksel_reg	= OMAP4430_CM_SCALE_FCLK,
-	.clksel_mask	= OMAP4430_SCALE_FCLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(per_abe_nc_fclk, dpll_abe_m2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(per_abe_nc_fclk_div, CM_SCALE_FCLK, SCALE_FCLK));
 
-static const struct clksel mcasp2_fclk_sel[] = {
-	{ .parent = &func_96m_fclk, .rates = div_1_0_rates },
-	{ .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(mcasp2_fclk_sel, func_96m_fclk, per_abe_nc_fclk);
 
-static struct clk mcasp2_fclk = {
-	.name		= "mcasp2_fclk",
-	.parent		= &func_96m_fclk,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(mcasp2_fclk, func_96m_fclk,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk mcasp3_fclk = {
-	.name		= "mcasp3_fclk",
-	.parent		= &func_96m_fclk,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(mcasp3_fclk, func_96m_fclk,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk ocp_abe_iclk = {
-	.name		= "ocp_abe_iclk",
-	.parent		= &aess_fclk,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(ocp_abe_iclk, aess_fclk,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk per_abe_24m_fclk = {
-	.name		= "per_abe_24m_fclk",
-	.parent		= &dpll_abe_m2_ck,
-	.ops		= &clkops_null,
-	.fixed_div	= 4,
-	.recalc		= &omap_fixed_divisor_recalc,
-};
+DEFINE_CLOCK(per_abe_24m_fclk, dpll_abe_m2_ck, CLOCK_RECALC_FIXED(4));
 
-static const struct clksel pmd_stm_clock_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
-	{ .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(pmd_stm_clock_mux_sel,
+	       sys_clkin_ck, dpll_core_m6x2_ck, tie_low_clock_ck);
 
-static struct clk pmd_stm_clock_mux_ck = {
-	.name		= "pmd_stm_clock_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(pmd_stm_clock_mux_ck, sys_clkin_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk pmd_trace_clk_mux_ck = {
-	.name		= "pmd_trace_clk_mux_ck",
-	.parent		= &sys_clkin_ck,
-	.ops		= &clkops_null,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(pmd_trace_clk_mux_ck, sys_clkin_ck,
+	     CLOCK_OPS_NULL(), CLOCK_RECALC_FOLLOWPARENT());
 
-static const struct clksel syc_clk_div_div[] = {
-	{ .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(syc_clk_div_div, sys_clkin_ck, div2_1to2_rates);
 
-static struct clk syc_clk_div_ck = {
-	.name		= "syc_clk_div_ck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= syc_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
-	.clksel_mask	= OMAP4430_CLKSEL_0_0_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLOCK(syc_clk_div_ck, sys_clkin_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(syc_clk_div_div, CM_ABE_DSS_SYS_CLKSEL, CLKSEL_0_0));
 
 /* Leaf clocks controlled by modules */
 
-static struct clk aes1_fck = {
-	.name		= "aes1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_AES1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(aes1_fck, l3_div_ck, l4_secure_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4SEC_AES1));
 
-static struct clk aes2_fck = {
-	.name		= "aes2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_AES2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(aes2_fck, l3_div_ck, l4_secure_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4SEC_AES2));
 
-static struct clk aess_fck = {
-	.name		= "aess_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_AESS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &aess_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(aess_fck, aess_fclk, abe_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM1_ABE_AESS));
 
-static struct clk bandgap_fclk = {
-	.name		= "bandgap_fclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(bandgap_fclk, sys_32k_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4SEC_AES2, OPTFCLKEN_BGAP_32K));
 
-static struct clk des3des_fck = {
-	.name		= "des3des_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(des3des_fck, l4_div_ck, l4_secure_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4SEC_DES3DES));
 
-static const struct clksel dmic_sync_mux_sel[] = {
-	{ .parent = &abe_24m_fclk, .rates = div_1_0_rates },
-	{ .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
-	{ .parent = &func_24m_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(dmic_sync_mux_sel,
+	       abe_24m_fclk, syc_clk_div_ck, func_24m_clk);
 
-static struct clk dmic_sync_mux_ck = {
-	.name		= "dmic_sync_mux_ck",
-	.parent		= &abe_24m_fclk,
-	.clksel		= dmic_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(dmic_sync_mux_ck, abe_24m_fclk,
+	     CLOCK_CLKSEL_INIT(dmic_sync_mux_sel,
+			       CM1_ABE_DMIC_CLKCTRL, CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
-	{ .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(func_dmic_abe_gfclk_sel,
+	       dmic_sync_mux_ck, pad_clks_ck, slimbus_clk);
 
 /* Merged func_dmic_abe_gfclk into dmic */
-static struct clk dmic_fck = {
-	.name		= "dmic_fck",
-	.parent		= &dmic_sync_mux_ck,
-	.clksel		= func_dmic_abe_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(dmic_fck, dmic_sync_mux_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(func_dmic_abe_gfclk_sel,
+				     CM1_ABE_DMIC, CLKSEL_SOURCE));
 
-static struct clk dsp_fck = {
-	.name		= "dsp_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_TESLA_TESLA_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "tesla_clkdm",
-	.parent		= &dpll_iva_m4x2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dsp_fck, dpll_iva_m4x2_ck, tesla_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_TESLA_TESLA));
 
-static struct clk dss_sys_clk = {
-	.name		= "dss_sys_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &syc_clk_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dss_sys_clk, syc_clk_div_ck, l3_dss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_SYS_CLK));
 
-static struct clk dss_tv_clk = {
-	.name		= "dss_tv_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &extalt_clkin_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dss_tv_clk, extalt_clkin_ck, l3_dss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_TV_CLK));
 
-static struct clk dss_dss_clk = {
-	.name		= "dss_dss_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &dpll_per_m5x2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dss_dss_clk, dpll_per_m5x2_ck, l3_dss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_DSSCLK));
 
-static struct clk dss_48mhz_clk = {
-	.name		= "dss_48mhz_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &func_48mc_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dss_48mhz_clk, func_48mc_fclk, l3_dss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_DSS_DSS, OPTFCLKEN_48MHZ_CLK));
 
-static struct clk dss_fck = {
-	.name		= "dss_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DSS_DSS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_dss_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(dss_fck, l3_div_ck, l3_dss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_DSS_DSS));
 
-static struct clk efuse_ctrl_cust_fck = {
-	.name		= "efuse_ctrl_cust_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_cefuse_clkdm",
-	.parent		= &sys_clkin_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(efuse_ctrl_cust_fck, sys_clkin_ck, l4_cefuse_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_CEFUSE_CEFUSE));
 
-static struct clk emif1_fck = {
-	.name		= "emif1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.flags		= ENABLE_ON_INIT,
-	.clkdm_name	= "l3_emif_clkdm",
-	.parent		= &ddrphy_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(emif1_fck, ddrphy_ck, l3_emif_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_MEMIF_EMIF_1),
+		CLOCK_FLAGS_ENABLE());
 
-static struct clk emif2_fck = {
-	.name		= "emif2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.flags		= ENABLE_ON_INIT,
-	.clkdm_name	= "l3_emif_clkdm",
-	.parent		= &ddrphy_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(emif2_fck, ddrphy_ck, l3_emif_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_MEMIF_EMIF_2),
+		CLOCK_FLAGS_ENABLE());
 
-static const struct clksel fdif_fclk_div[] = {
-	{ .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(fdif_fclk_div, dpll_per_m4x2_ck, div3_1to4_rates);
 
 /* Merged fdif_fclk into fdif */
 static struct clk fdif_fck = {
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [PATCHv2 2/2] [RFC] OMAP4: clock data: shrink more clock data.
  2011-05-15 21:45 ` Vladimir Zapolskiy
@ 2011-05-15 21:45   ` Vladimir Zapolskiy
  -1 siblings, 0 replies; 16+ messages in thread
From: Vladimir Zapolskiy @ 2011-05-15 21:45 UTC (permalink / raw)
  To: Tony Lindgren, Benoit Cousson
  Cc: linux-omap, linux-arm-kernel, Vladimir Zapolskiy

This mass change continues the reduction of homogeneous data chunks
along clock definitions. No semantical difference is added in the
change.

Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com>
---
 arch/arm/mach-omap2/clock44xx_data.c | 1675 ++++++++--------------------------
 1 files changed, 378 insertions(+), 1297 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 423f180..ccbc29e 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -846,1395 +846,524 @@ DEFINE_CLOCK_DM(emif2_fck, ddrphy_ck, l3_emif_clkdm,
 DEFINE_CLKSEL(fdif_fclk_div, dpll_per_m4x2_ck, div3_1to4_rates);
 
 /* Merged fdif_fclk into fdif */
-static struct clk fdif_fck = {
-	.name		= "fdif_fck",
-	.parent		= &dpll_per_m4x2_ck,
-	.clksel		= fdif_fclk_div,
-	.clksel_reg	= OMAP4430_CM_CAM_FDIF_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_FCLK_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-	.enable_reg	= OMAP4430_CM_CAM_FDIF_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "iss_clkdm",
-};
+DEFINE_CLOCK_DM(fdif_fck, dpll_per_m4x2_ck, iss_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_CAM_FDIF),
+		CLOCK_CLKSEL(fdif_fclk_div, CM_CAM_FDIF_CLKCTRL, CLKSEL_FCLK));
 
-static struct clk fpka_fck = {
-	.name		= "fpka_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(fpka_fck, l4_div_ck, l4_secure_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4SEC_PKAEIP29));
 
-static struct clk gpio1_dbclk = {
-	.name		= "gpio1_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio1_dbclk, sys_32k_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_WKUP_GPIO1, OPTFCLKEN_DBCLK));
 
-static struct clk gpio1_ick = {
-	.name		= "gpio1_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio1_ick, l4_wkup_clk_mux_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_WKUP_GPIO1));
 
-static struct clk gpio2_dbclk = {
-	.name		= "gpio2_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio2_dbclk, sys_32k_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4PER_GPIO2, OPTFCLKEN_DBCLK));
 
-static struct clk gpio2_ick = {
-	.name		= "gpio2_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio2_ick, l4_div_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L4PER_GPIO2));
 
-static struct clk gpio3_dbclk = {
-	.name		= "gpio3_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio3_dbclk, sys_32k_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4PER_GPIO3, OPTFCLKEN_DBCLK));
 
-static struct clk gpio3_ick = {
-	.name		= "gpio3_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio3_ick, l4_div_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L4PER_GPIO3));
 
-static struct clk gpio4_dbclk = {
-	.name		= "gpio4_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio4_dbclk, sys_32k_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4PER_GPIO4, OPTFCLKEN_DBCLK));
 
-static struct clk gpio4_ick = {
-	.name		= "gpio4_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio4_ick, l4_div_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L4PER_GPIO4));
 
-static struct clk gpio5_dbclk = {
-	.name		= "gpio5_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio5_dbclk, sys_32k_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4PER_GPIO5, OPTFCLKEN_DBCLK));
 
-static struct clk gpio5_ick = {
-	.name		= "gpio5_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio5_ick, l4_div_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L4PER_GPIO5));
 
-static struct clk gpio6_dbclk = {
-	.name		= "gpio6_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio6_dbclk, sys_32k_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4PER_GPIO6, OPTFCLKEN_DBCLK));
 
-static struct clk gpio6_ick = {
-	.name		= "gpio6_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio6_ick, l4_div_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L4PER_GPIO6));
 
-static struct clk gpmc_ick = {
-	.name		= "gpmc_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3_2_GPMC_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_2_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpmc_ick, l3_div_ck, l3_2_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L3_2_GPMC));
 
-static const struct clksel sgx_clk_mux_sel[] = {
-	{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(sgx_clk_mux_sel, dpll_core_m7x2_ck, dpll_per_m7x2_ck);
 
 /* Merged sgx_clk_mux into gpu */
-static struct clk gpu_fck = {
-	.name		= "gpu_fck",
-	.parent		= &dpll_core_m7x2_ck,
-	.clksel		= sgx_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_GFX_GFX_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SGX_FCLK_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_GFX_GFX_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_gfx_clkdm",
-};
+DEFINE_CLOCK_DM(gpu_fck, dpll_core_m7x2_ck, l3_gfx_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_GFX_GFX),
+		CLOCK_CLKSEL0(sgx_clk_mux_sel,
+			      CM_GFX_GFX_CLKCTRL, CLKSEL_SGX_FCLK));
 
-static struct clk hdq1w_fck = {
-	.name		= "hdq1w_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_12m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(hdq1w_fck, func_12m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_HDQ1W));
 
-static const struct clksel hsi_fclk_div[] = {
-	{ .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(hsi_fclk_div, dpll_per_m2x2_ck, div3_1to4_rates);
 
 /* Merged hsi_fclk into hsi */
-static struct clk hsi_fck = {
-	.name		= "hsi_fck",
-	.parent		= &dpll_per_m2x2_ck,
-	.clksel		= hsi_fclk_div,
-	.clksel_reg	= OMAP4430_CM_L3INIT_HSI_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_24_25_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-	.enable_reg	= OMAP4430_CM_L3INIT_HSI_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-};
+DEFINE_CLOCK_DM(hsi_fck, dpll_per_m2x2_ck, l3_init_clkdm,
+		CLOCK_OPS_DFLT_HW(CM_L3INIT_HSI),
+		CLOCK_CLKSEL(hsi_fclk_div,
+			     CM_L3INIT_HSI_CLKCTRL, CLKSEL_24_25));
 
-static struct clk i2c1_fck = {
-	.name		= "i2c1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(i2c1_fck, func_96m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_I2C1));
 
-static struct clk i2c2_fck = {
-	.name		= "i2c2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(i2c2_fck, func_96m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_I2C2));
 
-static struct clk i2c3_fck = {
-	.name		= "i2c3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(i2c3_fck, func_96m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_I2C3));
 
-static struct clk i2c4_fck = {
-	.name		= "i2c4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(i2c4_fck, func_96m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_I2C4));
 
-static struct clk ipu_fck = {
-	.name		= "ipu_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "ducati_clkdm",
-	.parent		= &ducati_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(ipu_fck, ducati_clk_mux_ck, ducati_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_DUCATI_DUCATI));
 
-static struct clk iss_ctrlclk = {
-	.name		= "iss_ctrlclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_CAM_ISS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
-	.clkdm_name	= "iss_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(iss_ctrlclk, func_96m_fclk, iss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_CAM_ISS, OPTFCLKEN_CTRLCLK));
 
-static struct clk iss_fck = {
-	.name		= "iss_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_CAM_ISS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "iss_clkdm",
-	.parent		= &ducati_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(iss_fck, ducati_clk_mux_ck, iss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_CAM_ISS));
 
-static struct clk iva_fck = {
-	.name		= "iva_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5x2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(iva_fck, dpll_iva_m5x2_ck, ivahd_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_IVAHD_IVAHD));
 
-static struct clk kbd_fck = {
-	.name		= "kbd_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(kbd_fck, sys_32k_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_WKUP_KEYBOARD));
 
-static struct clk l3_instr_ick = {
-	.name		= "l3_instr_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_instr_clkdm",
-	.flags		= ENABLE_ON_INIT,
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(l3_instr_ick, l3_div_ck, l3_instr_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L3INSTR_L3_INSTR),
+		CLOCK_FLAGS_ENABLE());
 
-static struct clk l3_main_3_ick = {
-	.name		= "l3_main_3_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_instr_clkdm",
-	.flags		= ENABLE_ON_INIT,
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(l3_main_3_ick, l3_div_ck, l3_instr_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L3INSTR_L3_3),
+		CLOCK_FLAGS_ENABLE());
 
-static struct clk mcasp_sync_mux_ck = {
-	.name		= "mcasp_sync_mux_ck",
-	.parent		= &abe_24m_fclk,
-	.clksel		= dmic_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(mcasp_sync_mux_ck, abe_24m_fclk,
+	     CLOCK_CLKSEL_INIT(dmic_sync_mux_sel,
+			       CM1_ABE_MCASP_CLKCTRL, CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
-	{ .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(func_mcasp_abe_gfclk_sel,
+	       mcasp_sync_mux_ck, pad_clks_ck, slimbus_clk);
 
 /* Merged func_mcasp_abe_gfclk into mcasp */
-static struct clk mcasp_fck = {
-	.name		= "mcasp_fck",
-	.parent		= &mcasp_sync_mux_ck,
-	.clksel		= func_mcasp_abe_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(mcasp_fck, mcasp_sync_mux_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(func_mcasp_abe_gfclk_sel,
+				     CM1_ABE_MCASP, CLKSEL_SOURCE));
 
-static struct clk mcbsp1_sync_mux_ck = {
-	.name		= "mcbsp1_sync_mux_ck",
-	.parent		= &abe_24m_fclk,
-	.clksel		= dmic_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(mcbsp1_sync_mux_ck, abe_24m_fclk,
+	     CLOCK_CLKSEL_INIT(dmic_sync_mux_sel,
+			       CM1_ABE_MCBSP1_CLKCTRL, CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
-	{ .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(func_mcbsp1_gfclk_sel,
+	       mcbsp1_sync_mux_ck, pad_clks_ck, slimbus_clk);
 
 /* Merged func_mcbsp1_gfclk into mcbsp1 */
-static struct clk mcbsp1_fck = {
-	.name		= "mcbsp1_fck",
-	.parent		= &mcbsp1_sync_mux_ck,
-	.clksel		= func_mcbsp1_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(mcbsp1_fck, mcbsp1_sync_mux_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(func_mcbsp1_gfclk_sel,
+				     CM1_ABE_MCBSP1, CLKSEL_SOURCE));
 
-static struct clk mcbsp2_sync_mux_ck = {
-	.name		= "mcbsp2_sync_mux_ck",
-	.parent		= &abe_24m_fclk,
-	.clksel		= dmic_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(mcbsp2_sync_mux_ck, abe_24m_fclk,
+	     CLOCK_CLKSEL_INIT(dmic_sync_mux_sel,
+			       CM1_ABE_MCBSP2_CLKCTRL, CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
-	{ .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(func_mcbsp2_gfclk_sel,
+	       mcbsp2_sync_mux_ck, pad_clks_ck, slimbus_clk);
 
 /* Merged func_mcbsp2_gfclk into mcbsp2 */
-static struct clk mcbsp2_fck = {
-	.name		= "mcbsp2_fck",
-	.parent		= &mcbsp2_sync_mux_ck,
-	.clksel		= func_mcbsp2_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(mcbsp2_fck, mcbsp2_sync_mux_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(func_mcbsp2_gfclk_sel,
+				     CM1_ABE_MCBSP2, CLKSEL_SOURCE));
 
-static struct clk mcbsp3_sync_mux_ck = {
-	.name		= "mcbsp3_sync_mux_ck",
-	.parent		= &abe_24m_fclk,
-	.clksel		= dmic_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(mcbsp3_sync_mux_ck, abe_24m_fclk,
+	     CLOCK_CLKSEL_INIT(dmic_sync_mux_sel,
+			       CM1_ABE_MCBSP3_CLKCTRL, CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
-	{ .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(func_mcbsp3_gfclk_sel,
+	       mcbsp3_sync_mux_ck, pad_clks_ck, slimbus_clk);
 
 /* Merged func_mcbsp3_gfclk into mcbsp3 */
-static struct clk mcbsp3_fck = {
-	.name		= "mcbsp3_fck",
-	.parent		= &mcbsp3_sync_mux_ck,
-	.clksel		= func_mcbsp3_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(mcbsp3_fck, mcbsp3_sync_mux_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(func_mcbsp3_gfclk_sel,
+				     CM1_ABE_MCBSP3, CLKSEL_SOURCE));
 
-static struct clk mcbsp4_sync_mux_ck = {
-	.name		= "mcbsp4_sync_mux_ck",
-	.parent		= &func_96m_fclk,
-	.clksel		= mcasp2_fclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(mcbsp4_sync_mux_ck, func_96m_fclk,
+	     CLOCK_CLKSEL_INIT(mcasp2_fclk_sel,
+			       CM_L4PER_MCBSP4_CLKCTRL,
+			       CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
-	{ .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(per_mcbsp4_gfclk_sel, mcbsp4_sync_mux_ck, pad_clks_ck);
 
 /* Merged per_mcbsp4_gfclk into mcbsp4 */
-static struct clk mcbsp4_fck = {
-	.name		= "mcbsp4_fck",
-	.parent		= &mcbsp4_sync_mux_ck,
-	.clksel		= per_mcbsp4_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_24_24_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(mcbsp4_fck, mcbsp4_sync_mux_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(per_mcbsp4_gfclk_sel,
+				     CM_L4PER_MCBSP4, CLKSEL_SOURCE_24_24));
 
-static struct clk mcpdm_fck = {
-	.name		= "mcpdm_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_PDM_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &pad_clks_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mcpdm_fck, pad_clks_ck, abe_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM1_ABE_PDM));
 
-static struct clk mcspi1_fck = {
-	.name		= "mcspi1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mcspi1_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MCSPI1));
 
-static struct clk mcspi2_fck = {
-	.name		= "mcspi2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mcspi2_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MCSPI2));
 
-static struct clk mcspi3_fck = {
-	.name		= "mcspi3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mcspi3_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MCSPI3));
 
-static struct clk mcspi4_fck = {
-	.name		= "mcspi4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mcspi4_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MCSPI4));
 
 /* Merged hsmmc1_fclk into mmc1 */
-static struct clk mmc1_fck = {
-	.name		= "mmc1_fck",
-	.parent		= &func_64m_fclk,
-	.clksel		= hsmmc6_fclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-};
+DEFINE_CLOCK_DM(mmc1_fck, func_64m_fclk, l3_init_clkdm,
+		CLOCK_CLKSEL_INIT_SW(hsmmc6_fclk_sel, CM_L3INIT_MMC1, CLKSEL));
 
 /* Merged hsmmc2_fclk into mmc2 */
-static struct clk mmc2_fck = {
-	.name		= "mmc2_fck",
-	.parent		= &func_64m_fclk,
-	.clksel		= hsmmc6_fclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-};
+DEFINE_CLOCK_DM(mmc2_fck, func_64m_fclk, l3_init_clkdm,
+		CLOCK_CLKSEL_INIT_SW(hsmmc6_fclk_sel, CM_L3INIT_MMC2, CLKSEL));
 
-static struct clk mmc3_fck = {
-	.name		= "mmc3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mmc3_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MMCSD3),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk mmc4_fck = {
-	.name		= "mmc4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mmc4_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MMCSD4),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk mmc5_fck = {
-	.name		= "mmc5_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mmc5_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MMCSD5),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk ocp2scp_usb_phy_phy_48m = {
-	.name		= "ocp2scp_usb_phy_phy_48m",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(ocp2scp_usb_phy_phy_48m, func_48m_fclk, l3_init_clkdm,
+		CLOCK_OPS_DFLT(CM_L3INIT_USBPHYOCP2SCP, OPTFCLKEN_PHY_48M),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk ocp2scp_usb_phy_ick = {
-	.name		= "ocp2scp_usb_phy_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(ocp2scp_usb_phy_ick, l4_div_ck, l3_init_clkdm,
+		CLOCK_OPS_DFLT_HW(CM_L3INIT_USBPHYOCP2SCP),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk ocp_wp_noc_ick = {
-	.name		= "ocp_wp_noc_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_instr_clkdm",
-	.flags		= ENABLE_ON_INIT,
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(ocp_wp_noc_ick, l3_div_ck, l3_instr_clkdm,
+		CLOCK_OPS_DFLT_HW(CM_L3INSTR_OCP_WP1),
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_FLAGS_ENABLE());
 
-static struct clk rng_ick = {
-	.name		= "rng_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_RNG_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(rng_ick, l4_div_ck, l4_secure_clkdm,
+		CLOCK_OPS_DFLT_HW(CM_L4SEC_RNG),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk sha2md5_fck = {
-	.name		= "sha2md5_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(sha2md5_fck, l3_div_ck, l4_secure_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_L4SEC_SHA2MD51),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk sl2if_ick = {
-	.name		= "sl2if_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_IVAHD_SL2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5x2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(sl2if_ick, dpll_iva_m5x2_ck, ivahd_clkdm,
+		CLOCK_OPS_DFLT_HW(CM_IVAHD_SL2),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus1_fclk_1 = {
-	.name		= "slimbus1_fclk_1",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &func_24m_clk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus1_fclk_0, abe_24m_fclk, abe_clkdm,
+		CLOCK_OPS_DFLT(CM1_ABE_SLIMBUS, OPTFCLKEN_FCLK0),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus1_fclk_0 = {
-	.name		= "slimbus1_fclk_0",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &abe_24m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus1_fclk_1, func_24m_clk, abe_clkdm,
+		CLOCK_OPS_DFLT(CM1_ABE_SLIMBUS, OPTFCLKEN_FCLK1),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus1_fclk_2 = {
-	.name		= "slimbus1_fclk_2",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &pad_clks_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus1_fclk_2, pad_clks_ck, abe_clkdm,
+		CLOCK_OPS_DFLT(CM1_ABE_SLIMBUS, OPTFCLKEN_FCLK2),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus1_slimbus_clk = {
-	.name		= "slimbus1_slimbus_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &slimbus_clk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus1_slimbus_clk, slimbus_clk, abe_clkdm,
+		CLOCK_OPS_DFLT(CM1_ABE_SLIMBUS, OPTFCLKEN_SLIMBUS_CLK_11_11),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus1_fck = {
-	.name		= "slimbus1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &ocp_abe_iclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus1_fck, ocp_abe_iclk, abe_clkdm,
+		CLOCK_OPS_DFLT_SW(CM1_ABE_SLIMBUS),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus2_fclk_1 = {
-	.name		= "slimbus2_fclk_1",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &per_abe_24m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus2_fclk_1, per_abe_24m_fclk, l4_per_clkdm,
+		CLOCK_OPS_DFLT(CM_L4PER_SLIMBUS2, OPTFCLKEN_PERABE24M_GFCLK),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus2_fclk_0 = {
-	.name		= "slimbus2_fclk_0",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_24mc_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus2_fclk_0, func_24mc_fclk, l4_per_clkdm,
+		CLOCK_OPS_DFLT(CM_L4PER_SLIMBUS2, OPTFCLKEN_PER24MC_GFCLK),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus2_slimbus_clk = {
-	.name		= "slimbus2_slimbus_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &pad_slimbus_core_clks_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus2_slimbus_clk, pad_slimbus_core_clks_ck, l4_per_clkdm,
+		CLOCK_OPS_DFLT(CM_L4PER_SLIMBUS2, OPTFCLKEN_SLIMBUS_CLK),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus2_fck = {
-	.name		= "slimbus2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus2_fck, l4_div_ck, l4_per_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_L4PER_SLIMBUS2),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk smartreflex_core_fck = {
-	.name		= "smartreflex_core_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(smartreflex_core_fck, l4_wkup_clk_mux_ck, l4_ao_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_ALWON_SR_CORE),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk smartreflex_iva_fck = {
-	.name		= "smartreflex_iva_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(smartreflex_iva_fck, l4_wkup_clk_mux_ck, l4_ao_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_ALWON_SR_IVA),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk smartreflex_mpu_fck = {
-	.name		= "smartreflex_mpu_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(smartreflex_mpu_fck, l4_wkup_clk_mux_ck, l4_ao_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_ALWON_SR_MPU),
+		CLOCK_RECALC_FOLLOWPARENT());
 
 /* Merged dmt1_clk_mux into timer1 */
-static struct clk timer1_fck = {
-	.name		= "timer1_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-};
+DEFINE_CLOCK_DM(timer1_fck, sys_clkin_ck, l4_wkup_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_WKUP_TIMER1, CLKSEL));
 
 /* Merged cm2_dm10_mux into timer10 */
-static struct clk timer10_fck = {
-	.name		= "timer10_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer10_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER10, CLKSEL));
 
 /* Merged cm2_dm11_mux into timer11 */
-static struct clk timer11_fck = {
-	.name		= "timer11_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer11_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER11, CLKSEL));
 
 /* Merged cm2_dm2_mux into timer2 */
-static struct clk timer2_fck = {
-	.name		= "timer2_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer2_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER2, CLKSEL));
 
 /* Merged cm2_dm3_mux into timer3 */
-static struct clk timer3_fck = {
-	.name		= "timer3_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer3_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER3, CLKSEL));
 
 /* Merged cm2_dm4_mux into timer4 */
-static struct clk timer4_fck = {
-	.name		= "timer4_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer4_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER4, CLKSEL));
 
-static const struct clksel timer5_sync_mux_sel[] = {
-	{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(timer5_sync_mux_sel, syc_clk_div_ck, sys_32k_ck);
 
 /* Merged timer5_sync_mux into timer5 */
-static struct clk timer5_fck = {
-	.name		= "timer5_fck",
-	.parent		= &syc_clk_div_ck,
-	.clksel		= timer5_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(timer5_fck, syc_clk_div_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(timer5_sync_mux_sel,
+				     CM1_ABE_TIMER5, CLKSEL));
 
 /* Merged timer6_sync_mux into timer6 */
-static struct clk timer6_fck = {
-	.name		= "timer6_fck",
-	.parent		= &syc_clk_div_ck,
-	.clksel		= timer5_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(timer6_fck, syc_clk_div_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(timer5_sync_mux_sel,
+				     CM1_ABE_TIMER6, CLKSEL));
 
 /* Merged timer7_sync_mux into timer7 */
-static struct clk timer7_fck = {
-	.name		= "timer7_fck",
-	.parent		= &syc_clk_div_ck,
-	.clksel		= timer5_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(timer7_fck, syc_clk_div_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(timer5_sync_mux_sel,
+				     CM1_ABE_TIMER7, CLKSEL));
 
 /* Merged timer8_sync_mux into timer8 */
-static struct clk timer8_fck = {
-	.name		= "timer8_fck",
-	.parent		= &syc_clk_div_ck,
-	.clksel		= timer5_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(timer8_fck, syc_clk_div_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(timer5_sync_mux_sel,
+				     CM1_ABE_TIMER8, CLKSEL));
 
 /* Merged cm2_dm9_mux into timer9 */
-static struct clk timer9_fck = {
-	.name		= "timer9_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer9_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER9, CLKSEL));
 
-static struct clk uart1_fck = {
-	.name		= "uart1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(uart1_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_UART1));
 
-static struct clk uart2_fck = {
-	.name		= "uart2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(uart2_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_UART2));
 
-static struct clk uart3_fck = {
-	.name		= "uart3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(uart3_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_UART3));
 
-static struct clk uart4_fck = {
-	.name		= "uart4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(uart4_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_UART4));
 
-static struct clk usb_host_fs_fck = {
-	.name		= "usb_host_fs_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &func_48mc_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_fs_fck, func_48mc_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L3INIT_USB_HOST_FS));
 
-static const struct clksel utmi_p1_gfclk_sel[] = {
-	{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
-	{ .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(utmi_p1_gfclk_sel, init_60m_fclk, xclk60mhsp1_ck);
 
-static struct clk utmi_p1_gfclk = {
-	.name		= "utmi_p1_gfclk",
-	.parent		= &init_60m_fclk,
-	.clksel		= utmi_p1_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_UTMI_P1_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(utmi_p1_gfclk, init_60m_fclk,
+	     CLOCK_CLKSEL_INIT(utmi_p1_gfclk_sel,
+			       CM_L3INIT_USB_HOST_CLKCTRL, CLKSEL_UTMI_P1));
 
-static struct clk usb_host_hs_utmi_p1_clk = {
-	.name		= "usb_host_hs_utmi_p1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &utmi_p1_gfclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_utmi_p1_clk, utmi_p1_gfclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_UTMI_P1_CLK));
 
-static const struct clksel utmi_p2_gfclk_sel[] = {
-	{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
-	{ .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(utmi_p2_gfclk_sel, init_60m_fclk, xclk60mhsp2_ck);
 
-static struct clk utmi_p2_gfclk = {
-	.name		= "utmi_p2_gfclk",
-	.parent		= &init_60m_fclk,
-	.clksel		= utmi_p2_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_UTMI_P2_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(utmi_p2_gfclk, init_60m_fclk,
+	     CLOCK_CLKSEL_INIT(utmi_p2_gfclk_sel,
+			       CM_L3INIT_USB_HOST_CLKCTRL, CLKSEL_UTMI_P2));
 
-static struct clk usb_host_hs_utmi_p2_clk = {
-	.name		= "usb_host_hs_utmi_p2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &utmi_p2_gfclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_utmi_p2_clk, utmi_p2_gfclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_UTMI_P2_CLK));
 
-static struct clk usb_host_hs_utmi_p3_clk = {
-	.name		= "usb_host_hs_utmi_p3_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_utmi_p3_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_UTMI_P3_CLK));
 
-static struct clk usb_host_hs_hsic480m_p1_clk = {
-	.name		= "usb_host_hs_hsic480m_p1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &dpll_usb_m2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_hsic60m_p1_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_HSIC60M_P1_CLK));
 
-static struct clk usb_host_hs_hsic60m_p1_clk = {
-	.name		= "usb_host_hs_hsic60m_p1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_hsic60m_p2_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_HSIC60M_P2_CLK));
 
-static struct clk usb_host_hs_hsic60m_p2_clk = {
-	.name		= "usb_host_hs_hsic60m_p2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_hsic480m_p1_clk, dpll_usb_m2_ck, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_HSIC480M_P1_CLK));
 
-static struct clk usb_host_hs_hsic480m_p2_clk = {
-	.name		= "usb_host_hs_hsic480m_p2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &dpll_usb_m2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_hsic480m_p2_clk, dpll_usb_m2_ck, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_HSIC480M_P2_CLK));
 
-static struct clk usb_host_hs_func48mclk = {
-	.name		= "usb_host_hs_func48mclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &func_48mc_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_func48mclk, func_48mc_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_FUNC48MCLK));
 
-static struct clk usb_host_hs_fck = {
-	.name		= "usb_host_hs_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_fck, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L3INIT_USB_HOST));
 
-static const struct clksel otg_60m_gfclk_sel[] = {
-	{ .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
-	{ .parent = &xclk60motg_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(otg_60m_gfclk_sel, utmi_phy_clkout_ck, xclk60motg_ck);
 
-static struct clk otg_60m_gfclk = {
-	.name		= "otg_60m_gfclk",
-	.parent		= &utmi_phy_clkout_ck,
-	.clksel		= otg_60m_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_60M_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(otg_60m_gfclk, utmi_phy_clkout_ck,
+	     CLOCK_CLKSEL_INIT(otg_60m_gfclk_sel,
+			       CM_L3INIT_USB_OTG_CLKCTRL, CLKSEL_60M));
 
-static struct clk usb_otg_hs_xclk = {
-	.name		= "usb_otg_hs_xclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_XCLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &otg_60m_gfclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_otg_hs_xclk, otg_60m_gfclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_OTG, OPTFCLKEN_XCLK));
 
-static struct clk usb_otg_hs_ick = {
-	.name		= "usb_otg_hs_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_otg_hs_ick, l3_div_ck, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L3INIT_USB_OTG));
 
-static struct clk usb_phy_cm_clk32k = {
-	.name		= "usb_phy_cm_clk32k",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_phy_cm_clk32k, sys_32k_ck, l4_ao_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_ALWON_USBPHY, OPTFCLKEN_CLK32K));
 
-static struct clk usb_tll_hs_usb_ch2_clk = {
-	.name		= "usb_tll_hs_usb_ch2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_tll_hs_usb_ch0_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_TLL, OPTFCLKEN_USB_CH0_CLK));
 
-static struct clk usb_tll_hs_usb_ch0_clk = {
-	.name		= "usb_tll_hs_usb_ch0_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_tll_hs_usb_ch1_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_TLL, OPTFCLKEN_USB_CH1_CLK));
 
-static struct clk usb_tll_hs_usb_ch1_clk = {
-	.name		= "usb_tll_hs_usb_ch1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_tll_hs_usb_ch2_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_TLL, OPTFCLKEN_USB_CH2_CLK));
 
-static struct clk usb_tll_hs_ick = {
-	.name		= "usb_tll_hs_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
 
-static const struct clksel_rate div2_14to18_rates[] = {
-	{ .div = 14, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 18, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_CLOCK_DM(usb_tll_hs_ick, l4_div_ck, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L3INIT_USB_TLL));
 
-static const struct clksel usim_fclk_div[] = {
-	{ .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL_RATE2(14to18, 14, 18);
 
-static struct clk usim_ck = {
-	.name		= "usim_ck",
-	.parent		= &dpll_per_m4x2_ck,
-	.clksel		= usim_fclk_div,
-	.clksel_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_DIV_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLKSEL(usim_fclk_div, dpll_per_m4x2_ck, div2_14to18_rates);
 
-static struct clk usim_fclk = {
-	.name		= "usim_fclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK_SHIFT,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &usim_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(usim_ck, dpll_per_m4x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(usim_fclk_div, CM_WKUP_USIM_CLKCTRL, CLKSEL_DIV));
 
-static struct clk usim_fck = {
-	.name		= "usim_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usim_fclk, usim_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_WKUP_USIM, OPTFCLKEN_FCLK));
 
-static struct clk wd_timer2_fck = {
-	.name		= "wd_timer2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_WDT2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usim_fck, sys_32k_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_WKUP_USIM));
 
-static struct clk wd_timer3_fck = {
-	.name		= "wd_timer3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_WDT3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(wd_timer2_fck, sys_32k_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_WKUP_WDT2));
+
+DEFINE_CLOCK_DM(wd_timer3_fck, sys_32k_ck, abe_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM1_ABE_WDT3));
 
 /* Remaining optional clocks */
-static const struct clksel stm_clk_div_div[] = {
-	{ .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
 
-static struct clk stm_clk_div_ck = {
-	.name		= "stm_clk_div_ck",
-	.parent		= &pmd_stm_clock_mux_ck,
-	.clksel		= stm_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLKSEL(stm_clk_div_div, pmd_stm_clock_mux_ck, div3_1to4_rates);
 
-static const struct clksel trace_clk_div_div[] = {
-	{ .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(stm_clk_div_ck, pmd_stm_clock_mux_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(stm_clk_div_div,
+			  CM_EMU_DEBUGSS_CLKCTRL, CLKSEL_PMD_STM_CLK));
 
-static struct clk trace_clk_div_ck = {
-	.name		= "trace_clk_div_ck",
-	.parent		= &pmd_trace_clk_mux_ck,
-	.clksel		= trace_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLKSEL(trace_clk_div_div, pmd_trace_clk_mux_ck, div3_1to4_rates);
+
+DEFINE_CLOCK(trace_clk_div_ck, pmd_trace_clk_mux_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(trace_clk_div_div,
+			  CM_EMU_DEBUGSS_CLKCTRL, CLKSEL_PMD_TRACE_CLK));
 
 /* SCRM aux clk nodes */
 
-static const struct clksel auxclk_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
-	{ .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(auxclk_sel,
+	       sys_clkin_ck, dpll_core_m3x2_ck, dpll_per_m3x2_ck);
 
-static struct clk auxclk0_ck = {
-	.name		= "auxclk0_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK0,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK0,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
+DEFINE_CLOCK(auxclk0_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK0),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK0, SRCSELECT));
 
-static struct clk auxclk1_ck = {
-	.name		= "auxclk1_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK1,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK1,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
+DEFINE_CLOCK(auxclk1_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK1),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK1, SRCSELECT));
 
-static struct clk auxclk2_ck = {
-	.name		= "auxclk2_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK2,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK2,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
-static struct clk auxclk3_ck = {
-	.name		= "auxclk3_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK3,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK3,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
+DEFINE_CLOCK(auxclk2_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK2),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK2, SRCSELECT));
 
-static struct clk auxclk4_ck = {
-	.name		= "auxclk4_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK4,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK4,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
+DEFINE_CLOCK(auxclk3_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK3),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK3, SRCSELECT));
 
-static struct clk auxclk5_ck = {
-	.name		= "auxclk5_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK5,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK5,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
+DEFINE_CLOCK(auxclk4_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK4),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK4, SRCSELECT));
+
+DEFINE_CLOCK(auxclk5_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK5),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK5, SRCSELECT));
 
 static const struct clksel auxclkreq_sel[] = {
 	{ .parent = &auxclk0_ck, .rates = div_1_0_rates },
@@ -2246,71 +1375,23 @@ static const struct clksel auxclkreq_sel[] = {
 	{ .parent = NULL },
 };
 
-static struct clk auxclkreq0_ck = {
-	.name		= "auxclkreq0_ck",
-	.parent		= &auxclk0_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ0,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq0_ck, auxclk0_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ0, MAPPING));
 
-static struct clk auxclkreq1_ck = {
-	.name		= "auxclkreq1_ck",
-	.parent		= &auxclk1_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ1,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq1_ck, auxclk1_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ1, MAPPING));
 
-static struct clk auxclkreq2_ck = {
-	.name		= "auxclkreq2_ck",
-	.parent		= &auxclk2_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ2,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq2_ck, auxclk2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ2, MAPPING));
 
-static struct clk auxclkreq3_ck = {
-	.name		= "auxclkreq3_ck",
-	.parent		= &auxclk3_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ3,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq3_ck, auxclk3_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ3, MAPPING));
 
-static struct clk auxclkreq4_ck = {
-	.name		= "auxclkreq4_ck",
-	.parent		= &auxclk4_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ4,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq4_ck, auxclk4_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ4, MAPPING));
 
-static struct clk auxclkreq5_ck = {
-	.name		= "auxclkreq5_ck",
-	.parent		= &auxclk5_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ5,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq5_ck, auxclk5_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ5, MAPPING));
 
 /*
  * clkdev
-- 
1.7.2.3


^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [PATCHv2 2/2] [RFC] OMAP4: clock data: shrink more clock data.
@ 2011-05-15 21:45   ` Vladimir Zapolskiy
  0 siblings, 0 replies; 16+ messages in thread
From: Vladimir Zapolskiy @ 2011-05-15 21:45 UTC (permalink / raw)
  To: linux-arm-kernel

This mass change continues the reduction of homogeneous data chunks
along clock definitions. No semantical difference is added in the
change.

Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com>
---
 arch/arm/mach-omap2/clock44xx_data.c | 1675 ++++++++--------------------------
 1 files changed, 378 insertions(+), 1297 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 423f180..ccbc29e 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -846,1395 +846,524 @@ DEFINE_CLOCK_DM(emif2_fck, ddrphy_ck, l3_emif_clkdm,
 DEFINE_CLKSEL(fdif_fclk_div, dpll_per_m4x2_ck, div3_1to4_rates);
 
 /* Merged fdif_fclk into fdif */
-static struct clk fdif_fck = {
-	.name		= "fdif_fck",
-	.parent		= &dpll_per_m4x2_ck,
-	.clksel		= fdif_fclk_div,
-	.clksel_reg	= OMAP4430_CM_CAM_FDIF_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_FCLK_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-	.enable_reg	= OMAP4430_CM_CAM_FDIF_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "iss_clkdm",
-};
+DEFINE_CLOCK_DM(fdif_fck, dpll_per_m4x2_ck, iss_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_CAM_FDIF),
+		CLOCK_CLKSEL(fdif_fclk_div, CM_CAM_FDIF_CLKCTRL, CLKSEL_FCLK));
 
-static struct clk fpka_fck = {
-	.name		= "fpka_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(fpka_fck, l4_div_ck, l4_secure_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4SEC_PKAEIP29));
 
-static struct clk gpio1_dbclk = {
-	.name		= "gpio1_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio1_dbclk, sys_32k_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_WKUP_GPIO1, OPTFCLKEN_DBCLK));
 
-static struct clk gpio1_ick = {
-	.name		= "gpio1_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio1_ick, l4_wkup_clk_mux_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_WKUP_GPIO1));
 
-static struct clk gpio2_dbclk = {
-	.name		= "gpio2_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio2_dbclk, sys_32k_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4PER_GPIO2, OPTFCLKEN_DBCLK));
 
-static struct clk gpio2_ick = {
-	.name		= "gpio2_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio2_ick, l4_div_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L4PER_GPIO2));
 
-static struct clk gpio3_dbclk = {
-	.name		= "gpio3_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio3_dbclk, sys_32k_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4PER_GPIO3, OPTFCLKEN_DBCLK));
 
-static struct clk gpio3_ick = {
-	.name		= "gpio3_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio3_ick, l4_div_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L4PER_GPIO3));
 
-static struct clk gpio4_dbclk = {
-	.name		= "gpio4_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio4_dbclk, sys_32k_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4PER_GPIO4, OPTFCLKEN_DBCLK));
 
-static struct clk gpio4_ick = {
-	.name		= "gpio4_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio4_ick, l4_div_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L4PER_GPIO4));
 
-static struct clk gpio5_dbclk = {
-	.name		= "gpio5_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio5_dbclk, sys_32k_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4PER_GPIO5, OPTFCLKEN_DBCLK));
 
-static struct clk gpio5_ick = {
-	.name		= "gpio5_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio5_ick, l4_div_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L4PER_GPIO5));
 
-static struct clk gpio6_dbclk = {
-	.name		= "gpio6_dbclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio6_dbclk, sys_32k_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L4PER_GPIO6, OPTFCLKEN_DBCLK));
 
-static struct clk gpio6_ick = {
-	.name		= "gpio6_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpio6_ick, l4_div_ck, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L4PER_GPIO6));
 
-static struct clk gpmc_ick = {
-	.name		= "gpmc_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3_2_GPMC_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_2_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(gpmc_ick, l3_div_ck, l3_2_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L3_2_GPMC));
 
-static const struct clksel sgx_clk_mux_sel[] = {
-	{ .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(sgx_clk_mux_sel, dpll_core_m7x2_ck, dpll_per_m7x2_ck);
 
 /* Merged sgx_clk_mux into gpu */
-static struct clk gpu_fck = {
-	.name		= "gpu_fck",
-	.parent		= &dpll_core_m7x2_ck,
-	.clksel		= sgx_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_GFX_GFX_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SGX_FCLK_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_GFX_GFX_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_gfx_clkdm",
-};
+DEFINE_CLOCK_DM(gpu_fck, dpll_core_m7x2_ck, l3_gfx_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_GFX_GFX),
+		CLOCK_CLKSEL0(sgx_clk_mux_sel,
+			      CM_GFX_GFX_CLKCTRL, CLKSEL_SGX_FCLK));
 
-static struct clk hdq1w_fck = {
-	.name		= "hdq1w_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_12m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(hdq1w_fck, func_12m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_HDQ1W));
 
-static const struct clksel hsi_fclk_div[] = {
-	{ .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(hsi_fclk_div, dpll_per_m2x2_ck, div3_1to4_rates);
 
 /* Merged hsi_fclk into hsi */
-static struct clk hsi_fck = {
-	.name		= "hsi_fck",
-	.parent		= &dpll_per_m2x2_ck,
-	.clksel		= hsi_fclk_div,
-	.clksel_reg	= OMAP4430_CM_L3INIT_HSI_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_24_25_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-	.enable_reg	= OMAP4430_CM_L3INIT_HSI_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-};
+DEFINE_CLOCK_DM(hsi_fck, dpll_per_m2x2_ck, l3_init_clkdm,
+		CLOCK_OPS_DFLT_HW(CM_L3INIT_HSI),
+		CLOCK_CLKSEL(hsi_fclk_div,
+			     CM_L3INIT_HSI_CLKCTRL, CLKSEL_24_25));
 
-static struct clk i2c1_fck = {
-	.name		= "i2c1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(i2c1_fck, func_96m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_I2C1));
 
-static struct clk i2c2_fck = {
-	.name		= "i2c2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(i2c2_fck, func_96m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_I2C2));
 
-static struct clk i2c3_fck = {
-	.name		= "i2c3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(i2c3_fck, func_96m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_I2C3));
 
-static struct clk i2c4_fck = {
-	.name		= "i2c4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_I2C4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(i2c4_fck, func_96m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_I2C4));
 
-static struct clk ipu_fck = {
-	.name		= "ipu_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "ducati_clkdm",
-	.parent		= &ducati_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(ipu_fck, ducati_clk_mux_ck, ducati_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_DUCATI_DUCATI));
 
-static struct clk iss_ctrlclk = {
-	.name		= "iss_ctrlclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_CAM_ISS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
-	.clkdm_name	= "iss_clkdm",
-	.parent		= &func_96m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(iss_ctrlclk, func_96m_fclk, iss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_CAM_ISS, OPTFCLKEN_CTRLCLK));
 
-static struct clk iss_fck = {
-	.name		= "iss_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_CAM_ISS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "iss_clkdm",
-	.parent		= &ducati_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(iss_fck, ducati_clk_mux_ck, iss_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_CAM_ISS));
 
-static struct clk iva_fck = {
-	.name		= "iva_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5x2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(iva_fck, dpll_iva_m5x2_ck, ivahd_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_IVAHD_IVAHD));
 
-static struct clk kbd_fck = {
-	.name		= "kbd_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(kbd_fck, sys_32k_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_WKUP_KEYBOARD));
 
-static struct clk l3_instr_ick = {
-	.name		= "l3_instr_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_instr_clkdm",
-	.flags		= ENABLE_ON_INIT,
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(l3_instr_ick, l3_div_ck, l3_instr_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L3INSTR_L3_INSTR),
+		CLOCK_FLAGS_ENABLE());
 
-static struct clk l3_main_3_ick = {
-	.name		= "l3_main_3_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_instr_clkdm",
-	.flags		= ENABLE_ON_INIT,
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(l3_main_3_ick, l3_div_ck, l3_instr_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L3INSTR_L3_3),
+		CLOCK_FLAGS_ENABLE());
 
-static struct clk mcasp_sync_mux_ck = {
-	.name		= "mcasp_sync_mux_ck",
-	.parent		= &abe_24m_fclk,
-	.clksel		= dmic_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(mcasp_sync_mux_ck, abe_24m_fclk,
+	     CLOCK_CLKSEL_INIT(dmic_sync_mux_sel,
+			       CM1_ABE_MCASP_CLKCTRL, CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
-	{ .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(func_mcasp_abe_gfclk_sel,
+	       mcasp_sync_mux_ck, pad_clks_ck, slimbus_clk);
 
 /* Merged func_mcasp_abe_gfclk into mcasp */
-static struct clk mcasp_fck = {
-	.name		= "mcasp_fck",
-	.parent		= &mcasp_sync_mux_ck,
-	.clksel		= func_mcasp_abe_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(mcasp_fck, mcasp_sync_mux_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(func_mcasp_abe_gfclk_sel,
+				     CM1_ABE_MCASP, CLKSEL_SOURCE));
 
-static struct clk mcbsp1_sync_mux_ck = {
-	.name		= "mcbsp1_sync_mux_ck",
-	.parent		= &abe_24m_fclk,
-	.clksel		= dmic_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(mcbsp1_sync_mux_ck, abe_24m_fclk,
+	     CLOCK_CLKSEL_INIT(dmic_sync_mux_sel,
+			       CM1_ABE_MCBSP1_CLKCTRL, CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
-	{ .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(func_mcbsp1_gfclk_sel,
+	       mcbsp1_sync_mux_ck, pad_clks_ck, slimbus_clk);
 
 /* Merged func_mcbsp1_gfclk into mcbsp1 */
-static struct clk mcbsp1_fck = {
-	.name		= "mcbsp1_fck",
-	.parent		= &mcbsp1_sync_mux_ck,
-	.clksel		= func_mcbsp1_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(mcbsp1_fck, mcbsp1_sync_mux_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(func_mcbsp1_gfclk_sel,
+				     CM1_ABE_MCBSP1, CLKSEL_SOURCE));
 
-static struct clk mcbsp2_sync_mux_ck = {
-	.name		= "mcbsp2_sync_mux_ck",
-	.parent		= &abe_24m_fclk,
-	.clksel		= dmic_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(mcbsp2_sync_mux_ck, abe_24m_fclk,
+	     CLOCK_CLKSEL_INIT(dmic_sync_mux_sel,
+			       CM1_ABE_MCBSP2_CLKCTRL, CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
-	{ .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(func_mcbsp2_gfclk_sel,
+	       mcbsp2_sync_mux_ck, pad_clks_ck, slimbus_clk);
 
 /* Merged func_mcbsp2_gfclk into mcbsp2 */
-static struct clk mcbsp2_fck = {
-	.name		= "mcbsp2_fck",
-	.parent		= &mcbsp2_sync_mux_ck,
-	.clksel		= func_mcbsp2_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(mcbsp2_fck, mcbsp2_sync_mux_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(func_mcbsp2_gfclk_sel,
+				     CM1_ABE_MCBSP2, CLKSEL_SOURCE));
 
-static struct clk mcbsp3_sync_mux_ck = {
-	.name		= "mcbsp3_sync_mux_ck",
-	.parent		= &abe_24m_fclk,
-	.clksel		= dmic_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(mcbsp3_sync_mux_ck, abe_24m_fclk,
+	     CLOCK_CLKSEL_INIT(dmic_sync_mux_sel,
+			       CM1_ABE_MCBSP3_CLKCTRL, CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
-	{ .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = &slimbus_clk, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(func_mcbsp3_gfclk_sel,
+	       mcbsp3_sync_mux_ck, pad_clks_ck, slimbus_clk);
 
 /* Merged func_mcbsp3_gfclk into mcbsp3 */
-static struct clk mcbsp3_fck = {
-	.name		= "mcbsp3_fck",
-	.parent		= &mcbsp3_sync_mux_ck,
-	.clksel		= func_mcbsp3_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(mcbsp3_fck, mcbsp3_sync_mux_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(func_mcbsp3_gfclk_sel,
+				     CM1_ABE_MCBSP3, CLKSEL_SOURCE));
 
-static struct clk mcbsp4_sync_mux_ck = {
-	.name		= "mcbsp4_sync_mux_ck",
-	.parent		= &func_96m_fclk,
-	.clksel		= mcasp2_fclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(mcbsp4_sync_mux_ck, func_96m_fclk,
+	     CLOCK_CLKSEL_INIT(mcasp2_fclk_sel,
+			       CM_L4PER_MCBSP4_CLKCTRL,
+			       CLKSEL_INTERNAL_SOURCE));
 
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
-	{ .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
-	{ .parent = &pad_clks_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(per_mcbsp4_gfclk_sel, mcbsp4_sync_mux_ck, pad_clks_ck);
 
 /* Merged per_mcbsp4_gfclk into mcbsp4 */
-static struct clk mcbsp4_fck = {
-	.name		= "mcbsp4_fck",
-	.parent		= &mcbsp4_sync_mux_ck,
-	.clksel		= per_mcbsp4_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_SOURCE_24_24_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(mcbsp4_fck, mcbsp4_sync_mux_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(per_mcbsp4_gfclk_sel,
+				     CM_L4PER_MCBSP4, CLKSEL_SOURCE_24_24));
 
-static struct clk mcpdm_fck = {
-	.name		= "mcpdm_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_PDM_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &pad_clks_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mcpdm_fck, pad_clks_ck, abe_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM1_ABE_PDM));
 
-static struct clk mcspi1_fck = {
-	.name		= "mcspi1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mcspi1_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MCSPI1));
 
-static struct clk mcspi2_fck = {
-	.name		= "mcspi2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mcspi2_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MCSPI2));
 
-static struct clk mcspi3_fck = {
-	.name		= "mcspi3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mcspi3_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MCSPI3));
 
-static struct clk mcspi4_fck = {
-	.name		= "mcspi4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mcspi4_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MCSPI4));
 
 /* Merged hsmmc1_fclk into mmc1 */
-static struct clk mmc1_fck = {
-	.name		= "mmc1_fck",
-	.parent		= &func_64m_fclk,
-	.clksel		= hsmmc6_fclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-};
+DEFINE_CLOCK_DM(mmc1_fck, func_64m_fclk, l3_init_clkdm,
+		CLOCK_CLKSEL_INIT_SW(hsmmc6_fclk_sel, CM_L3INIT_MMC1, CLKSEL));
 
 /* Merged hsmmc2_fclk into mmc2 */
-static struct clk mmc2_fck = {
-	.name		= "mmc2_fck",
-	.parent		= &func_64m_fclk,
-	.clksel		= hsmmc6_fclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-};
+DEFINE_CLOCK_DM(mmc2_fck, func_64m_fclk, l3_init_clkdm,
+		CLOCK_CLKSEL_INIT_SW(hsmmc6_fclk_sel, CM_L3INIT_MMC2, CLKSEL));
 
-static struct clk mmc3_fck = {
-	.name		= "mmc3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mmc3_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MMCSD3),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk mmc4_fck = {
-	.name		= "mmc4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mmc4_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MMCSD4),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk mmc5_fck = {
-	.name		= "mmc5_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(mmc5_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_L4PER_MMCSD5),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk ocp2scp_usb_phy_phy_48m = {
-	.name		= "ocp2scp_usb_phy_phy_48m",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(ocp2scp_usb_phy_phy_48m, func_48m_fclk, l3_init_clkdm,
+		CLOCK_OPS_DFLT(CM_L3INIT_USBPHYOCP2SCP, OPTFCLKEN_PHY_48M),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk ocp2scp_usb_phy_ick = {
-	.name		= "ocp2scp_usb_phy_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(ocp2scp_usb_phy_ick, l4_div_ck, l3_init_clkdm,
+		CLOCK_OPS_DFLT_HW(CM_L3INIT_USBPHYOCP2SCP),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk ocp_wp_noc_ick = {
-	.name		= "ocp_wp_noc_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_instr_clkdm",
-	.flags		= ENABLE_ON_INIT,
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(ocp_wp_noc_ick, l3_div_ck, l3_instr_clkdm,
+		CLOCK_OPS_DFLT_HW(CM_L3INSTR_OCP_WP1),
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_FLAGS_ENABLE());
 
-static struct clk rng_ick = {
-	.name		= "rng_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_RNG_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(rng_ick, l4_div_ck, l4_secure_clkdm,
+		CLOCK_OPS_DFLT_HW(CM_L4SEC_RNG),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk sha2md5_fck = {
-	.name		= "sha2md5_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_secure_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(sha2md5_fck, l3_div_ck, l4_secure_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_L4SEC_SHA2MD51),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk sl2if_ick = {
-	.name		= "sl2if_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_IVAHD_SL2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5x2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(sl2if_ick, dpll_iva_m5x2_ck, ivahd_clkdm,
+		CLOCK_OPS_DFLT_HW(CM_IVAHD_SL2),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus1_fclk_1 = {
-	.name		= "slimbus1_fclk_1",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &func_24m_clk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus1_fclk_0, abe_24m_fclk, abe_clkdm,
+		CLOCK_OPS_DFLT(CM1_ABE_SLIMBUS, OPTFCLKEN_FCLK0),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus1_fclk_0 = {
-	.name		= "slimbus1_fclk_0",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &abe_24m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus1_fclk_1, func_24m_clk, abe_clkdm,
+		CLOCK_OPS_DFLT(CM1_ABE_SLIMBUS, OPTFCLKEN_FCLK1),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus1_fclk_2 = {
-	.name		= "slimbus1_fclk_2",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &pad_clks_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus1_fclk_2, pad_clks_ck, abe_clkdm,
+		CLOCK_OPS_DFLT(CM1_ABE_SLIMBUS, OPTFCLKEN_FCLK2),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus1_slimbus_clk = {
-	.name		= "slimbus1_slimbus_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &slimbus_clk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus1_slimbus_clk, slimbus_clk, abe_clkdm,
+		CLOCK_OPS_DFLT(CM1_ABE_SLIMBUS, OPTFCLKEN_SLIMBUS_CLK_11_11),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus1_fck = {
-	.name		= "slimbus1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &ocp_abe_iclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus1_fck, ocp_abe_iclk, abe_clkdm,
+		CLOCK_OPS_DFLT_SW(CM1_ABE_SLIMBUS),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus2_fclk_1 = {
-	.name		= "slimbus2_fclk_1",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &per_abe_24m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus2_fclk_1, per_abe_24m_fclk, l4_per_clkdm,
+		CLOCK_OPS_DFLT(CM_L4PER_SLIMBUS2, OPTFCLKEN_PERABE24M_GFCLK),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus2_fclk_0 = {
-	.name		= "slimbus2_fclk_0",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_24mc_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus2_fclk_0, func_24mc_fclk, l4_per_clkdm,
+		CLOCK_OPS_DFLT(CM_L4PER_SLIMBUS2, OPTFCLKEN_PER24MC_GFCLK),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus2_slimbus_clk = {
-	.name		= "slimbus2_slimbus_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &pad_slimbus_core_clks_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus2_slimbus_clk, pad_slimbus_core_clks_ck, l4_per_clkdm,
+		CLOCK_OPS_DFLT(CM_L4PER_SLIMBUS2, OPTFCLKEN_SLIMBUS_CLK),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk slimbus2_fck = {
-	.name		= "slimbus2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(slimbus2_fck, l4_div_ck, l4_per_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_L4PER_SLIMBUS2),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk smartreflex_core_fck = {
-	.name		= "smartreflex_core_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(smartreflex_core_fck, l4_wkup_clk_mux_ck, l4_ao_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_ALWON_SR_CORE),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk smartreflex_iva_fck = {
-	.name		= "smartreflex_iva_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(smartreflex_iva_fck, l4_wkup_clk_mux_ck, l4_ao_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_ALWON_SR_IVA),
+		CLOCK_RECALC_FOLLOWPARENT());
 
-static struct clk smartreflex_mpu_fck = {
-	.name		= "smartreflex_mpu_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &l4_wkup_clk_mux_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(smartreflex_mpu_fck, l4_wkup_clk_mux_ck, l4_ao_clkdm,
+		CLOCK_OPS_DFLT_SW(CM_ALWON_SR_MPU),
+		CLOCK_RECALC_FOLLOWPARENT());
 
 /* Merged dmt1_clk_mux into timer1 */
-static struct clk timer1_fck = {
-	.name		= "timer1_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-};
+DEFINE_CLOCK_DM(timer1_fck, sys_clkin_ck, l4_wkup_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_WKUP_TIMER1, CLKSEL));
 
 /* Merged cm2_dm10_mux into timer10 */
-static struct clk timer10_fck = {
-	.name		= "timer10_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer10_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER10, CLKSEL));
 
 /* Merged cm2_dm11_mux into timer11 */
-static struct clk timer11_fck = {
-	.name		= "timer11_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer11_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER11, CLKSEL));
 
 /* Merged cm2_dm2_mux into timer2 */
-static struct clk timer2_fck = {
-	.name		= "timer2_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer2_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER2, CLKSEL));
 
 /* Merged cm2_dm3_mux into timer3 */
-static struct clk timer3_fck = {
-	.name		= "timer3_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer3_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER3, CLKSEL));
 
 /* Merged cm2_dm4_mux into timer4 */
-static struct clk timer4_fck = {
-	.name		= "timer4_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer4_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER4, CLKSEL));
 
-static const struct clksel timer5_sync_mux_sel[] = {
-	{ .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-	{ .parent = &sys_32k_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(timer5_sync_mux_sel, syc_clk_div_ck, sys_32k_ck);
 
 /* Merged timer5_sync_mux into timer5 */
-static struct clk timer5_fck = {
-	.name		= "timer5_fck",
-	.parent		= &syc_clk_div_ck,
-	.clksel		= timer5_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(timer5_fck, syc_clk_div_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(timer5_sync_mux_sel,
+				     CM1_ABE_TIMER5, CLKSEL));
 
 /* Merged timer6_sync_mux into timer6 */
-static struct clk timer6_fck = {
-	.name		= "timer6_fck",
-	.parent		= &syc_clk_div_ck,
-	.clksel		= timer5_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(timer6_fck, syc_clk_div_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(timer5_sync_mux_sel,
+				     CM1_ABE_TIMER6, CLKSEL));
 
 /* Merged timer7_sync_mux into timer7 */
-static struct clk timer7_fck = {
-	.name		= "timer7_fck",
-	.parent		= &syc_clk_div_ck,
-	.clksel		= timer5_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(timer7_fck, syc_clk_div_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(timer5_sync_mux_sel,
+				     CM1_ABE_TIMER7, CLKSEL));
 
 /* Merged timer8_sync_mux into timer8 */
-static struct clk timer8_fck = {
-	.name		= "timer8_fck",
-	.parent		= &syc_clk_div_ck,
-	.clksel		= timer5_sync_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-};
+DEFINE_CLOCK_DM(timer8_fck, syc_clk_div_ck, abe_clkdm,
+		CLOCK_CLKSEL_INIT_SW(timer5_sync_mux_sel,
+				     CM1_ABE_TIMER8, CLKSEL));
 
 /* Merged cm2_dm9_mux into timer9 */
-static struct clk timer9_fck = {
-	.name		= "timer9_fck",
-	.parent		= &sys_clkin_ck,
-	.clksel		= abe_dpll_bypass_clk_mux_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_MASK,
-	.ops		= &clkops_omap2_dflt,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-};
+DEFINE_CLOCK_DM(timer9_fck, sys_clkin_ck, l4_per_clkdm,
+		CLOCK_CLKSEL_INIT_SW(abe_dpll_bypass_clk_mux_sel,
+				     CM_L4PER_DMTIMER9, CLKSEL));
 
-static struct clk uart1_fck = {
-	.name		= "uart1_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART1_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(uart1_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_UART1));
 
-static struct clk uart2_fck = {
-	.name		= "uart2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(uart2_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_UART2));
 
-static struct clk uart3_fck = {
-	.name		= "uart3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(uart3_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_UART3));
 
-static struct clk uart4_fck = {
-	.name		= "uart4_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L4PER_UART4_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_per_clkdm",
-	.parent		= &func_48m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(uart4_fck, func_48m_fclk, l4_per_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L4PER_UART4));
 
-static struct clk usb_host_fs_fck = {
-	.name		= "usb_host_fs_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &func_48mc_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_fs_fck, func_48mc_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L3INIT_USB_HOST_FS));
 
-static const struct clksel utmi_p1_gfclk_sel[] = {
-	{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
-	{ .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(utmi_p1_gfclk_sel, init_60m_fclk, xclk60mhsp1_ck);
 
-static struct clk utmi_p1_gfclk = {
-	.name		= "utmi_p1_gfclk",
-	.parent		= &init_60m_fclk,
-	.clksel		= utmi_p1_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_UTMI_P1_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(utmi_p1_gfclk, init_60m_fclk,
+	     CLOCK_CLKSEL_INIT(utmi_p1_gfclk_sel,
+			       CM_L3INIT_USB_HOST_CLKCTRL, CLKSEL_UTMI_P1));
 
-static struct clk usb_host_hs_utmi_p1_clk = {
-	.name		= "usb_host_hs_utmi_p1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &utmi_p1_gfclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_utmi_p1_clk, utmi_p1_gfclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_UTMI_P1_CLK));
 
-static const struct clksel utmi_p2_gfclk_sel[] = {
-	{ .parent = &init_60m_fclk, .rates = div_1_0_rates },
-	{ .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(utmi_p2_gfclk_sel, init_60m_fclk, xclk60mhsp2_ck);
 
-static struct clk utmi_p2_gfclk = {
-	.name		= "utmi_p2_gfclk",
-	.parent		= &init_60m_fclk,
-	.clksel		= utmi_p2_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_UTMI_P2_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(utmi_p2_gfclk, init_60m_fclk,
+	     CLOCK_CLKSEL_INIT(utmi_p2_gfclk_sel,
+			       CM_L3INIT_USB_HOST_CLKCTRL, CLKSEL_UTMI_P2));
 
-static struct clk usb_host_hs_utmi_p2_clk = {
-	.name		= "usb_host_hs_utmi_p2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &utmi_p2_gfclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_utmi_p2_clk, utmi_p2_gfclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_UTMI_P2_CLK));
 
-static struct clk usb_host_hs_utmi_p3_clk = {
-	.name		= "usb_host_hs_utmi_p3_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_utmi_p3_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_UTMI_P3_CLK));
 
-static struct clk usb_host_hs_hsic480m_p1_clk = {
-	.name		= "usb_host_hs_hsic480m_p1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &dpll_usb_m2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_hsic60m_p1_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_HSIC60M_P1_CLK));
 
-static struct clk usb_host_hs_hsic60m_p1_clk = {
-	.name		= "usb_host_hs_hsic60m_p1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_hsic60m_p2_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_HSIC60M_P2_CLK));
 
-static struct clk usb_host_hs_hsic60m_p2_clk = {
-	.name		= "usb_host_hs_hsic60m_p2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_hsic480m_p1_clk, dpll_usb_m2_ck, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_HSIC480M_P1_CLK));
 
-static struct clk usb_host_hs_hsic480m_p2_clk = {
-	.name		= "usb_host_hs_hsic480m_p2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &dpll_usb_m2_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_hsic480m_p2_clk, dpll_usb_m2_ck, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_HSIC480M_P2_CLK));
 
-static struct clk usb_host_hs_func48mclk = {
-	.name		= "usb_host_hs_func48mclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &func_48mc_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_func48mclk, func_48mc_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_HOST, OPTFCLKEN_FUNC48MCLK));
 
-static struct clk usb_host_hs_fck = {
-	.name		= "usb_host_hs_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_host_hs_fck, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_L3INIT_USB_HOST));
 
-static const struct clksel otg_60m_gfclk_sel[] = {
-	{ .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
-	{ .parent = &xclk60motg_ck, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(otg_60m_gfclk_sel, utmi_phy_clkout_ck, xclk60motg_ck);
 
-static struct clk otg_60m_gfclk = {
-	.name		= "otg_60m_gfclk",
-	.parent		= &utmi_phy_clkout_ck,
-	.clksel		= otg_60m_gfclk_sel,
-	.init		= &omap2_init_clksel_parent,
-	.clksel_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_60M_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(otg_60m_gfclk, utmi_phy_clkout_ck,
+	     CLOCK_CLKSEL_INIT(otg_60m_gfclk_sel,
+			       CM_L3INIT_USB_OTG_CLKCTRL, CLKSEL_60M));
 
-static struct clk usb_otg_hs_xclk = {
-	.name		= "usb_otg_hs_xclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_XCLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &otg_60m_gfclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_otg_hs_xclk, otg_60m_gfclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_OTG, OPTFCLKEN_XCLK));
 
-static struct clk usb_otg_hs_ick = {
-	.name		= "usb_otg_hs_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &l3_div_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_otg_hs_ick, l3_div_ck, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L3INIT_USB_OTG));
 
-static struct clk usb_phy_cm_clk32k = {
-	.name		= "usb_phy_cm_clk32k",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
-	.clkdm_name	= "l4_ao_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_phy_cm_clk32k, sys_32k_ck, l4_ao_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_ALWON_USBPHY, OPTFCLKEN_CLK32K));
 
-static struct clk usb_tll_hs_usb_ch2_clk = {
-	.name		= "usb_tll_hs_usb_ch2_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_tll_hs_usb_ch0_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_TLL, OPTFCLKEN_USB_CH0_CLK));
 
-static struct clk usb_tll_hs_usb_ch0_clk = {
-	.name		= "usb_tll_hs_usb_ch0_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_tll_hs_usb_ch1_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_TLL, OPTFCLKEN_USB_CH1_CLK));
 
-static struct clk usb_tll_hs_usb_ch1_clk = {
-	.name		= "usb_tll_hs_usb_ch1_clk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &init_60m_fclk,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usb_tll_hs_usb_ch2_clk, init_60m_fclk, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_L3INIT_USB_TLL, OPTFCLKEN_USB_CH2_CLK));
 
-static struct clk usb_tll_hs_ick = {
-	.name		= "usb_tll_hs_ick",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l3_init_clkdm",
-	.parent		= &l4_div_ck,
-	.recalc		= &followparent_recalc,
-};
 
-static const struct clksel_rate div2_14to18_rates[] = {
-	{ .div = 14, .val = 0, .flags = RATE_IN_4430 },
-	{ .div = 18, .val = 1, .flags = RATE_IN_4430 },
-	{ .div = 0 },
-};
+DEFINE_CLOCK_DM(usb_tll_hs_ick, l4_div_ck, l3_init_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_L3INIT_USB_TLL));
 
-static const struct clksel usim_fclk_div[] = {
-	{ .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL_RATE2(14to18, 14, 18);
 
-static struct clk usim_ck = {
-	.name		= "usim_ck",
-	.parent		= &dpll_per_m4x2_ck,
-	.clksel		= usim_fclk_div,
-	.clksel_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_DIV_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLKSEL(usim_fclk_div, dpll_per_m4x2_ck, div2_14to18_rates);
 
-static struct clk usim_fclk = {
-	.name		= "usim_fclk",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
-	.enable_bit	= OMAP4430_OPTFCLKEN_FCLK_SHIFT,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &usim_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK(usim_ck, dpll_per_m4x2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(usim_fclk_div, CM_WKUP_USIM_CLKCTRL, CLKSEL_DIV));
 
-static struct clk usim_fck = {
-	.name		= "usim_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_USIM_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usim_fclk, usim_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT(CM_WKUP_USIM, OPTFCLKEN_FCLK));
 
-static struct clk wd_timer2_fck = {
-	.name		= "wd_timer2_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM_WKUP_WDT2_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "l4_wkup_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(usim_fck, sys_32k_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_HW(CM_WKUP_USIM));
 
-static struct clk wd_timer3_fck = {
-	.name		= "wd_timer3_fck",
-	.ops		= &clkops_omap2_dflt,
-	.enable_reg	= OMAP4430_CM1_ABE_WDT3_CLKCTRL,
-	.enable_bit	= OMAP4430_MODULEMODE_SWCTRL,
-	.clkdm_name	= "abe_clkdm",
-	.parent		= &sys_32k_ck,
-	.recalc		= &followparent_recalc,
-};
+DEFINE_CLOCK_DM(wd_timer2_fck, sys_32k_ck, l4_wkup_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM_WKUP_WDT2));
+
+DEFINE_CLOCK_DM(wd_timer3_fck, sys_32k_ck, abe_clkdm,
+		CLOCK_RECALC_FOLLOWPARENT(),
+		CLOCK_OPS_DFLT_SW(CM1_ABE_WDT3));
 
 /* Remaining optional clocks */
-static const struct clksel stm_clk_div_div[] = {
-	{ .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
 
-static struct clk stm_clk_div_ck = {
-	.name		= "stm_clk_div_ck",
-	.parent		= &pmd_stm_clock_mux_ck,
-	.clksel		= stm_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLKSEL(stm_clk_div_div, pmd_stm_clock_mux_ck, div3_1to4_rates);
 
-static const struct clksel trace_clk_div_div[] = {
-	{ .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLOCK(stm_clk_div_ck, pmd_stm_clock_mux_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(stm_clk_div_div,
+			  CM_EMU_DEBUGSS_CLKCTRL, CLKSEL_PMD_STM_CLK));
 
-static struct clk trace_clk_div_ck = {
-	.name		= "trace_clk_div_ck",
-	.parent		= &pmd_trace_clk_mux_ck,
-	.clksel		= trace_clk_div_div,
-	.clksel_reg	= OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-	.clksel_mask	= OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-	.ops		= &clkops_null,
-	.recalc		= &omap2_clksel_recalc,
-	.round_rate	= &omap2_clksel_round_rate,
-	.set_rate	= &omap2_clksel_set_rate,
-};
+DEFINE_CLKSEL(trace_clk_div_div, pmd_trace_clk_mux_ck, div3_1to4_rates);
+
+DEFINE_CLOCK(trace_clk_div_ck, pmd_trace_clk_mux_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL(trace_clk_div_div,
+			  CM_EMU_DEBUGSS_CLKCTRL, CLKSEL_PMD_TRACE_CLK));
 
 /* SCRM aux clk nodes */
 
-static const struct clksel auxclk_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
-	{ .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL3(auxclk_sel,
+	       sys_clkin_ck, dpll_core_m3x2_ck, dpll_per_m3x2_ck);
 
-static struct clk auxclk0_ck = {
-	.name		= "auxclk0_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK0,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK0,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
+DEFINE_CLOCK(auxclk0_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK0),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK0, SRCSELECT));
 
-static struct clk auxclk1_ck = {
-	.name		= "auxclk1_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK1,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK1,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
+DEFINE_CLOCK(auxclk1_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK1),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK1, SRCSELECT));
 
-static struct clk auxclk2_ck = {
-	.name		= "auxclk2_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK2,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK2,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
-static struct clk auxclk3_ck = {
-	.name		= "auxclk3_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK3,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK3,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
+DEFINE_CLOCK(auxclk2_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK2),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK2, SRCSELECT));
 
-static struct clk auxclk4_ck = {
-	.name		= "auxclk4_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK4,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK4,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
+DEFINE_CLOCK(auxclk3_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK3),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK3, SRCSELECT));
 
-static struct clk auxclk5_ck = {
-	.name		= "auxclk5_ck",
-	.parent		= &sys_clkin_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_omap2_dflt,
-	.clksel		= auxclk_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLK5,
-	.clksel_mask	= OMAP4_SRCSELECT_MASK,
-	.recalc		= &omap2_clksel_recalc,
-	.enable_reg	= OMAP4_SCRM_AUXCLK5,
-	.enable_bit	= OMAP4_ENABLE_SHIFT,
-};
+DEFINE_CLOCK(auxclk4_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK4),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK4, SRCSELECT));
+
+DEFINE_CLOCK(auxclk5_ck, sys_clkin_ck, CLOCK_OPS_DFLT2(SCRM_AUXCLK5),
+	     CLOCK_CLKSEL_INIT2(auxclk_sel, SCRM_AUXCLK5, SRCSELECT));
 
 static const struct clksel auxclkreq_sel[] = {
 	{ .parent = &auxclk0_ck, .rates = div_1_0_rates },
@@ -2246,71 +1375,23 @@ static const struct clksel auxclkreq_sel[] = {
 	{ .parent = NULL },
 };
 
-static struct clk auxclkreq0_ck = {
-	.name		= "auxclkreq0_ck",
-	.parent		= &auxclk0_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ0,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq0_ck, auxclk0_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ0, MAPPING));
 
-static struct clk auxclkreq1_ck = {
-	.name		= "auxclkreq1_ck",
-	.parent		= &auxclk1_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ1,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq1_ck, auxclk1_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ1, MAPPING));
 
-static struct clk auxclkreq2_ck = {
-	.name		= "auxclkreq2_ck",
-	.parent		= &auxclk2_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ2,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq2_ck, auxclk2_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ2, MAPPING));
 
-static struct clk auxclkreq3_ck = {
-	.name		= "auxclkreq3_ck",
-	.parent		= &auxclk3_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ3,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq3_ck, auxclk3_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ3, MAPPING));
 
-static struct clk auxclkreq4_ck = {
-	.name		= "auxclkreq4_ck",
-	.parent		= &auxclk4_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ4,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq4_ck, auxclk4_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ4, MAPPING));
 
-static struct clk auxclkreq5_ck = {
-	.name		= "auxclkreq5_ck",
-	.parent		= &auxclk5_ck,
-	.init		= &omap2_init_clksel_parent,
-	.ops		= &clkops_null,
-	.clksel         = auxclkreq_sel,
-	.clksel_reg	= OMAP4_SCRM_AUXCLKREQ5,
-	.clksel_mask	= OMAP4_MAPPING_MASK,
-	.recalc		= &omap2_clksel_recalc,
-};
+DEFINE_CLOCK(auxclkreq5_ck, auxclk5_ck, CLOCK_OPS_NULL(),
+	     CLOCK_CLKSEL_INIT2(auxclkreq_sel, SCRM_AUXCLKREQ5, MAPPING));
 
 /*
  * clkdev
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* Re: [PATCHv2 2/2] [RFC] OMAP4: clock data: shrink more clock data.
  2011-05-15 21:45   ` Vladimir Zapolskiy
@ 2011-05-16  6:53     ` Avinash.H.M.
  -1 siblings, 0 replies; 16+ messages in thread
From: Avinash.H.M. @ 2011-05-16  6:53 UTC (permalink / raw)
  To: Vladimir Zapolskiy
  Cc: Tony Lindgren, Benoit Cousson, linux-omap, linux-arm-kernel

On Mon, May 16, 2011 at 12:45:58AM +0300, Vladimir Zapolskiy wrote:
> This mass change continues the reduction of homogeneous data chunks
> along clock definitions. No semantical difference is added in the
> change.
> 
> Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com>
> ---

[ ... ]

> +DEFINE_CLOCK_DM(gpu_fck, dpll_core_m7x2_ck, l3_gfx_clkdm,
> +		CLOCK_OPS_DFLT_SW(CM_GFX_GFX),
> +		CLOCK_CLKSEL0(sgx_clk_mux_sel,
> +			      CM_GFX_GFX_CLKCTRL, CLKSEL_SGX_FCLK));
>  

Hi Vladimir ,

With this the rate wouldn't get initialised and it throws a warning at
boot.

[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: at arch/arm/mach-omap2/clkt_clksel.c:194 omap2_clksel_recalc+0xd4/0xe4()
[    0.000000] clock: Could not find fieldval 1 for clock gpu_fck parent dpll_core_m7x2_ck
[    0.000000] Modules linked in:
[    0.000000] [<c005fd5c>] (unwind_backtrace+0x0/0xe4) from [<c00921b4>] (warn_slowpath_common+0x4c/0x64)
[    0.000000] [<c00921b4>] (warn_slowpath_common+0x4c/0x64) from [<c009224c>] (warn_slowpath_fmt+0x2c/0x3c)
[    0.000000] [<c009224c>] (warn_slowpath_fmt+0x2c/0x3c) from [<c0072594>] (omap2_clksel_recalc+0xd4/0xe4)
[    0.000000] [<c0072594>] (omap2_clksel_recalc+0xd4/0xe4) from [<c007712c>] (propagate_rate+0x24/0x50)
[    0.000000] [<c007712c>] (propagate_rate+0x24/0x50) from [<c0077138>] (propagate_rate+0x30/0x50)
[    0.000000] ---[ end trace 1b75b31a2719ed1c ]---

Will be fixed with this change below :

-		CLOCK_CLKSEL0(sgx_clk_mux_sel,
+		CLOCK_CLKSEL_INIT(sgx_clk_mux_sel,

May be CLOCK_CLKSEL0 is not required altogether. I see it used only to
initialise gpu_fck. May be can remove this.

I boot tested it on 4430 sdp. FWIW , you can add 
Tested-by: Avinash.H.M. <avinashhm@ti.com>

thanks,

- Avinash
 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCHv2 2/2] [RFC] OMAP4: clock data: shrink more clock data.
@ 2011-05-16  6:53     ` Avinash.H.M.
  0 siblings, 0 replies; 16+ messages in thread
From: Avinash.H.M. @ 2011-05-16  6:53 UTC (permalink / raw)
  To: linux-arm-kernel

On Mon, May 16, 2011 at 12:45:58AM +0300, Vladimir Zapolskiy wrote:
> This mass change continues the reduction of homogeneous data chunks
> along clock definitions. No semantical difference is added in the
> change.
> 
> Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com>
> ---

[ ... ]

> +DEFINE_CLOCK_DM(gpu_fck, dpll_core_m7x2_ck, l3_gfx_clkdm,
> +		CLOCK_OPS_DFLT_SW(CM_GFX_GFX),
> +		CLOCK_CLKSEL0(sgx_clk_mux_sel,
> +			      CM_GFX_GFX_CLKCTRL, CLKSEL_SGX_FCLK));
>  

Hi Vladimir ,

With this the rate wouldn't get initialised and it throws a warning at
boot.

[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: at arch/arm/mach-omap2/clkt_clksel.c:194 omap2_clksel_recalc+0xd4/0xe4()
[    0.000000] clock: Could not find fieldval 1 for clock gpu_fck parent dpll_core_m7x2_ck
[    0.000000] Modules linked in:
[    0.000000] [<c005fd5c>] (unwind_backtrace+0x0/0xe4) from [<c00921b4>] (warn_slowpath_common+0x4c/0x64)
[    0.000000] [<c00921b4>] (warn_slowpath_common+0x4c/0x64) from [<c009224c>] (warn_slowpath_fmt+0x2c/0x3c)
[    0.000000] [<c009224c>] (warn_slowpath_fmt+0x2c/0x3c) from [<c0072594>] (omap2_clksel_recalc+0xd4/0xe4)
[    0.000000] [<c0072594>] (omap2_clksel_recalc+0xd4/0xe4) from [<c007712c>] (propagate_rate+0x24/0x50)
[    0.000000] [<c007712c>] (propagate_rate+0x24/0x50) from [<c0077138>] (propagate_rate+0x30/0x50)
[    0.000000] ---[ end trace 1b75b31a2719ed1c ]---

Will be fixed with this change below :

-		CLOCK_CLKSEL0(sgx_clk_mux_sel,
+		CLOCK_CLKSEL_INIT(sgx_clk_mux_sel,

May be CLOCK_CLKSEL0 is not required altogether. I see it used only to
initialise gpu_fck. May be can remove this.

I boot tested it on 4430 sdp. FWIW , you can add 
Tested-by: Avinash.H.M. <avinashhm@ti.com>

thanks,

- Avinash
 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor
  2011-05-15 21:45 ` Vladimir Zapolskiy
@ 2011-05-16  7:56   ` Sascha Hauer
  -1 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2011-05-16  7:56 UTC (permalink / raw)
  To: Vladimir Zapolskiy
  Cc: Tony Lindgren, Benoit Cousson, linux-omap, linux-arm-kernel

Hi Vladimir,

On Mon, May 16, 2011 at 12:45:56AM +0300, Vladimir Zapolskiy wrote:
> This change shows a possibility to utilize C preprocessor to remove
> redundant data from clock definitions for OMAP4 architecture.
> 
> If the change is evaluated as a positive one, the same approach could
> be applied in reducing LOCs from other files, which contain monotonous
> data enumeration.
> 
> Vladimir Zapolskiy (2):
>   OMAP4: clock data: shrink clock data utilizing preprocessor.
>   OMAP4: clock data: shrink more clock data.
> 
>  arch/arm/mach-omap2/clock44xx_data.c | 3313 +++++++++-------------------------
>  1 files changed, 848 insertions(+), 2465 deletions(-)

While the diffstat shows a huge saving in loc I suggest to delay this
until we have common clock code merged so that we don't have to
completely rework these files again in the near future.

This has been said before, I just wanted to add my +1 on this opinion.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor
@ 2011-05-16  7:56   ` Sascha Hauer
  0 siblings, 0 replies; 16+ messages in thread
From: Sascha Hauer @ 2011-05-16  7:56 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Vladimir,

On Mon, May 16, 2011 at 12:45:56AM +0300, Vladimir Zapolskiy wrote:
> This change shows a possibility to utilize C preprocessor to remove
> redundant data from clock definitions for OMAP4 architecture.
> 
> If the change is evaluated as a positive one, the same approach could
> be applied in reducing LOCs from other files, which contain monotonous
> data enumeration.
> 
> Vladimir Zapolskiy (2):
>   OMAP4: clock data: shrink clock data utilizing preprocessor.
>   OMAP4: clock data: shrink more clock data.
> 
>  arch/arm/mach-omap2/clock44xx_data.c | 3313 +++++++++-------------------------
>  1 files changed, 848 insertions(+), 2465 deletions(-)

While the diffstat shows a huge saving in loc I suggest to delay this
until we have common clock code merged so that we don't have to
completely rework these files again in the near future.

This has been said before, I just wanted to add my +1 on this opinion.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor
  2011-05-16  7:56   ` Sascha Hauer
@ 2011-05-16 16:25     ` Vladimir Zapolskiy
  -1 siblings, 0 replies; 16+ messages in thread
From: Vladimir Zapolskiy @ 2011-05-16 16:25 UTC (permalink / raw)
  To: Sascha Hauer; +Cc: Tony Lindgren, Benoit Cousson, linux-omap, linux-arm-kernel

Hi Sascha,

On Mon, May 16, 2011 at 10:56 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> Hi Vladimir,
>
> On Mon, May 16, 2011 at 12:45:56AM +0300, Vladimir Zapolskiy wrote:
>> This change shows a possibility to utilize C preprocessor to remove
>> redundant data from clock definitions for OMAP4 architecture.
>>
>> If the change is evaluated as a positive one, the same approach could
>> be applied in reducing LOCs from other files, which contain monotonous
>> data enumeration.
>>
>> Vladimir Zapolskiy (2):
>>   OMAP4: clock data: shrink clock data utilizing preprocessor.
>>   OMAP4: clock data: shrink more clock data.
>>
>>  arch/arm/mach-omap2/clock44xx_data.c | 3313 +++++++++-------------------------
>>  1 files changed, 848 insertions(+), 2465 deletions(-)
>
> While the diffstat shows a huge saving in loc I suggest to delay this
> until we have common clock code merged so that we don't have to
> completely rework these files again in the near future.
>
> This has been said before, I just wanted to add my +1 on this opinion.

no objections from my side, the proposed change is deliberately marked
as RFC, and I've decided to resend the patches just to show them publicly
and to gather more comments.

Best wishes,
Vladimir
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor
@ 2011-05-16 16:25     ` Vladimir Zapolskiy
  0 siblings, 0 replies; 16+ messages in thread
From: Vladimir Zapolskiy @ 2011-05-16 16:25 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Sascha,

On Mon, May 16, 2011 at 10:56 AM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> Hi Vladimir,
>
> On Mon, May 16, 2011 at 12:45:56AM +0300, Vladimir Zapolskiy wrote:
>> This change shows a possibility to utilize C preprocessor to remove
>> redundant data from clock definitions for OMAP4 architecture.
>>
>> If the change is evaluated as a positive one, the same approach could
>> be applied in reducing LOCs from other files, which contain monotonous
>> data enumeration.
>>
>> Vladimir Zapolskiy (2):
>> ? OMAP4: clock data: shrink clock data utilizing preprocessor.
>> ? OMAP4: clock data: shrink more clock data.
>>
>> ?arch/arm/mach-omap2/clock44xx_data.c | 3313 +++++++++-------------------------
>> ?1 files changed, 848 insertions(+), 2465 deletions(-)
>
> While the diffstat shows a huge saving in loc I suggest to delay this
> until we have common clock code merged so that we don't have to
> completely rework these files again in the near future.
>
> This has been said before, I just wanted to add my +1 on this opinion.

no objections from my side, the proposed change is deliberately marked
as RFC, and I've decided to resend the patches just to show them publicly
and to gather more comments.

Best wishes,
Vladimir

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor
  2011-05-15 21:45 ` Vladimir Zapolskiy
@ 2011-05-17 13:06   ` Kevin Hilman
  -1 siblings, 0 replies; 16+ messages in thread
From: Kevin Hilman @ 2011-05-17 13:06 UTC (permalink / raw)
  To: Vladimir Zapolskiy
  Cc: Tony Lindgren, Benoit Cousson, linux-omap, linux-arm-kernel

Vladimir Zapolskiy <vzapolskiy@gmail.com> writes:

> This change shows a possibility to utilize C preprocessor to remove
> redundant data from clock definitions for OMAP4 architecture.
>
> If the change is evaluated as a positive one, the same approach could
> be applied in reducing LOCs from other files, which contain monotonous
> data enumeration.

Now that I can apply these patches and look at the result, I still have
the same opinion.  For me, this results in a major loss of readability.

Changes just to make nice diffstats are fine, but not when it impacts
readability, etc.  Especially since this data will likely be eventually
moved to device tree, I'd rather see consolidation efforts focused
elsewhere.

Kevin

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor
@ 2011-05-17 13:06   ` Kevin Hilman
  0 siblings, 0 replies; 16+ messages in thread
From: Kevin Hilman @ 2011-05-17 13:06 UTC (permalink / raw)
  To: linux-arm-kernel

Vladimir Zapolskiy <vzapolskiy@gmail.com> writes:

> This change shows a possibility to utilize C preprocessor to remove
> redundant data from clock definitions for OMAP4 architecture.
>
> If the change is evaluated as a positive one, the same approach could
> be applied in reducing LOCs from other files, which contain monotonous
> data enumeration.

Now that I can apply these patches and look at the result, I still have
the same opinion.  For me, this results in a major loss of readability.

Changes just to make nice diffstats are fine, but not when it impacts
readability, etc.  Especially since this data will likely be eventually
moved to device tree, I'd rather see consolidation efforts focused
elsewhere.

Kevin

^ permalink raw reply	[flat|nested] 16+ messages in thread

* RE: [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor
  2011-05-17 13:06   ` Kevin Hilman
@ 2011-05-17 15:47     ` Premi, Sanjeev
  -1 siblings, 0 replies; 16+ messages in thread
From: Premi, Sanjeev @ 2011-05-17 15:47 UTC (permalink / raw)
  To: Hilman, Kevin, Vladimir Zapolskiy
  Cc: Tony Lindgren, Cousson, Benoit, linux-omap@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org 
> [mailto:linux-omap-owner@vger.kernel.org] On Behalf Of Hilman, Kevin
> Sent: Tuesday, May 17, 2011 6:37 PM
> To: Vladimir Zapolskiy
> Cc: Tony Lindgren; Cousson, Benoit; 
> linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCHv2 0/2] [RFC] Shrink clock data utilizing 
> preprocessor
> 
> Vladimir Zapolskiy <vzapolskiy@gmail.com> writes:
> 
> > This change shows a possibility to utilize C preprocessor to remove
> > redundant data from clock definitions for OMAP4 architecture.
> >
> > If the change is evaluated as a positive one, the same 
> approach could
> > be applied in reducing LOCs from other files, which contain 
> monotonous
> > data enumeration.
> 
> Now that I can apply these patches and look at the result, I 
> still have
> the same opinion.  For me, this results in a major loss of 
> readability.

[sp] I agree here. __VA_ARGS__ in most of the macros make it difficult
     to undertsand the containment relation.

     Multiple inclusion of macros within another makes it difficult
     to follow the chain/ sequence.

     Using a set of changes to illustrate issue with scalability of
     the macros as well:

-static const struct clksel dpll_core_m2_div[] = {
-	{ .parent = &dpll_core_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_core_m2_div, dpll_core_ck, div31_1to31_rates);
...
... many lines below...
...
-static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(iva_hsd_byp_clk_mux_sel, sys_clkin_ck, div_iva_hs_clk);

    In DEFINE_CLKSEL() we need to pass the "rate" as argument
    and in DEFINE_CLKSEL2() it isn't because we they are hardcoded
    for current implementation.

    But then,

+#define DEFINE_CLKSEL3(_name, _parent0, _parent1, _parent2)		\
+	static const struct clksel _name[] = {				\
+		{ .parent = &_parent0, .rates = div_1_0_rates },	\
+		{ .parent = &_parent1, .rates = div_1_1_rates },	\
+		{ .parent = &_parent2, .rates = div_1_2_rates },	\
+		{ .parent = NULL },					\
+	}
 
    All these definitions don't scale well.

~sanjeev

> 
> Changes just to make nice diffstats are fine, but not when it impacts
> readability, etc.  Especially since this data will likely be 
> eventually
> moved to device tree, I'd rather see consolidation efforts focused
> elsewhere.
> 
> Kevin
> 
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe 
> linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor
@ 2011-05-17 15:47     ` Premi, Sanjeev
  0 siblings, 0 replies; 16+ messages in thread
From: Premi, Sanjeev @ 2011-05-17 15:47 UTC (permalink / raw)
  To: linux-arm-kernel

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org 
> [mailto:linux-omap-owner at vger.kernel.org] On Behalf Of Hilman, Kevin
> Sent: Tuesday, May 17, 2011 6:37 PM
> To: Vladimir Zapolskiy
> Cc: Tony Lindgren; Cousson, Benoit; 
> linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCHv2 0/2] [RFC] Shrink clock data utilizing 
> preprocessor
> 
> Vladimir Zapolskiy <vzapolskiy@gmail.com> writes:
> 
> > This change shows a possibility to utilize C preprocessor to remove
> > redundant data from clock definitions for OMAP4 architecture.
> >
> > If the change is evaluated as a positive one, the same 
> approach could
> > be applied in reducing LOCs from other files, which contain 
> monotonous
> > data enumeration.
> 
> Now that I can apply these patches and look at the result, I 
> still have
> the same opinion.  For me, this results in a major loss of 
> readability.

[sp] I agree here. __VA_ARGS__ in most of the macros make it difficult
     to undertsand the containment relation.

     Multiple inclusion of macros within another makes it difficult
     to follow the chain/ sequence.

     Using a set of changes to illustrate issue with scalability of
     the macros as well:

-static const struct clksel dpll_core_m2_div[] = {
-	{ .parent = &dpll_core_ck, .rates = div31_1to31_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL(dpll_core_m2_div, dpll_core_ck, div31_1to31_rates);
...
... many lines below...
...
-static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
-	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-	{ .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
-	{ .parent = NULL },
-};
+DEFINE_CLKSEL2(iva_hsd_byp_clk_mux_sel, sys_clkin_ck, div_iva_hs_clk);

    In DEFINE_CLKSEL() we need to pass the "rate" as argument
    and in DEFINE_CLKSEL2() it isn't because we they are hardcoded
    for current implementation.

    But then,

+#define DEFINE_CLKSEL3(_name, _parent0, _parent1, _parent2)		\
+	static const struct clksel _name[] = {				\
+		{ .parent = &_parent0, .rates = div_1_0_rates },	\
+		{ .parent = &_parent1, .rates = div_1_1_rates },	\
+		{ .parent = &_parent2, .rates = div_1_2_rates },	\
+		{ .parent = NULL },					\
+	}
 
    All these definitions don't scale well.

~sanjeev

> 
> Changes just to make nice diffstats are fine, but not when it impacts
> readability, etc.  Especially since this data will likely be 
> eventually
> moved to device tree, I'd rather see consolidation efforts focused
> elsewhere.
> 
> Kevin
> 
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe 
> linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2011-05-17 15:47 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-05-15 21:45 [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor Vladimir Zapolskiy
2011-05-15 21:45 ` Vladimir Zapolskiy
2011-05-15 21:45 ` [PATCHv2 1/2] [RFC] OMAP4: clock data: shrink " Vladimir Zapolskiy
2011-05-15 21:45   ` Vladimir Zapolskiy
2011-05-15 21:45 ` [PATCHv2 2/2] [RFC] OMAP4: clock data: shrink more clock data Vladimir Zapolskiy
2011-05-15 21:45   ` Vladimir Zapolskiy
2011-05-16  6:53   ` Avinash.H.M.
2011-05-16  6:53     ` Avinash.H.M.
2011-05-16  7:56 ` [PATCHv2 0/2] [RFC] Shrink clock data utilizing preprocessor Sascha Hauer
2011-05-16  7:56   ` Sascha Hauer
2011-05-16 16:25   ` Vladimir Zapolskiy
2011-05-16 16:25     ` Vladimir Zapolskiy
2011-05-17 13:06 ` Kevin Hilman
2011-05-17 13:06   ` Kevin Hilman
2011-05-17 15:47   ` Premi, Sanjeev
2011-05-17 15:47     ` Premi, Sanjeev

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