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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 3/5] drm/i915/bdw: WaProgramL3SqcReg1Default
Date: Fri, 26 Sep 2014 15:03:19 +0300	[thread overview]
Message-ID: <87sijelhbs.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <1411172190-1642-3-git-send-email-rodrigo.vivi@intel.com>

Rodrigo Vivi <rodrigo.vivi@intel.com> writes:

> Program the default initial value of the L3SqcReg1 on BDW for performance
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 3 +++
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 124ea60..8aafa08 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4821,6 +4821,9 @@ enum punit_power_well {
>  #define GEN7_L3SQCREG1				0xB010
>  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
>  
> +#define GEN8_L3SQCREG1				0xB100
> +#define  BDW_WA_L3SQCREG1_DEFAULT		0x00610000
> +

This is the default after reset. I think we want 0x00810000

-Mika

>  #define GEN7_L3CNTLREG1				0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
>  #define  GEN7_L3AGDIS				(1<<19)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1ec3c8f..8a58565 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5811,6 +5811,9 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>  
> +	/* WaProgramL3SqcReg1Default:bdw */
> +	I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
> +

Should we use intel_ring_emit_wa?

-Mika

>  	lpt_init_clock_gating(dev);
>  }
>  
> -- 
> 1.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2014-09-26 12:03 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-20  0:16 [PATCH 1/5] drm/i915: Add IS_BDW_GT3 macro Rodrigo Vivi
2014-09-20  0:16 ` [PATCH 2/5] drm/i915/bdw: WaDisableFenceDestinationToSLM Rodrigo Vivi
2014-09-25 12:37   ` Mika Kuoppala
2014-09-29 12:32     ` Daniel Vetter
2014-09-29 12:49       ` Daniel Vetter
2014-09-30 15:02         ` Mika Kuoppala
2014-09-30 16:27           ` Daniel Vetter
2014-09-20  0:16 ` [PATCH 3/5] drm/i915/bdw: WaProgramL3SqcReg1Default Rodrigo Vivi
2014-09-26 12:03   ` Mika Kuoppala [this message]
2014-09-26 18:32     ` Rodrigo Vivi
2014-09-26 19:06     ` Ville Syrjälä
2014-09-30 15:11       ` [PATCH] " Rodrigo Vivi
2014-10-01 13:46         ` Mika Kuoppala
2014-09-20  0:16 ` [PATCH 4/5] drm/i915: Let number of workarounds more clear Rodrigo Vivi
2014-09-24 22:44   ` [PATCH] " Rodrigo Vivi
2014-09-26 12:22   ` [PATCH 4/5] " Mika Kuoppala
2014-09-26 12:56     ` Jani Nikula
2014-09-26 12:58       ` Chris Wilson
2014-09-26 13:02         ` Damien Lespiau
2014-09-26 14:16       ` Mika Kuoppala
2014-09-26 14:56         ` Chris Wilson
2014-09-30 22:13           ` Rodrigo Vivi
2014-09-20  0:16 ` [PATCH 5/5] drm/i915/bdw: Remove BDW preproduction W/As until C stepping Rodrigo Vivi
2014-09-24 22:46   ` [PATCH] " Rodrigo Vivi
2014-09-30 22:14     ` Rodrigo Vivi
2014-10-01 14:11     ` Mika Kuoppala
2014-10-09 14:11       ` Rodrigo Vivi
2014-10-19 12:14         ` Daniel Vetter
2014-09-29 19:58 ` [PATCH 1/5] drm/i915: Add IS_BDW_GT3 macro Jesse Barnes

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