* [Intel-gfx] [CI 2/3] drm/i915: extract engine WA programming to common resume function
2020-01-31 7:57 [Intel-gfx] [CI 1/3] drm/i915/gt: Skip rmw for masked registers Chris Wilson
@ 2020-01-31 7:57 ` Chris Wilson
2020-01-31 7:57 ` [Intel-gfx] [CI 3/3] drm/i915: Move ringbuffer WAs to engine workaround list Chris Wilson
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-01-31 7:57 UTC (permalink / raw)
To: intel-gfx
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
The workarounds are a common "feature" across gens and submission
mechanisms and we already call the other WA related functions from
common engine ones (<setup/cleanup>_common), so it makes sense to
do the same with WA application. Medium-term, This will help us
reduce the duplication once the GuC resume function is added, but short
term it will also allow us to use the workaround lists for pre-gen8
engine workarounds.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 14 ++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ---
drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++--
5 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 5df003061e44..b36ec1fddc3d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -192,6 +192,8 @@ void intel_engines_free(struct intel_gt *gt);
int intel_engine_init_common(struct intel_engine_cs *engine);
void intel_engine_cleanup_common(struct intel_engine_cs *engine);
+int intel_engine_resume(struct intel_engine_cs *engine);
+
int intel_ring_submission_setup(struct intel_engine_cs *engine);
int intel_engine_stop_cs(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 86af5edd6933..b1c7b1ed6149 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -841,6 +841,20 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
intel_wa_list_free(&engine->whitelist);
}
+/**
+ * intel_engine_resume - re-initializes the HW state of the engine
+ * @engine: Engine to resume.
+ *
+ * Returns zero on success or an error code on failure.
+ */
+int intel_engine_resume(struct intel_engine_cs *engine)
+{
+ intel_engine_apply_workarounds(engine);
+ intel_engine_apply_whitelist(engine);
+
+ return engine->resume(engine);
+}
+
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index d1c2f034296a..8b653c0f5e5f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -216,7 +216,7 @@ int intel_gt_resume(struct intel_gt *gt)
intel_engine_pm_get(engine);
engine->serial++; /* kernel context lost */
- err = engine->resume(engine);
+ err = intel_engine_resume(engine);
intel_engine_pm_put(engine);
if (err) {
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 5906fc7df2a4..c196fb90c59f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3435,9 +3435,6 @@ static bool unexpected_starting_state(struct intel_engine_cs *engine)
static int execlists_resume(struct intel_engine_cs *engine)
{
- intel_engine_apply_workarounds(engine);
- intel_engine_apply_whitelist(engine);
-
intel_mocs_init_engine(engine);
intel_engine_reset_breadcrumbs(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index d77a1a32da78..a8317e046f81 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -986,7 +986,7 @@ static int resume(struct intel_gt *gt)
int ret;
for_each_engine(engine, gt, id) {
- ret = engine->resume(engine);
+ ret = intel_engine_resume(engine);
if (ret)
return ret;
}
@@ -1161,7 +1161,7 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
* have been reset to their default values. Follow the init_ring
* process to program RING_MODE, HWSP and re-enable submission.
*/
- ret = engine->resume(engine);
+ ret = intel_engine_resume(engine);
out:
intel_engine_cancel_stop_cs(engine);
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Intel-gfx] [CI 3/3] drm/i915: Move ringbuffer WAs to engine workaround list
2020-01-31 7:57 [Intel-gfx] [CI 1/3] drm/i915/gt: Skip rmw for masked registers Chris Wilson
2020-01-31 7:57 ` [Intel-gfx] [CI 2/3] drm/i915: extract engine WA programming to common resume function Chris Wilson
@ 2020-01-31 7:57 ` Chris Wilson
2020-01-31 9:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915/gt: Skip rmw for masked registers Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-01-31 7:57 UTC (permalink / raw)
To: intel-gfx
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Now that intel_engine_apply_workarounds is called on all gens, we can
use the engine workaround lists for pre-gen8 workarounds as well to be
consistent in the way we handle and dump the WAs.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 37 --------------
drivers/gpu/drm/i915/gt/intel_workarounds.c | 49 ++++++++++++++++++-
2 files changed, 47 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 9aa86ba15ce7..9537d4912225 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -858,43 +858,6 @@ static int rcs_resume(struct intel_engine_cs *engine)
intel_uncore_write(uncore, ECOSKPD,
_MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE));
- /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
- if (IS_GEN_RANGE(i915, 4, 6))
- intel_uncore_write(uncore, MI_MODE,
- _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
-
- /* We need to disable the AsyncFlip performance optimisations in order
- * to use MI_WAIT_FOR_EVENT within the CS. It should already be
- * programmed to '1' on all products.
- *
- * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
- */
- if (IS_GEN_RANGE(i915, 6, 7))
- intel_uncore_write(uncore, MI_MODE,
- _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
-
- /* Required for the hardware to program scanline values for waiting */
- /* WaEnableFlushTlbInvalidationMode:snb */
- if (IS_GEN(i915, 6))
- intel_uncore_write(uncore, GFX_MODE,
- _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
-
- /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
- if (IS_GEN(i915, 7))
- intel_uncore_write(uncore, GFX_MODE_GEN7,
- _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
- _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
-
- if (IS_GEN(i915, 6)) {
- /* From the Sandybridge PRM, volume 1 part 3, page 24:
- * "If this bit is set, STCunit will have LRA as replacement
- * policy. [...] This bit must be reset. LRA replacement
- * policy is not supported."
- */
- intel_uncore_write(uncore, CACHE_MODE_0,
- _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
- }
-
if (IS_GEN_RANGE(i915, 6, 7))
intel_uncore_write(uncore, INSTPM,
_MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e4c2b6d42f46..0520ec93564f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1467,6 +1467,51 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN8_L3SQCREG4,
GEN8_LQSC_FLUSH_COHERENT_LINES);
}
+
+ if (IS_GEN(i915, 7))
+ /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
+ wa_masked_en(wal,
+ GFX_MODE_GEN7,
+ GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
+
+ if (IS_GEN_RANGE(i915, 6, 7))
+ /*
+ * We need to disable the AsyncFlip performance optimisations in
+ * order to use MI_WAIT_FOR_EVENT within the CS. It should
+ * already be programmed to '1' on all products.
+ *
+ * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
+ */
+ wa_masked_en(wal,
+ MI_MODE,
+ ASYNC_FLIP_PERF_DISABLE);
+
+ if (IS_GEN(i915, 6)) {
+ /*
+ * Required for the hardware to program scanline values for
+ * waiting
+ * WaEnableFlushTlbInvalidationMode:snb
+ */
+ wa_masked_en(wal,
+ GFX_MODE,
+ GFX_TLB_INVALIDATE_EXPLICIT);
+
+ /*
+ * From the Sandybridge PRM, volume 1 part 3, page 24:
+ * "If this bit is set, STCunit will have LRA as replacement
+ * policy. [...] This bit must be reset. LRA replacement
+ * policy is not supported."
+ */
+ wa_masked_dis(wal,
+ CACHE_MODE_0,
+ CM0_STC_EVICT_DISABLE_LRA_SNB);
+ }
+
+ if (IS_GEN_RANGE(i915, 4, 6))
+ /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
+ wa_masked_en(wal,
+ MI_MODE,
+ VS_TIMER_DISPATCH);
}
static void
@@ -1485,7 +1530,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static void
engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
- if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))
+ if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
return;
if (engine->class == RENDER_CLASS)
@@ -1498,7 +1543,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
{
struct i915_wa_list *wal = &engine->wa_list;
- if (INTEL_GEN(engine->i915) < 8)
+ if (INTEL_GEN(engine->i915) < 4)
return;
wa_init_start(wal, "engine", engine->name);
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915/gt: Skip rmw for masked registers
2020-01-31 7:57 [Intel-gfx] [CI 1/3] drm/i915/gt: Skip rmw for masked registers Chris Wilson
2020-01-31 7:57 ` [Intel-gfx] [CI 2/3] drm/i915: extract engine WA programming to common resume function Chris Wilson
2020-01-31 7:57 ` [Intel-gfx] [CI 3/3] drm/i915: Move ringbuffer WAs to engine workaround list Chris Wilson
@ 2020-01-31 9:13 ` Patchwork
2020-01-31 11:56 ` Chris Wilson
2020-01-31 11:51 ` [Intel-gfx] [CI 1/3] " Mika Kuoppala
2020-01-31 23:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/gt: Skip rmw for masked registers (rev2) Patchwork
4 siblings, 1 reply; 10+ messages in thread
From: Patchwork @ 2020-01-31 9:13 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gt: Skip rmw for masked registers
URL : https://patchwork.freedesktop.org/series/72804/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7849 -> Patchwork_16350
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16350 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16350, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16350:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_suspend@basic-s0:
- fi-bsw-kefka: NOTRUN -> [TIMEOUT][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-bsw-kefka/igt@gem_exec_suspend@basic-s0.html
Known issues
------------
Here are the changes found in Patchwork_16350 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_blt:
- fi-byt-j1900: [PASS][2] -> [DMESG-FAIL][3] ([i915#725])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7849/fi-byt-j1900/igt@i915_selftest@live_blt.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-byt-j1900/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_execlists:
- fi-icl-y: [PASS][4] -> [DMESG-FAIL][5] ([fdo#108569])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7849/fi-icl-y/igt@i915_selftest@live_execlists.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-icl-y/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gt_heartbeat:
- fi-kbl-guc: [PASS][6] -> [DMESG-FAIL][7] ([fdo#112406])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7849/fi-kbl-guc/igt@i915_selftest@live_gt_heartbeat.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-kbl-guc/igt@i915_selftest@live_gt_heartbeat.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-guc: [PASS][8] -> [INCOMPLETE][9] ([fdo#108569])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7849/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][10] -> [FAIL][11] ([fdo#111096] / [i915#323])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7849/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@i915_selftest@live_blt:
- fi-hsw-4770: [DMESG-FAIL][12] ([i915#553] / [i915#725]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7849/fi-hsw-4770/igt@i915_selftest@live_blt.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-j1900: [DMESG-FAIL][14] ([i915#1052]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7849/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][16] ([i915#217]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7849/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@prime_busy@basic-wait-after-default:
- fi-icl-dsi: [DMESG-WARN][18] ([i915#109]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7849/fi-icl-dsi/igt@prime_busy@basic-wait-after-default.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-icl-dsi/igt@prime_busy@basic-wait-after-default.html
#### Warnings ####
* igt@gem_exec_parallel@contexts:
- fi-byt-j1900: [FAIL][20] ([i915#694]) -> [TIMEOUT][21] ([fdo#112271] / [i915#1084])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7849/fi-byt-j1900/igt@gem_exec_parallel@contexts.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-byt-j1900/igt@gem_exec_parallel@contexts.html
- fi-byt-n2820: [FAIL][22] ([i915#694]) -> [TIMEOUT][23] ([fdo#112271])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7849/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[fdo#112406]: https://bugs.freedesktop.org/show_bug.cgi?id=112406
[i915#1052]: https://gitlab.freedesktop.org/drm/intel/issues/1052
[i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
Participating hosts (43 -> 45)
------------------------------
Additional (7): fi-hsw-peppy fi-skl-6770hq fi-snb-2520m fi-ivb-3770 fi-elk-e7500 fi-bsw-kefka fi-skl-6700k2
Missing (5): fi-icl-1065g7 fi-hsw-4200u fi-byt-squawks fi-bwr-2160 fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7849 -> Patchwork_16350
CI-20190529: 20190529
CI_DRM_7849: b35f634060c22079434e153fbdcc15ef3846ef4d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5407: a9d69f51dadbcbc53527671f87572d05c3370cba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16350: b6b81a75697328ed5c7ceb4ccde130773693a3c3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b6b81a756973 drm/i915: Move ringbuffer WAs to engine workaround list
30bdce314ce4 drm/i915: extract engine WA programming to common resume function
b013d4ba346f drm/i915/gt: Skip rmw for masked registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16350/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [Intel-gfx] [CI 1/3] drm/i915/gt: Skip rmw for masked registers
2020-01-31 7:57 [Intel-gfx] [CI 1/3] drm/i915/gt: Skip rmw for masked registers Chris Wilson
` (2 preceding siblings ...)
2020-01-31 9:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915/gt: Skip rmw for masked registers Patchwork
@ 2020-01-31 11:51 ` Mika Kuoppala
2020-01-31 11:55 ` Chris Wilson
2020-01-31 23:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/gt: Skip rmw for masked registers (rev2) Patchwork
4 siblings, 1 reply; 10+ messages in thread
From: Mika Kuoppala @ 2020-01-31 11:51 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> A masked register does not need rmw to update, and it is best not to use
> such a sequence.
>
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++++++++++++++-------
> 1 file changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5a7db279f702..e4c2b6d42f46 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -116,7 +116,8 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
> } else {
> wa_ = &wal->list[mid];
>
> - if ((wa->mask & ~wa_->mask) == 0) {
> + if ((wa->mask | wa_->mask) &&
Don't we want to discard if someone tries to demote a masked
one into a plain?
-Mika
> + (wa->mask & ~wa_->mask) == 0) {
> DRM_ERROR("Discarding overwritten w/a for reg %04x (mask: %08x, value: %08x)\n",
> i915_mmio_reg_offset(wa_->reg),
> wa_->mask, wa_->val);
> @@ -167,12 +168,6 @@ wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> wa_add(wal, reg, mask, val, mask);
> }
>
> -static void
> -wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> -{
> - wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val));
> -}
> -
> static void
> wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> {
> @@ -185,14 +180,26 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> wa_write_masked_or(wal, reg, val, val);
> }
>
> +static void
> +wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> +{
> + wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val);
> +}
> +
> +static void
> +wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> +{
> + wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val);
> +}
> +
> #define WA_SET_BIT_MASKED(addr, mask) \
> - wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
> + wa_masked_en(wal, (addr), mask)
>
> #define WA_CLR_BIT_MASKED(addr, mask) \
> - wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask))
> + wa_masked_dis(wal, (addr), mask)
>
> #define WA_SET_FIELD_MASKED(addr, mask, value) \
> - wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), (value)))
> + wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value)))
>
> static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> @@ -1020,7 +1027,10 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
> intel_uncore_forcewake_get__locked(uncore, fw);
>
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> - intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
> + if (wa->mask)
> + intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
> + else
> + intel_uncore_write_fw(uncore, wa->reg, wa->val);
> if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> wa_verify(wa,
> intel_uncore_read_fw(uncore, wa->reg),
> --
> 2.25.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [Intel-gfx] [CI 1/3] drm/i915/gt: Skip rmw for masked registers
2020-01-31 11:51 ` [Intel-gfx] [CI 1/3] " Mika Kuoppala
@ 2020-01-31 11:55 ` Chris Wilson
2020-01-31 13:14 ` Mika Kuoppala
0 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2020-01-31 11:55 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-01-31 11:51:44)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > A masked register does not need rmw to update, and it is best not to use
> > such a sequence.
> >
> > Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++++++++++++++-------
> > 1 file changed, 21 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 5a7db279f702..e4c2b6d42f46 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -116,7 +116,8 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
> > } else {
> > wa_ = &wal->list[mid];
> >
> > - if ((wa->mask & ~wa_->mask) == 0) {
> > + if ((wa->mask | wa_->mask) &&
>
> Don't we want to discard if someone tries to demote a masked
> one into a plain?
That should throw the error, right?
If either used a mask and now we don't, then 0 & x == 0 => DRM_ERROR.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [Intel-gfx] [CI 1/3] drm/i915/gt: Skip rmw for masked registers
2020-01-31 11:55 ` Chris Wilson
@ 2020-01-31 13:14 ` Mika Kuoppala
2020-01-31 13:18 ` Chris Wilson
0 siblings, 1 reply; 10+ messages in thread
From: Mika Kuoppala @ 2020-01-31 13:14 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2020-01-31 11:51:44)
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>>
>> > A masked register does not need rmw to update, and it is best not to use
>> > such a sequence.
>> >
>> > Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++++++++++++++-------
>> > 1 file changed, 21 insertions(+), 11 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > index 5a7db279f702..e4c2b6d42f46 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > @@ -116,7 +116,8 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
>> > } else {
>> > wa_ = &wal->list[mid];
>> >
>> > - if ((wa->mask & ~wa_->mask) == 0) {
>> > + if ((wa->mask | wa_->mask) &&
>>
>> Don't we want to discard if someone tries to demote a masked
>> one into a plain?
>
> That should throw the error, right?
>
> If either used a mask and now we don't, then 0 & x == 0 => DRM_ERROR.
Yes, it will throw the error. My mistake.
But if we have a mask, we should not allow nonmasked additions
aswell? So mask == 0 would always be masked register and you
can't mix.
-Mika
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [Intel-gfx] [CI 1/3] drm/i915/gt: Skip rmw for masked registers
2020-01-31 13:14 ` Mika Kuoppala
@ 2020-01-31 13:18 ` Chris Wilson
0 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-01-31 13:18 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-01-31 13:14:38)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Quoting Mika Kuoppala (2020-01-31 11:51:44)
> >> Chris Wilson <chris@chris-wilson.co.uk> writes:
> >>
> >> > A masked register does not need rmw to update, and it is best not to use
> >> > such a sequence.
> >> >
> >> > Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++++++++++++++-------
> >> > 1 file changed, 21 insertions(+), 11 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> > index 5a7db279f702..e4c2b6d42f46 100644
> >> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> > @@ -116,7 +116,8 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
> >> > } else {
> >> > wa_ = &wal->list[mid];
> >> >
> >> > - if ((wa->mask & ~wa_->mask) == 0) {
> >> > + if ((wa->mask | wa_->mask) &&
> >>
> >> Don't we want to discard if someone tries to demote a masked
> >> one into a plain?
> >
> > That should throw the error, right?
> >
> > If either used a mask and now we don't, then 0 & x == 0 => DRM_ERROR.
>
> Yes, it will throw the error. My mistake.
>
> But if we have a mask, we should not allow nonmasked additions
> aswell? So mask == 0 would always be masked register and you
> can't mix.
Indeed. We do not want rmw on masked registers. Some might say wa->mask
is a misnomer ;)
-Chris
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/gt: Skip rmw for masked registers (rev2)
2020-01-31 7:57 [Intel-gfx] [CI 1/3] drm/i915/gt: Skip rmw for masked registers Chris Wilson
` (3 preceding siblings ...)
2020-01-31 11:51 ` [Intel-gfx] [CI 1/3] " Mika Kuoppala
@ 2020-01-31 23:15 ` Patchwork
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-01-31 23:15 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gt: Skip rmw for masked registers (rev2)
URL : https://patchwork.freedesktop.org/series/72804/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7853 -> Patchwork_16362
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/index.html
Known issues
------------
Here are the changes found in Patchwork_16362 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_execlists:
- fi-apl-guc: [PASS][1] -> [TIMEOUT][2] ([i915#529])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-apl-guc/igt@i915_selftest@live_execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-apl-guc/igt@i915_selftest@live_execlists.html
#### Possible fixes ####
* igt@gem_close_race@basic-threads:
- fi-byt-n2820: [TIMEOUT][3] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-byt-n2820/igt@gem_close_race@basic-threads.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-byt-n2820/igt@gem_close_race@basic-threads.html
* igt@gem_exec_suspend@basic-s3:
- fi-icl-u2: [FAIL][5] ([fdo#103375]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-icl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u2: [FAIL][7] ([fdo#111550]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-icl-u2/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_selftest@live_execlists:
- fi-icl-y: [DMESG-FAIL][9] ([fdo#108569]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-y/igt@i915_selftest@live_execlists.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-icl-y/igt@i915_selftest@live_execlists.html
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [FAIL][11] ([i915#579]) -> [SKIP][12] ([fdo#109271])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770: [DMESG-FAIL][13] ([i915#563]) -> [DMESG-FAIL][14] ([i915#725])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-hsw-4770/igt@i915_selftest@live_blt.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [FAIL][15] ([fdo#103375]) -> [DMESG-WARN][16] ([IGT#4] / [i915#263])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][17] ([fdo#111096] / [i915#323]) -> [FAIL][18] ([fdo#111407])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7853/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
[i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#529]: https://gitlab.freedesktop.org/drm/intel/issues/529
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
Participating hosts (47 -> 41)
------------------------------
Additional (5): fi-cfl-8109u fi-skl-6600u fi-kbl-7560u fi-skl-6700k2 fi-snb-2600
Missing (11): fi-ilk-m540 fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-kbl-x1275 fi-ivb-3770 fi-blb-e6850 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7853 -> Patchwork_16362
CI-20190529: 20190529
CI_DRM_7853: 1df04205c16923e525efe9c26d6e98612d38c9b3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5409: 93aefe6baa3fabf8c0cabe83e185f7b8f8d8753d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16362: f9fa1507c7966bf46af2c080cb662190bd1ae837 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f9fa1507c796 drm/i915: Move ringbuffer WAs to engine workaround list
2c8907d75021 drm/i915: extract engine WA programming to common resume function
6b04ccbd1830 drm/i915/gt: Skip rmw for masked registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16362/index.html
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^ permalink raw reply [flat|nested] 10+ messages in thread