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From: Yoshinori Sato <ysato@users.sourceforge.jp>
To: "Philippe Mathieu-Daudé" <philmd@redhat.com>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org,
	richard.henderson@linaro.org
Subject: Re: [Qemu-devel] [PATCH RFC v6 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers
Date: Sun, 14 Apr 2019 23:55:32 +0900	[thread overview]
Message-ID: <87tvf0d4bf.wl-ysato@users.sourceforge.jp> (raw)
In-Reply-To: <09399349-5134-7347-b86d-d28c9fd1803d@redhat.com>

On Thu, 11 Apr 2019 19:09:38 +0900,
Philippe Mathieu-Daudé wrote:
> 
> Hi Yoshinori,
> 
> Note about the patch subject:
> - typo in regiserfields (missing 't') -> registerfields
> - I'd simply use "hw/registerfields: Add 8bit and 16bit register macros"

OK.

> On 4/1/19 4:03 PM, Yoshinori Sato wrote:
> > Some RX peripheral using 8bit and 16bit registers.
> > Added 8bit and 16bit APIs.
> > 
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > ---
> >  include/hw/registerfields.h | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
> > index 2659a58737..f6bf911990 100644
> > --- a/include/hw/registerfields.h
> > +++ b/include/hw/registerfields.h
> > @@ -22,6 +22,14 @@
> >      enum { A_ ## reg = (addr) };                                          \
> >      enum { R_ ## reg = (addr) / 4 };
> >  
> > +#define REG8(reg, addr)                                                  \
> > +    enum { A_ ## reg = (addr) };                                          \
> > +    enum { R_ ## reg = (addr) };
> > +
> > +#define REG16(reg, addr)                                                  \
> > +    enum { A_ ## reg = (addr) };                                          \
> > +    enum { R_ ## reg = (addr) / 2 };
> > +
> >  /* Define SHIFT, LENGTH and MASK constants for a field within a register */
> >  
> >  /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
> > @@ -40,6 +48,8 @@
> >  #define FIELD_EX64(storage, reg, field)                                   \
> >      extract64((storage), R_ ## reg ## _ ## field ## _SHIFT,               \
> >                R_ ## reg ## _ ## field ## _LENGTH)
> > +#define FIELD_EX8  FIELD_EX32
> > +#define FIELD_EX16 FIELD_EX32
> >  
> >  /* Extract a field from an array of registers */
> >  #define ARRAY_FIELD_EX32(regs, reg, field)                                \
> 
> For completeness, what about adding FIELD_DP8() and FIELD_DP16()?

I did not add it because I did not use it.
Certainly it is strange that there is no these, so I will add it.
As the registerfields support is incomplete, we will fix it together.

> Regards,
> 
> Phil.
> 

-- 
Yosinori Sato

WARNING: multiple messages have this Message-ID (diff)
From: Yoshinori Sato <ysato@users.sourceforge.jp>
To: "Philippe Mathieu-Daudé" <philmd@redhat.com>
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
	qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH RFC v6 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers
Date: Sun, 14 Apr 2019 23:55:32 +0900	[thread overview]
Message-ID: <87tvf0d4bf.wl-ysato@users.sourceforge.jp> (raw)
Message-ID: <20190414145532.rIkjDlzpR_eP2iwoNR1kMulzkG3kBfJmAWcyv116tXY@z> (raw)
In-Reply-To: <09399349-5134-7347-b86d-d28c9fd1803d@redhat.com>

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="UTF-8", Size: 2295 bytes --]

On Thu, 11 Apr 2019 19:09:38 +0900,
Philippe Mathieu-Daudé wrote:
> 
> Hi Yoshinori,
> 
> Note about the patch subject:
> - typo in regiserfields (missing 't') -> registerfields
> - I'd simply use "hw/registerfields: Add 8bit and 16bit register macros"

OK.

> On 4/1/19 4:03 PM, Yoshinori Sato wrote:
> > Some RX peripheral using 8bit and 16bit registers.
> > Added 8bit and 16bit APIs.
> > 
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > ---
> >  include/hw/registerfields.h | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
> > index 2659a58737..f6bf911990 100644
> > --- a/include/hw/registerfields.h
> > +++ b/include/hw/registerfields.h
> > @@ -22,6 +22,14 @@
> >      enum { A_ ## reg = (addr) };                                          \
> >      enum { R_ ## reg = (addr) / 4 };
> >  
> > +#define REG8(reg, addr)                                                  \
> > +    enum { A_ ## reg = (addr) };                                          \
> > +    enum { R_ ## reg = (addr) };
> > +
> > +#define REG16(reg, addr)                                                  \
> > +    enum { A_ ## reg = (addr) };                                          \
> > +    enum { R_ ## reg = (addr) / 2 };
> > +
> >  /* Define SHIFT, LENGTH and MASK constants for a field within a register */
> >  
> >  /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
> > @@ -40,6 +48,8 @@
> >  #define FIELD_EX64(storage, reg, field)                                   \
> >      extract64((storage), R_ ## reg ## _ ## field ## _SHIFT,               \
> >                R_ ## reg ## _ ## field ## _LENGTH)
> > +#define FIELD_EX8  FIELD_EX32
> > +#define FIELD_EX16 FIELD_EX32
> >  
> >  /* Extract a field from an array of registers */
> >  #define ARRAY_FIELD_EX32(regs, reg, field)                                \
> 
> For completeness, what about adding FIELD_DP8() and FIELD_DP16()?

I did not add it because I did not use it.
Certainly it is strange that there is no these, so I will add it.
As the registerfields support is incomplete, we will fix it together.

> Regards,
> 
> Phil.
> 

-- 
Yosinori Sato


  reply	other threads:[~2019-04-14 14:55 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20190325090047.122981-1-ysato@users.sourceforge.jp>
2019-04-01 14:03 ` [Qemu-devel] [PATCH RFC v6 00/12] Add RX archtecture support Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 01/12] target/rx: TCG translation Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 02/12] target/rx: TCG helper Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 03/12] target/rx: CPU definition Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 04/12] target/rx: RX disassembler Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 05/12] target/rx: Miscellaneous files Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 06/12] hw/intc: RX62N interrupt controller (ICUa) Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 07/12] hw/timer: RX62N internal timer modules Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 08/12] hw/char: RX62N serical communication interface (SCI) Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 09/12] hw/rx: RX Target hardware definition Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 10/12] Add rx-softmmu Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 11/12] MAINTAINERS: Add RX Yoshinori Sato
2019-04-01 14:03   ` [Qemu-devel] [PATCH RFC v6 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers Yoshinori Sato
2019-04-11 10:09     ` Philippe Mathieu-Daudé
2019-04-14 14:55       ` Yoshinori Sato [this message]
2019-04-14 14:55         ` Yoshinori Sato
2019-04-01 15:35   ` [Qemu-devel] [PATCH RFC v6 00/12] Add RX archtecture support no-reply
2019-04-11 10:15   ` Philippe Mathieu-Daudé
2019-04-12 13:27     ` Yoshinori Sato
2019-04-12 13:27       ` Yoshinori Sato

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