* [PATCH 00/20] DSC misc fixes
@ 2023-08-10 13:02 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:02 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
This series is an attempt to address multiple issues with DSC,
scattered in separate existing series.
Patches 1-4 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
https://patchwork.freedesktop.org/series/107550/
Patches 5-6 are from series DSC fixes for Bigjoiner:
https://patchwork.freedesktop.org/series/115773/
Patches 7-17 are based on series to add DSC fractional BPP support:
https://patchwork.freedesktop.org/series/111391/
Patch 20 is to fix compressed bpc for MST DSC, from Stan's series :
https://patchwork.freedesktop.org/series/116179/
Rev2: Addressed review comments from Stan, Ville.
Rev3: Split larger patches. Separate out common helpers.
Rev4: Rebased, fixed checkpatch warnings.
Rev5: Addressed review comments from Stan.
Added a patch to check if forced dsc format can be used before forcing.
Rev6: Addressed review comments from Stan.
Rev7: Reordered and rebased.
Ankit Nautiyal (19):
drm/i915/dp: Consider output_format while computing dsc bpp
drm/i915/dp: Move compressed bpp check with 420 format inside the
helper
drm/i915/dp_mst: Use output_format to get the final link bpp
drm/i915/dp: Use consistent name for link bpp and compressed bpp
drm/i915/dp: Update Bigjoiner interface bits for computing compressed
bpp
drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
drm/i915/dp: Remove extra logs for printing DSC info
drm/display/dp: Fix the DP DSC Receiver cap size
drm/i915/dp: Avoid forcing DSC BPC for MST case
drm/i915/dp: Add functions to get min/max src input bpc with DSC
drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
drm/i915/dp: Avoid left shift of DSC output bpp by 4
drm/i915/dp: Rename helper to get DSC max pipe_bpp
drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with
DSC
drm/i915/dp: Separate out function to get compressed bpp with joiner
drm/i915/dp: Get optimal link config to have best compressed bpp
drm/i915/dp: Check src/sink compressed bpp limit for edp
drm/i915/dp: Check if force_dsc_output_format is possible
Stanislav Lisovskiy (1):
drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
info
drivers/gpu/drm/i915/display/intel_cdclk.c | 59 +-
drivers/gpu/drm/i915/display/intel_dp.c | 655 ++++++++++++++++----
drivers/gpu/drm/i915/display/intel_dp.h | 20 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 80 +--
include/drm/display/drm_dp.h | 2 +-
5 files changed, 625 insertions(+), 191 deletions(-)
--
2.40.1
^ permalink raw reply [flat|nested] 53+ messages in thread* [Intel-gfx] [PATCH 01/20] drm/i915/dp: Consider output_format while computing dsc bpp
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v2: Use output_bpp instead for pipe_bpp to clamp compressed_bpp. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 12bd2f322e62..f138dfa5a2a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -744,6 +744,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
bool bigjoiner,
+ enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots)
{
@@ -768,6 +769,10 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
bits_per_pixel = ((link_clock * lane_count) * timeslots) /
(intel_dp_mode_to_fec_clock(mode_clock) * 8);
+ /* Bandwidth required for 420 is half, that of 444 format */
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel *= 2;
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1161,11 +1166,16 @@ intel_dp_mode_valid(struct drm_connector *_connector,
if (HAS_DSC(dev_priv) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ enum intel_output_format sink_format, output_format;
+ int pipe_bpp;
+
+ sink_format = intel_dp_sink_format(connector, mode);
+ output_format = intel_dp_output_format(connector, sink_format);
/*
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
/*
* Output bpp is stored in 6.4 format so right shift by 4 to get the
@@ -1185,6 +1195,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
+ output_format,
pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
@@ -1724,6 +1735,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
pipe_bpp,
timeslots);
/*
@@ -1759,9 +1771,12 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* calculation procedure is bit different for MST case.
*/
if (compute_pipe_bpp) {
+ u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
+ pipe_config->pipe_bpp);
+
pipe_config->dsc.compressed_bpp = min_t(u16,
dsc_max_output_bpp >> 4,
- pipe_config->pipe_bpp);
+ output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 22099de3ca45..bb4f976af296 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -111,6 +111,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
bool bigjoiner,
+ enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e3f176a093d2..aa8d9d570626 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -973,6 +973,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
target_clock,
mode->hdisplay,
bigjoiner,
+ INTEL_OUTPUT_FORMAT_RGB,
pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 01/20] drm/i915/dp: Consider output_format while computing dsc bpp
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
While using DSC the compressed bpp is computed assuming RGB output
format. Consider the output_format and compute the compressed bpp
during mode valid and compute config steps.
For DP-MST we currently use RGB output format only, so continue
using RGB while computing compressed bpp for MST case.
v2: Use output_bpp instead for pipe_bpp to clamp compressed_bpp. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 12bd2f322e62..f138dfa5a2a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -744,6 +744,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
bool bigjoiner,
+ enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots)
{
@@ -768,6 +769,10 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
bits_per_pixel = ((link_clock * lane_count) * timeslots) /
(intel_dp_mode_to_fec_clock(mode_clock) * 8);
+ /* Bandwidth required for 420 is half, that of 444 format */
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel *= 2;
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1161,11 +1166,16 @@ intel_dp_mode_valid(struct drm_connector *_connector,
if (HAS_DSC(dev_priv) &&
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ enum intel_output_format sink_format, output_format;
+ int pipe_bpp;
+
+ sink_format = intel_dp_sink_format(connector, mode);
+ output_format = intel_dp_output_format(connector, sink_format);
/*
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
/*
* Output bpp is stored in 6.4 format so right shift by 4 to get the
@@ -1185,6 +1195,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
+ output_format,
pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
@@ -1724,6 +1735,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_clock,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
pipe_bpp,
timeslots);
/*
@@ -1759,9 +1771,12 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* calculation procedure is bit different for MST case.
*/
if (compute_pipe_bpp) {
+ u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
+ pipe_config->pipe_bpp);
+
pipe_config->dsc.compressed_bpp = min_t(u16,
dsc_max_output_bpp >> 4,
- pipe_config->pipe_bpp);
+ output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 22099de3ca45..bb4f976af296 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -111,6 +111,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
bool bigjoiner,
+ enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e3f176a093d2..aa8d9d570626 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -973,6 +973,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
target_clock,
mode->hdisplay,
bigjoiner,
+ INTEL_OUTPUT_FORMAT_RGB,
pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 02/20] drm/i915/dp: Move compressed bpp check with 420 format inside the helper
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
Move the check for limiting compressed bite_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f138dfa5a2a2..6bb8fa4a3c96 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -773,6 +773,15 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
bits_per_pixel *= 2;
+ /*
+ * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
+ * supported PPS value can be 63.9375 and with the further
+ * mention that for 420, 422 formats, bpp should be programmed double
+ * the target bpp restricting our target bpp to be 31.9375 at max.
+ */
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel = min_t(u32, bits_per_pixel, 31);
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1738,15 +1747,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->output_format,
pipe_bpp,
timeslots);
- /*
- * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
- * supported PPS value can be 63.9375 and with the further
- * mention that bpp should be programmed double the target bpp
- * restricting our target bpp to be 31.9375 at max
- */
- if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
-
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 02/20] drm/i915/dp: Move compressed bpp check with 420 format inside the helper
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Move the check for limiting compressed bite_per_pixel for 420,422
formats in the helper to compute bits_per_pixel.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f138dfa5a2a2..6bb8fa4a3c96 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -773,6 +773,15 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
bits_per_pixel *= 2;
+ /*
+ * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
+ * supported PPS value can be 63.9375 and with the further
+ * mention that for 420, 422 formats, bpp should be programmed double
+ * the target bpp restricting our target bpp to be 31.9375 at max.
+ */
+ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ bits_per_pixel = min_t(u32, bits_per_pixel, 31);
+
drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
"total bw %u pixel clock %u\n",
bits_per_pixel, timeslots,
@@ -1738,15 +1747,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->output_format,
pipe_bpp,
timeslots);
- /*
- * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
- * supported PPS value can be 63.9375 and with the further
- * mention that bpp should be programmed double the target bpp
- * restricting our target bpp to be 31.9375 at max
- */
- if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
-
if (!dsc_max_output_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 03/20] drm/i915/dp_mst: Use output_format to get the final link bpp
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++++-
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6bb8fa4a3c96..0252cce76519 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -965,7 +965,7 @@ int intel_dp_min_bpp(enum intel_output_format output_format)
return 8 * 3;
}
-static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
{
/*
* bpp value was assumed to RGB format. And YCbCr 4:2:0 output
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index bb4f976af296..7dd015385054 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -144,5 +144,6 @@ void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
void intel_dp_phy_test(struct intel_encoder *encoder);
void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index aa8d9d570626..ef5375eb923e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -155,6 +155,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
int slots = -EINVAL;
+ int link_bpp;
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
limits->min_bpp, limits,
@@ -163,7 +164,9 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
if (slots < 0)
return slots;
- intel_link_compute_m_n(crtc_state->pipe_bpp,
+ link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
+
+ intel_link_compute_m_n(link_bpp,
crtc_state->lane_count,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 03/20] drm/i915/dp_mst: Use output_format to get the final link bpp
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
The final link bpp used to calculate the m_n values depend on the
output_format. Though the output_format is set to RGB for MST case and
the link bpp will be same as the pipe bpp, for the sake of semantics,
lets calculate the m_n values with the link bpp, instead of pipe_bpp.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++++-
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6bb8fa4a3c96..0252cce76519 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -965,7 +965,7 @@ int intel_dp_min_bpp(enum intel_output_format output_format)
return 8 * 3;
}
-static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
{
/*
* bpp value was assumed to RGB format. And YCbCr 4:2:0 output
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index bb4f976af296..7dd015385054 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -144,5 +144,6 @@ void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
void intel_dp_phy_test(struct intel_encoder *encoder);
void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
+int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index aa8d9d570626..ef5375eb923e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -155,6 +155,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
int slots = -EINVAL;
+ int link_bpp;
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
limits->min_bpp, limits,
@@ -163,7 +164,9 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
if (slots < 0)
return slots;
- intel_link_compute_m_n(crtc_state->pipe_bpp,
+ link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
+
+ intel_link_compute_m_n(link_bpp,
crtc_state->lane_count,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 04/20] drm/i915/dp: Use consistent name for link bpp and compressed bpp
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
For 444 sampling without DSC:
link_bpp = output_bpp = pipe_bpp
For 420 sampling without DSC:
output_bpp = pipe_bpp / 2
link_bpp = output_bpp
For 444 sampling with DSC:
output_bpp = pipe_bpp
link_bpp = compressed_bpp, computed with output_bpp (i.e. pipe_bpp in
this case)
For 420 sampling with DSC:
output_bpp = pipe_bpp/2
link_bpp = compressed_bpp, computed with output_bpp
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 84 ++++++++++-----------
drivers/gpu/drm/i915/display/intel_dp.h | 14 ++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++---
3 files changed, 60 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0252cce76519..35608b9de573 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -740,13 +740,13 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- enum intel_output_format output_format,
- u32 pipe_bpp,
- u32 timeslots)
+u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ enum intel_output_format output_format,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
@@ -1136,7 +1136,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk = dev_priv->max_dotclk_freq;
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_slice_count = 0;
enum drm_mode_status status;
bool dsc = false, bigjoiner = false;
@@ -1191,21 +1191,21 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* integer value since we support only integer values of bpp.
*/
if (intel_dp_is_edp(intel_dp)) {
- dsc_max_output_bpp =
+ dsc_max_compressed_bpp =
drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- output_format,
- pipe_bpp, 64) >> 4;
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ output_format,
+ pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1213,7 +1213,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
bigjoiner);
}
- dsc = dsc_max_output_bpp && dsc_slice_count;
+ dsc = dsc_max_compressed_bpp && dsc_slice_count;
}
/*
@@ -1502,9 +1502,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
int mode_rate, link_rate, link_avail;
for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
- int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
+ int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
- mode_rate = intel_dp_link_required(clock, output_bpp);
+ mode_rate = intel_dp_link_required(clock, link_bpp);
for (i = 0; i < intel_dp->num_common_rates; i++) {
link_rate = intel_dp_common_rate(intel_dp, i);
@@ -1733,21 +1733,21 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
} else {
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_dp_slice_count;
if (compute_pipe_bpp) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_bpp,
- timeslots);
- if (!dsc_max_output_bpp) {
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ pipe_config->port_clock,
+ pipe_config->lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
+ pipe_bpp,
+ timeslots);
+ if (!dsc_max_compressed_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
return -EINVAL;
@@ -1775,7 +1775,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp);
pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_output_bpp >> 4,
+ dsc_max_compressed_bpp >> 4,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
@@ -2151,7 +2151,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
static void
intel_dp_drrs_compute_config(struct intel_connector *connector,
struct intel_crtc_state *pipe_config,
- int output_bpp)
+ int link_bpp)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
const struct drm_display_mode *downclock_mode =
@@ -2176,7 +2176,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
if (pipe_config->splitter.enable)
pixel_clock /= pipe_config->splitter.link_count;
- intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
+ intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
pipe_config->port_clock, &pipe_config->dp_m2_n2,
pipe_config->fec_enable);
@@ -2274,7 +2274,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
const struct drm_display_mode *fixed_mode;
struct intel_connector *connector = intel_dp->attached_connector;
- int ret = 0, output_bpp;
+ int ret = 0, link_bpp;
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
pipe_config->has_pch_encoder = true;
@@ -2324,10 +2324,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_limited_color_range(pipe_config, conn_state);
if (pipe_config->dsc.compression_enable)
- output_bpp = pipe_config->dsc.compressed_bpp;
+ link_bpp = pipe_config->dsc.compressed_bpp;
else
- output_bpp = intel_dp_output_bpp(pipe_config->output_format,
- pipe_config->pipe_bpp);
+ link_bpp = intel_dp_output_bpp(pipe_config->output_format,
+ pipe_config->pipe_bpp);
if (intel_dp->mso_link_count) {
int n = intel_dp->mso_link_count;
@@ -2351,7 +2351,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
- intel_link_compute_m_n(output_bpp,
+ intel_link_compute_m_n(link_bpp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
@@ -2367,7 +2367,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_vrr_compute_config(pipe_config, conn_state);
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
- intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
+ intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 7dd015385054..6fd423463f5c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -107,13 +107,13 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- enum intel_output_format output_format,
- u32 pipe_bpp,
- u32 timeslots);
+u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ enum intel_output_format output_format,
+ u32 pipe_bpp,
+ u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index ef5375eb923e..1f00713fb1ad 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -915,7 +915,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
int max_rate, mode_rate, max_lanes, max_link_clock;
int ret;
bool dsc = false, bigjoiner = false;
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_slice_count = 0;
int target_clock = mode->clock;
@@ -969,15 +969,15 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- INTEL_OUTPUT_FORMAT_RGB,
- pipe_bpp, 64) >> 4;
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ INTEL_OUTPUT_FORMAT_RGB,
+ pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -985,7 +985,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
bigjoiner);
}
- dsc = dsc_max_output_bpp && dsc_slice_count;
+ dsc = dsc_max_compressed_bpp && dsc_slice_count;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 04/20] drm/i915/dp: Use consistent name for link bpp and compressed bpp
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Currently there are many places where we use output_bpp for link bpp and
compressed bpp.
Lets use consistent naming:
output_bpp : The intermediate value taking into account the
output_format chroma subsampling.
compressed_bpp : target bpp for the DSC encoder.
link_bpp : final bpp used in the link.
For 444 sampling without DSC:
link_bpp = output_bpp = pipe_bpp
For 420 sampling without DSC:
output_bpp = pipe_bpp / 2
link_bpp = output_bpp
For 444 sampling with DSC:
output_bpp = pipe_bpp
link_bpp = compressed_bpp, computed with output_bpp (i.e. pipe_bpp in
this case)
For 420 sampling with DSC:
output_bpp = pipe_bpp/2
link_bpp = compressed_bpp, computed with output_bpp
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 84 ++++++++++-----------
drivers/gpu/drm/i915/display/intel_dp.h | 14 ++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++---
3 files changed, 60 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0252cce76519..35608b9de573 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -740,13 +740,13 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- enum intel_output_format output_format,
- u32 pipe_bpp,
- u32 timeslots)
+u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ enum intel_output_format output_format,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
@@ -1136,7 +1136,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
int max_dotclk = dev_priv->max_dotclk_freq;
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_slice_count = 0;
enum drm_mode_status status;
bool dsc = false, bigjoiner = false;
@@ -1191,21 +1191,21 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* integer value since we support only integer values of bpp.
*/
if (intel_dp_is_edp(intel_dp)) {
- dsc_max_output_bpp =
+ dsc_max_compressed_bpp =
drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
dsc_slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- output_format,
- pipe_bpp, 64) >> 4;
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ output_format,
+ pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1213,7 +1213,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
bigjoiner);
}
- dsc = dsc_max_output_bpp && dsc_slice_count;
+ dsc = dsc_max_compressed_bpp && dsc_slice_count;
}
/*
@@ -1502,9 +1502,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
int mode_rate, link_rate, link_avail;
for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
- int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
+ int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
- mode_rate = intel_dp_link_required(clock, output_bpp);
+ mode_rate = intel_dp_link_required(clock, link_bpp);
for (i = 0; i < intel_dp->num_common_rates; i++) {
link_rate = intel_dp_common_rate(intel_dp, i);
@@ -1733,21 +1733,21 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
} else {
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_dp_slice_count;
if (compute_pipe_bpp) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_bpp,
- timeslots);
- if (!dsc_max_output_bpp) {
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ pipe_config->port_clock,
+ pipe_config->lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
+ pipe_bpp,
+ timeslots);
+ if (!dsc_max_compressed_bpp) {
drm_dbg_kms(&dev_priv->drm,
"Compressed BPP not supported\n");
return -EINVAL;
@@ -1775,7 +1775,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp);
pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_output_bpp >> 4,
+ dsc_max_compressed_bpp >> 4,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
@@ -2151,7 +2151,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
static void
intel_dp_drrs_compute_config(struct intel_connector *connector,
struct intel_crtc_state *pipe_config,
- int output_bpp)
+ int link_bpp)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
const struct drm_display_mode *downclock_mode =
@@ -2176,7 +2176,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
if (pipe_config->splitter.enable)
pixel_clock /= pipe_config->splitter.link_count;
- intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
+ intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
pipe_config->port_clock, &pipe_config->dp_m2_n2,
pipe_config->fec_enable);
@@ -2274,7 +2274,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
const struct drm_display_mode *fixed_mode;
struct intel_connector *connector = intel_dp->attached_connector;
- int ret = 0, output_bpp;
+ int ret = 0, link_bpp;
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
pipe_config->has_pch_encoder = true;
@@ -2324,10 +2324,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_limited_color_range(pipe_config, conn_state);
if (pipe_config->dsc.compression_enable)
- output_bpp = pipe_config->dsc.compressed_bpp;
+ link_bpp = pipe_config->dsc.compressed_bpp;
else
- output_bpp = intel_dp_output_bpp(pipe_config->output_format,
- pipe_config->pipe_bpp);
+ link_bpp = intel_dp_output_bpp(pipe_config->output_format,
+ pipe_config->pipe_bpp);
if (intel_dp->mso_link_count) {
int n = intel_dp->mso_link_count;
@@ -2351,7 +2351,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
- intel_link_compute_m_n(output_bpp,
+ intel_link_compute_m_n(link_bpp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
@@ -2367,7 +2367,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_vrr_compute_config(pipe_config, conn_state);
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
- intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
+ intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 7dd015385054..6fd423463f5c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -107,13 +107,13 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
-u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- enum intel_output_format output_format,
- u32 pipe_bpp,
- u32 timeslots);
+u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ enum intel_output_format output_format,
+ u32 pipe_bpp,
+ u32 timeslots);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index ef5375eb923e..1f00713fb1ad 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -915,7 +915,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
int max_rate, mode_rate, max_lanes, max_link_clock;
int ret;
bool dsc = false, bigjoiner = false;
- u16 dsc_max_output_bpp = 0;
+ u16 dsc_max_compressed_bpp = 0;
u8 dsc_slice_count = 0;
int target_clock = mode->clock;
@@ -969,15 +969,15 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
- dsc_max_output_bpp =
- intel_dp_dsc_get_output_bpp(dev_priv,
- max_link_clock,
- max_lanes,
- target_clock,
- mode->hdisplay,
- bigjoiner,
- INTEL_OUTPUT_FORMAT_RGB,
- pipe_bpp, 64) >> 4;
+ dsc_max_compressed_bpp =
+ intel_dp_dsc_get_max_compressed_bpp(dev_priv,
+ max_link_clock,
+ max_lanes,
+ target_clock,
+ mode->hdisplay,
+ bigjoiner,
+ INTEL_OUTPUT_FORMAT_RGB,
+ pipe_bpp, 64) >> 4;
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -985,7 +985,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
bigjoiner);
}
- dsc = dsc_max_output_bpp && dsc_slice_count;
+ dsc = dsc_max_compressed_bpp && dsc_slice_count;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 05/20] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
v4: Fix check for display ver. (Ville)
v5: Added note for 2 PPC. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 35608b9de573..fc08fc85d665 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -802,8 +802,11 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
if (bigjoiner) {
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
+ /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
+ int ppc = 2;
u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * 48 /
+ i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
intel_dp_mode_to_fec_clock(mode_clock);
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 05/20] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement. (Ville)
v4: Fix check for display ver. (Ville)
v5: Added note for 2 PPC. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 35608b9de573..fc08fc85d665 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -802,8 +802,11 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
if (bigjoiner) {
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
+ /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
+ int ppc = 2;
u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * 48 /
+ i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
intel_dp_mode_to_fec_clock(mode_clock);
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 06/20] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed later, lets account for Bigjoiner BW
check while calculating Min CDCLK.
v2: Use pixel clock in the bw calculations. (Ville)
v3: Use helper to account for FEC overhead. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 59 +++++++++++++++++-----
1 file changed, 45 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 2fb030b1ff1d..de04a6fe54f3 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -32,6 +32,7 @@
#include "intel_cdclk.h"
#include "intel_crtc.h"
#include "intel_de.h"
+#include "intel_dp.h"
#include "intel_display_types.h"
#include "intel_mchbar_regs.h"
#include "intel_pci_config.h"
@@ -2533,6 +2534,48 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
return min_cdclk;
}
+static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
+ int min_cdclk = 0;
+
+ /*
+ * When we decide to use only one VDSC engine, since
+ * each VDSC operates with 1 ppc throughput, pixel clock
+ * cannot be higher than the VDSC clock (cdclk)
+ * If there 2 VDSC engines, then pixel clock can't be higher than
+ * VDSC clock(cdclk) * 2 and so on.
+ */
+ min_cdclk = max_t(int, min_cdclk,
+ DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
+
+ if (crtc_state->bigjoiner_pipes) {
+ int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
+
+ /*
+ * According to Bigjoiner bw check:
+ * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
+ *
+ * We have already computed compressed_bpp, so now compute the min CDCLK that
+ * is required to support this compressed_bpp.
+ *
+ * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
+ *
+ * Since PPC = 2 with bigjoiner
+ * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
+ */
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
+ int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
+ (2 * bigjoiner_interface_bits);
+
+ min_cdclk = max(min_cdclk, min_cdclk_bj);
+ }
+
+ return min_cdclk;
+}
+
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
@@ -2604,20 +2647,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
- /*
- * When we decide to use only one VDSC engine, since
- * each VDSC operates with 1 ppc throughput, pixel clock
- * cannot be higher than the VDSC clock (cdclk)
- * If there 2 VDSC engines, then pixel clock can't be higher than
- * VDSC clock(cdclk) * 2 and so on.
- */
- if (crtc_state->dsc.compression_enable) {
- int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
-
- min_cdclk = max_t(int, min_cdclk,
- DIV_ROUND_UP(crtc_state->pixel_rate,
- num_vdsc_instances));
- }
+ if (crtc_state->dsc.compression_enable)
+ min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
/*
* HACK. Currently for TGL/DG2 platforms we calculate
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 06/20] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
As per Bsepc:49259, Bigjoiner BW check puts restriction on the
compressed bpp for a given CDCLK, pixelclock in cases where
Bigjoiner + DSC are used.
Currently compressed bpp is computed first, and it is ensured that
the bpp will work at least with the max CDCLK freq.
Since the CDCLK is computed later, lets account for Bigjoiner BW
check while calculating Min CDCLK.
v2: Use pixel clock in the bw calculations. (Ville)
v3: Use helper to account for FEC overhead. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 59 +++++++++++++++++-----
1 file changed, 45 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 2fb030b1ff1d..de04a6fe54f3 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -32,6 +32,7 @@
#include "intel_cdclk.h"
#include "intel_crtc.h"
#include "intel_de.h"
+#include "intel_dp.h"
#include "intel_display_types.h"
#include "intel_mchbar_regs.h"
#include "intel_pci_config.h"
@@ -2533,6 +2534,48 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
return min_cdclk;
}
+static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
+ int min_cdclk = 0;
+
+ /*
+ * When we decide to use only one VDSC engine, since
+ * each VDSC operates with 1 ppc throughput, pixel clock
+ * cannot be higher than the VDSC clock (cdclk)
+ * If there 2 VDSC engines, then pixel clock can't be higher than
+ * VDSC clock(cdclk) * 2 and so on.
+ */
+ min_cdclk = max_t(int, min_cdclk,
+ DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
+
+ if (crtc_state->bigjoiner_pipes) {
+ int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
+
+ /*
+ * According to Bigjoiner bw check:
+ * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
+ *
+ * We have already computed compressed_bpp, so now compute the min CDCLK that
+ * is required to support this compressed_bpp.
+ *
+ * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
+ *
+ * Since PPC = 2 with bigjoiner
+ * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
+ */
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
+ int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
+ (2 * bigjoiner_interface_bits);
+
+ min_cdclk = max(min_cdclk, min_cdclk_bj);
+ }
+
+ return min_cdclk;
+}
+
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv =
@@ -2604,20 +2647,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
- /*
- * When we decide to use only one VDSC engine, since
- * each VDSC operates with 1 ppc throughput, pixel clock
- * cannot be higher than the VDSC clock (cdclk)
- * If there 2 VDSC engines, then pixel clock can't be higher than
- * VDSC clock(cdclk) * 2 and so on.
- */
- if (crtc_state->dsc.compression_enable) {
- int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
-
- min_cdclk = max_t(int, min_cdclk,
- DIV_ROUND_UP(crtc_state->pixel_rate,
- num_vdsc_instances));
- }
+ if (crtc_state->dsc.compression_enable)
+ min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
/*
* HACK. Currently for TGL/DG2 platforms we calculate
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 07/20] drm/i915/dp: Remove extra logs for printing DSC info
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fc08fc85d665..6bded67d986d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1782,9 +1782,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
- drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
- pipe_config->dsc.compressed_bpp,
- pipe_config->dsc.slice_count);
}
/*
* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 07/20] drm/i915/dp: Remove extra logs for printing DSC info
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
DSC compressed bpp and slice counts are already getting printed at the
end of dsc compute config. Remove extra logs.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fc08fc85d665..6bded67d986d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1782,9 +1782,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
- drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n",
- pipe_config->dsc.compressed_bpp,
- pipe_config->dsc.slice_count);
}
/*
* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 08/20] drm/display/dp: Fix the DP DSC Receiver cap size
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: <stable@vger.kernel.org> # v5.0+
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
include/drm/display/drm_dp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 02f2ac4dd2df..e69cece404b3 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1537,7 +1537,7 @@ enum drm_dp_phy {
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
-#define DP_DSC_RECEIVER_CAP_SIZE 0xf
+#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 3
#define DP_LTTPR_COMMON_CAP_SIZE 8
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 08/20] drm/display/dp: Fix the DP DSC Receiver cap size
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh.
Fix the DSC RECEIVER CAP SIZE accordingly.
Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: <stable@vger.kernel.org> # v5.0+
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
include/drm/display/drm_dp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 02f2ac4dd2df..e69cece404b3 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1537,7 +1537,7 @@ enum drm_dp_phy {
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
-#define DP_DSC_RECEIVER_CAP_SIZE 0xf
+#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 3
#define DP_LTTPR_COMMON_CAP_SIZE 8
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 09/20] drm/i915/dp: Avoid forcing DSC BPC for MST case
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
v4: Fix checkpatch longline warning.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6bded67d986d..c13efd0b7c98 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1697,14 +1697,14 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
- if (compute_pipe_bpp)
+ if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
+ pipe_bpp = intel_dp->force_dsc_bpc * 3;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
+ intel_dp->force_dsc_bpc);
+ } else if (compute_pipe_bpp) {
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- else
+ } else {
pipe_bpp = pipe_config->pipe_bpp;
-
- if (intel_dp->force_dsc_bpc) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
}
/* Min Input BPC for ICL+ is 8 */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1f00713fb1ad..dff4717edbd0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -361,6 +361,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
/* enable compression if the mode doesn't fit available BW */
drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
if (ret || intel_dp->force_dsc_en) {
+ /*
+ * FIXME: As bpc is hardcoded to 8, as mentioned above,
+ * WARN and ignore the debug flag force_dsc_bpc for now.
+ */
+ drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");
/*
* Try to get at least some timeslots and then see, if
* we can fit there with DSC.
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 09/20] drm/i915/dp: Avoid forcing DSC BPC for MST case
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
For MST the bpc is hardcoded to 8, and pipe bpp to 24.
So avoid forcing DSC bpc for MST case.
v2: Warn and ignore the debug flag than to bail out. (Jani)
v3: Fix dbg message to mention forced bpc instead of bpp.
v4: Fix checkpatch longline warning.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6bded67d986d..c13efd0b7c98 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1697,14 +1697,14 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
- if (compute_pipe_bpp)
+ if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
+ pipe_bpp = intel_dp->force_dsc_bpc * 3;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
+ intel_dp->force_dsc_bpc);
+ } else if (compute_pipe_bpp) {
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- else
+ } else {
pipe_bpp = pipe_config->pipe_bpp;
-
- if (intel_dp->force_dsc_bpc) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
}
/* Min Input BPC for ICL+ is 8 */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 1f00713fb1ad..dff4717edbd0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -361,6 +361,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
/* enable compression if the mode doesn't fit available BW */
drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
if (ret || intel_dp->force_dsc_en) {
+ /*
+ * FIXME: As bpc is hardcoded to 8, as mentioned above,
+ * WARN and ignore the debug flag force_dsc_bpc for now.
+ */
+ drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");
/*
* Try to get at least some timeslots and then see, if
* we can fit there with DSC.
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 10/20] drm/i915/dp: Add functions to get min/max src input bpc with DSC
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
v2: Use HAS_DSC macro instead of platform check while getting min input
bpc. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 35 +++++++++++++++++++------
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c13efd0b7c98..b414d09b5e80 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1535,6 +1535,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
return -EINVAL;
}
+static
+u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ return 12;
+ if (DISPLAY_VER(i915) == 11)
+ return 10;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1542,11 +1554,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
u8 dsc_bpc[3] = {0};
u8 dsc_max_bpc;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (DISPLAY_VER(i915) >= 12)
- dsc_max_bpc = min_t(u8, 12, max_req_bpc);
- else
- dsc_max_bpc = min_t(u8, 10, max_req_bpc);
+ dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
+
+ if (!dsc_max_bpc)
+ return dsc_max_bpc;
+
+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1674,6 +1687,13 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
}
+static
+u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Min DSC Input BPC for ICL+ is 8 */
+ return HAS_DSC(i915) ? 8 : 0;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1707,10 +1727,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_bpp = pipe_config->pipe_bpp;
}
- /* Min Input BPC for ICL+ is 8 */
- if (pipe_bpp < 8 * 3) {
+ if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
drm_dbg_kms(&dev_priv->drm,
- "No DSC support for less than 8bpc\n");
+ "Computed BPC less than min supported by source for DSC\n");
return -EINVAL;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 10/20] drm/i915/dp: Add functions to get min/max src input bpc with DSC
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Separate out functions for getting maximum and minimum input BPC based
on platforms, when DSC is used.
v2: Use HAS_DSC macro instead of platform check while getting min input
bpc. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 35 +++++++++++++++++++------
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c13efd0b7c98..b414d09b5e80 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1535,6 +1535,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
return -EINVAL;
}
+static
+u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (DISPLAY_VER(i915) >= 12)
+ return 12;
+ if (DISPLAY_VER(i915) == 11)
+ return 10;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1542,11 +1554,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
u8 dsc_bpc[3] = {0};
u8 dsc_max_bpc;
- /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
- if (DISPLAY_VER(i915) >= 12)
- dsc_max_bpc = min_t(u8, 12, max_req_bpc);
- else
- dsc_max_bpc = min_t(u8, 10, max_req_bpc);
+ dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
+
+ if (!dsc_max_bpc)
+ return dsc_max_bpc;
+
+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -1674,6 +1687,13 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
}
+static
+u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
+{
+ /* Min DSC Input BPC for ICL+ is 8 */
+ return HAS_DSC(i915) ? 8 : 0;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1707,10 +1727,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_bpp = pipe_config->pipe_bpp;
}
- /* Min Input BPC for ICL+ is 8 */
- if (pipe_bpp < 8 * 3) {
+ if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
drm_dbg_kms(&dev_priv->drm,
- "No DSC support for less than 8bpc\n");
+ "Computed BPC less than min supported by source for DSC\n");
return -EINVAL;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Intel-gfx] [PATCH 10/20] drm/i915/dp: Add functions to get min/max src input bpc with DSC
2023-08-10 13:03 ` Ankit Nautiyal
@ 2023-08-17 7:58 ` Lisovskiy, Stanislav
-1 siblings, 0 replies; 53+ messages in thread
From: Lisovskiy, Stanislav @ 2023-08-17 7:58 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, dri-devel
On Thu, Aug 10, 2023 at 06:33:09PM +0530, Ankit Nautiyal wrote:
> Separate out functions for getting maximum and minimum input BPC based
> on platforms, when DSC is used.
>
> v2: Use HAS_DSC macro instead of platform check while getting min input
> bpc. (Stan)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 35 +++++++++++++++++++------
> 1 file changed, 27 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index c13efd0b7c98..b414d09b5e80 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1535,6 +1535,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> return -EINVAL;
> }
>
> +static
> +u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
> +{
> + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
> + if (DISPLAY_VER(i915) >= 12)
> + return 12;
> + if (DISPLAY_VER(i915) == 11)
> + return 10;
> +
> + return 0;
> +}
> +
> int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> @@ -1542,11 +1554,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
> u8 dsc_bpc[3] = {0};
> u8 dsc_max_bpc;
>
> - /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
> - if (DISPLAY_VER(i915) >= 12)
> - dsc_max_bpc = min_t(u8, 12, max_req_bpc);
> - else
> - dsc_max_bpc = min_t(u8, 10, max_req_bpc);
> + dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
> +
> + if (!dsc_max_bpc)
> + return dsc_max_bpc;
> +
> + dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
>
> num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
> dsc_bpc);
> @@ -1674,6 +1687,13 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
> return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
> }
>
> +static
> +u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
> +{
> + /* Min DSC Input BPC for ICL+ is 8 */
> + return HAS_DSC(i915) ? 8 : 0;
> +}
> +
> int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state,
> @@ -1707,10 +1727,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> pipe_bpp = pipe_config->pipe_bpp;
> }
>
> - /* Min Input BPC for ICL+ is 8 */
> - if (pipe_bpp < 8 * 3) {
> + if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
> drm_dbg_kms(&dev_priv->drm,
> - "No DSC support for less than 8bpc\n");
> + "Computed BPC less than min supported by source for DSC\n");
> return -EINVAL;
> }
>
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [PATCH 10/20] drm/i915/dp: Add functions to get min/max src input bpc with DSC
@ 2023-08-17 7:58 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 53+ messages in thread
From: Lisovskiy, Stanislav @ 2023-08-17 7:58 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, anusha.srivatsa, dri-devel, navaremanasi
On Thu, Aug 10, 2023 at 06:33:09PM +0530, Ankit Nautiyal wrote:
> Separate out functions for getting maximum and minimum input BPC based
> on platforms, when DSC is used.
>
> v2: Use HAS_DSC macro instead of platform check while getting min input
> bpc. (Stan)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 35 +++++++++++++++++++------
> 1 file changed, 27 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index c13efd0b7c98..b414d09b5e80 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1535,6 +1535,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> return -EINVAL;
> }
>
> +static
> +u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
> +{
> + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
> + if (DISPLAY_VER(i915) >= 12)
> + return 12;
> + if (DISPLAY_VER(i915) == 11)
> + return 10;
> +
> + return 0;
> +}
> +
> int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> @@ -1542,11 +1554,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
> u8 dsc_bpc[3] = {0};
> u8 dsc_max_bpc;
>
> - /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
> - if (DISPLAY_VER(i915) >= 12)
> - dsc_max_bpc = min_t(u8, 12, max_req_bpc);
> - else
> - dsc_max_bpc = min_t(u8, 10, max_req_bpc);
> + dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
> +
> + if (!dsc_max_bpc)
> + return dsc_max_bpc;
> +
> + dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
>
> num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
> dsc_bpc);
> @@ -1674,6 +1687,13 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
> return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
> }
>
> +static
> +u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
> +{
> + /* Min DSC Input BPC for ICL+ is 8 */
> + return HAS_DSC(i915) ? 8 : 0;
> +}
> +
> int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state,
> @@ -1707,10 +1727,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> pipe_bpp = pipe_config->pipe_bpp;
> }
>
> - /* Min Input BPC for ICL+ is 8 */
> - if (pipe_bpp < 8 * 3) {
> + if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
> drm_dbg_kms(&dev_priv->drm,
> - "No DSC support for less than 8bpc\n");
> + "Computed BPC less than min supported by source for DSC\n");
> return -EINVAL;
> }
>
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 11/20] drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not required.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 48 ++++++++++++++++---------
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b414d09b5e80..d0cf0021df70 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1694,6 +1694,12 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
return HAS_DSC(i915) ? 8 : 0;
}
+static
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+{
+ return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1705,7 +1711,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- int pipe_bpp;
int ret;
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1717,28 +1722,37 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
- if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
- intel_dp->force_dsc_bpc);
- } else if (compute_pipe_bpp) {
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- } else {
- pipe_bpp = pipe_config->pipe_bpp;
- }
+ if (compute_pipe_bpp) {
+ int pipe_bpp;
+ int forced_bpp = intel_dp->force_dsc_bpc * 3;
- if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
- drm_dbg_kms(&dev_priv->drm,
- "Computed BPC less than min supported by source for DSC\n");
- return -EINVAL;
+ if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) {
+ pipe_bpp = forced_bpp;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
+ intel_dp->force_dsc_bpc);
+ } else {
+ drm_WARN(&dev_priv->drm, forced_bpp,
+ "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
+ intel_dp->force_dsc_bpc);
+
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
+ conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+
+ pipe_config->pipe_bpp = pipe_bpp;
}
/*
- * For now enable DSC for max bpp, max link rate, max lane count.
+ * For now enable DSC for max link rate, max lane count.
* Optimize this later for the minimum possible link rate/lane count
* with DSC enabled for the requested mode.
*/
- pipe_config->pipe_bpp = pipe_bpp;
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
@@ -1767,7 +1781,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
pipe_config->output_format,
- pipe_bpp,
+ pipe_config->pipe_bpp,
timeslots);
if (!dsc_max_compressed_bpp) {
drm_dbg_kms(&dev_priv->drm,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 11/20] drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24.
Check this condition for cases where bpc is forced by debugfs flag
dsc_force_bpc. If the check fails, then WARN and ignore the debugfs
flag.
For MST case the pipe_bpp is already computed (hardcoded to be 24),
and this check is not required.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 48 ++++++++++++++++---------
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b414d09b5e80..d0cf0021df70 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1694,6 +1694,12 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
return HAS_DSC(i915) ? 8 : 0;
}
+static
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+{
+ return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1705,7 +1711,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- int pipe_bpp;
int ret;
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1717,28 +1722,37 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
- if (intel_dp->force_dsc_bpc && compute_pipe_bpp) {
- pipe_bpp = intel_dp->force_dsc_bpc * 3;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
- intel_dp->force_dsc_bpc);
- } else if (compute_pipe_bpp) {
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
- } else {
- pipe_bpp = pipe_config->pipe_bpp;
- }
+ if (compute_pipe_bpp) {
+ int pipe_bpp;
+ int forced_bpp = intel_dp->force_dsc_bpc * 3;
- if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) {
- drm_dbg_kms(&dev_priv->drm,
- "Computed BPC less than min supported by source for DSC\n");
- return -EINVAL;
+ if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) {
+ pipe_bpp = forced_bpp;
+ drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
+ intel_dp->force_dsc_bpc);
+ } else {
+ drm_WARN(&dev_priv->drm, forced_bpp,
+ "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
+ intel_dp->force_dsc_bpc);
+
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
+ conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+
+ pipe_config->pipe_bpp = pipe_bpp;
}
/*
- * For now enable DSC for max bpp, max link rate, max lane count.
+ * For now enable DSC for max link rate, max lane count.
* Optimize this later for the minimum possible link rate/lane count
* with DSC enabled for the requested mode.
*/
- pipe_config->pipe_bpp = pipe_bpp;
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
@@ -1767,7 +1781,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
adjusted_mode->crtc_hdisplay,
pipe_config->bigjoiner_pipes,
pipe_config->output_format,
- pipe_bpp,
+ pipe_config->pipe_bpp,
timeslots);
if (!dsc_max_compressed_bpp) {
drm_dbg_kms(&dev_priv->drm,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 12/20] drm/i915/dp: Avoid left shift of DSC output bpp by 4
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++-------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d0cf0021df70..40ba2069ca69 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -814,11 +814,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
- /*
- * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
- * fractional part is 0
- */
- return bits_per_pixel << 4;
+ return bits_per_pixel;
}
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
@@ -1208,7 +1204,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
mode->hdisplay,
bigjoiner,
output_format,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1811,7 +1807,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp);
pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_compressed_bpp >> 4,
+ dsc_max_compressed_bpp,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index dff4717edbd0..4895d6242915 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -982,7 +982,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
mode->hdisplay,
bigjoiner,
INTEL_OUTPUT_FORMAT_RGB,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH 12/20] drm/i915/dp: Avoid left shift of DSC output bpp by 4
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
To make way for fractional bpp support, avoid left shifting the
output_bpp by 4 in helper intel_dp_dsc_get_output_bpp.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++-------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d0cf0021df70..40ba2069ca69 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -814,11 +814,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
- /*
- * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
- * fractional part is 0
- */
- return bits_per_pixel << 4;
+ return bits_per_pixel;
}
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
@@ -1208,7 +1204,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
mode->hdisplay,
bigjoiner,
output_format,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
@@ -1811,7 +1807,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
pipe_config->pipe_bpp);
pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_compressed_bpp >> 4,
+ dsc_max_compressed_bpp,
output_bpp);
}
pipe_config->dsc.slice_count = dsc_dp_slice_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index dff4717edbd0..4895d6242915 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -982,7 +982,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
mode->hdisplay,
bigjoiner,
INTEL_OUTPUT_FORMAT_RGB,
- pipe_bpp, 64) >> 4;
+ pipe_bpp, 64);
dsc_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 13/20] drm/i915/dp: Rename helper to get DSC max pipe_bpp
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
The helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the this to reflect that it returns max pipe bpp supported
with DSC.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 40ba2069ca69..fd321b314f91 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1183,7 +1183,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
/*
* Output bpp is stored in 6.4 format so right shift by 4 to get the
@@ -1543,7 +1543,7 @@ u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
return 0;
}
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1731,8 +1731,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
"Cannot force DSC BPC:%d, due to DSC BPC limits\n",
intel_dp->force_dsc_bpc);
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
- conn_state->max_requested_bpc);
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+ conn_state->max_requested_bpc);
if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6fd423463f5c..788a577ebe16 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -106,7 +106,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4895d6242915..3eb085fbc7c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -971,7 +971,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_compressed_bpp =
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 13/20] drm/i915/dp: Rename helper to get DSC max pipe_bpp
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
The helper intel_dp_dsc_compute_bpp gives the maximum
pipe bpp that is allowed with DSC.
Rename the this to reflect that it returns max pipe bpp supported
with DSC.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 40ba2069ca69..fd321b314f91 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1183,7 +1183,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
/*
* Output bpp is stored in 6.4 format so right shift by 4 to get the
@@ -1543,7 +1543,7 @@ u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
return 0;
}
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int i, num_bpc;
@@ -1731,8 +1731,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
"Cannot force DSC BPC:%d, due to DSC BPC limits\n",
intel_dp->force_dsc_bpc);
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
- conn_state->max_requested_bpc);
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+ conn_state->max_requested_bpc);
if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 6fd423463f5c..788a577ebe16 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -106,7 +106,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
unsigned int type);
bool intel_digital_port_connected(struct intel_encoder *encoder);
-int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 4895d6242915..3eb085fbc7c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -971,7 +971,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
* TBD pass the connector BPC,
* for now U8_MAX so that max BPC on that platform would be picked
*/
- int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+ int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX);
if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
dsc_max_compressed_bpp =
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 14/20] drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
v2: Fix checkpatch warning.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 191 ++++++++++++++++--------
1 file changed, 126 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fd321b314f91..f4870c9b0db6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1696,6 +1696,115 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
}
+static
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int forced_bpp;
+
+ if (!intel_dp->force_dsc_bpc)
+ return 0;
+
+ forced_bpp = intel_dp->force_dsc_bpc * 3;
+
+ if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
+ return forced_bpp;
+ }
+
+ drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
+ intel_dp->force_dsc_bpc);
+
+ return 0;
+}
+
+static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 output_bpp, dsc_max_compressed_bpp = 0;
+ int forced_bpp, pipe_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+ /*
+ * For now enable DSC for max link rate, max lane count.
+ * Optimize this later for the minimum possible link rate/lane count
+ * with DSC enabled for the requested mode.
+ */
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
+ pipe_config->port_clock,
+ pipe_config->lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
+ pipe_bpp,
+ timeslots);
+ if (!dsc_max_compressed_bpp) {
+ drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
+ return -EINVAL;
+ }
+
+ output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
+
+ pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp);
+
+ pipe_config->pipe_bpp = pipe_bpp;
+
+ return 0;
+}
+
+static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int pipe_bpp, forced_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ /* For eDP use max bpp that can be supported with DSC. */
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+ conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ pipe_config->dsc.compressed_bpp =
+ min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
+ pipe_bpp);
+
+ pipe_config->pipe_bpp = pipe_bpp;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1718,44 +1827,28 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
+ /*
+ * compute pipe bpp is set to false for DP MST DSC case
+ * and compressed_bpp is calculated same time once
+ * vpci timeslots are allocated, because overall bpp
+ * calculation procedure is bit different for MST case.
+ */
if (compute_pipe_bpp) {
- int pipe_bpp;
- int forced_bpp = intel_dp->force_dsc_bpc * 3;
-
- if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) {
- pipe_bpp = forced_bpp;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
- intel_dp->force_dsc_bpc);
- } else {
- drm_WARN(&dev_priv->drm, forced_bpp,
- "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
- intel_dp->force_dsc_bpc);
-
- pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
- conn_state->max_requested_bpc);
-
- if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
- drm_dbg_kms(&dev_priv->drm,
- "Computed BPC less than min supported by source for DSC\n");
- return -EINVAL;
- }
+ if (intel_dp_is_edp(intel_dp))
+ ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
+ conn_state, limits);
+ else
+ ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
+ conn_state, limits, timeslots);
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No Valid pipe bpp for given mode ret = %d\n", ret);
+ return ret;
}
-
- pipe_config->pipe_bpp = pipe_bpp;
}
- /*
- * For now enable DSC for max link rate, max lane count.
- * Optimize this later for the minimum possible link rate/lane count
- * with DSC enabled for the requested mode.
- */
- pipe_config->port_clock = limits->max_rate;
- pipe_config->lane_count = limits->max_lane_count;
-
+ /* Calculate Slice count */
if (intel_dp_is_edp(intel_dp)) {
- pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
- pipe_config->pipe_bpp);
pipe_config->dsc.slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
@@ -1765,26 +1858,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
} else {
- u16 dsc_max_compressed_bpp = 0;
u8 dsc_dp_slice_count;
- if (compute_pipe_bpp) {
- dsc_max_compressed_bpp =
- intel_dp_dsc_get_max_compressed_bpp(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_config->pipe_bpp,
- timeslots);
- if (!dsc_max_compressed_bpp) {
- drm_dbg_kms(&dev_priv->drm,
- "Compressed BPP not supported\n");
- return -EINVAL;
- }
- }
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
@@ -1796,20 +1871,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
- /*
- * compute pipe bpp is set to false for DP MST DSC case
- * and compressed_bpp is calculated same time once
- * vpci timeslots are allocated, because overall bpp
- * calculation procedure is bit different for MST case.
- */
- if (compute_pipe_bpp) {
- u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
- pipe_config->pipe_bpp);
-
- pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_compressed_bpp,
- output_bpp);
- }
pipe_config->dsc.slice_count = dsc_dp_slice_count;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 14/20] drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
v2: Fix checkpatch warning.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 191 ++++++++++++++++--------
1 file changed, 126 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fd321b314f91..f4870c9b0db6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1696,6 +1696,115 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
}
+static
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int forced_bpp;
+
+ if (!intel_dp->force_dsc_bpc)
+ return 0;
+
+ forced_bpp = intel_dp->force_dsc_bpc * 3;
+
+ if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
+ return forced_bpp;
+ }
+
+ drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
+ intel_dp->force_dsc_bpc);
+
+ return 0;
+}
+
+static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 output_bpp, dsc_max_compressed_bpp = 0;
+ int forced_bpp, pipe_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+ /*
+ * For now enable DSC for max link rate, max lane count.
+ * Optimize this later for the minimum possible link rate/lane count
+ * with DSC enabled for the requested mode.
+ */
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
+ pipe_config->port_clock,
+ pipe_config->lane_count,
+ adjusted_mode->crtc_clock,
+ adjusted_mode->crtc_hdisplay,
+ pipe_config->bigjoiner_pipes,
+ pipe_config->output_format,
+ pipe_bpp,
+ timeslots);
+ if (!dsc_max_compressed_bpp) {
+ drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
+ return -EINVAL;
+ }
+
+ output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
+
+ pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp);
+
+ pipe_config->pipe_bpp = pipe_bpp;
+
+ return 0;
+}
+
+static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int pipe_bpp, forced_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ /* For eDP use max bpp that can be supported with DSC. */
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+ conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min supported by source for DSC\n");
+ return -EINVAL;
+ }
+ }
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ pipe_config->dsc.compressed_bpp =
+ min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
+ pipe_bpp);
+
+ pipe_config->pipe_bpp = pipe_bpp;
+
+ return 0;
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1718,44 +1827,28 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
return -EINVAL;
+ /*
+ * compute pipe bpp is set to false for DP MST DSC case
+ * and compressed_bpp is calculated same time once
+ * vpci timeslots are allocated, because overall bpp
+ * calculation procedure is bit different for MST case.
+ */
if (compute_pipe_bpp) {
- int pipe_bpp;
- int forced_bpp = intel_dp->force_dsc_bpc * 3;
-
- if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) {
- pipe_bpp = forced_bpp;
- drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n",
- intel_dp->force_dsc_bpc);
- } else {
- drm_WARN(&dev_priv->drm, forced_bpp,
- "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
- intel_dp->force_dsc_bpc);
-
- pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
- conn_state->max_requested_bpc);
-
- if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) {
- drm_dbg_kms(&dev_priv->drm,
- "Computed BPC less than min supported by source for DSC\n");
- return -EINVAL;
- }
+ if (intel_dp_is_edp(intel_dp))
+ ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
+ conn_state, limits);
+ else
+ ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
+ conn_state, limits, timeslots);
+ if (ret) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No Valid pipe bpp for given mode ret = %d\n", ret);
+ return ret;
}
-
- pipe_config->pipe_bpp = pipe_bpp;
}
- /*
- * For now enable DSC for max link rate, max lane count.
- * Optimize this later for the minimum possible link rate/lane count
- * with DSC enabled for the requested mode.
- */
- pipe_config->port_clock = limits->max_rate;
- pipe_config->lane_count = limits->max_lane_count;
-
+ /* Calculate Slice count */
if (intel_dp_is_edp(intel_dp)) {
- pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
- pipe_config->pipe_bpp);
pipe_config->dsc.slice_count =
drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
@@ -1765,26 +1858,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
} else {
- u16 dsc_max_compressed_bpp = 0;
u8 dsc_dp_slice_count;
- if (compute_pipe_bpp) {
- dsc_max_compressed_bpp =
- intel_dp_dsc_get_max_compressed_bpp(dev_priv,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_config->pipe_bpp,
- timeslots);
- if (!dsc_max_compressed_bpp) {
- drm_dbg_kms(&dev_priv->drm,
- "Compressed BPP not supported\n");
- return -EINVAL;
- }
- }
dsc_dp_slice_count =
intel_dp_dsc_get_slice_count(intel_dp,
adjusted_mode->crtc_clock,
@@ -1796,20 +1871,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return -EINVAL;
}
- /*
- * compute pipe bpp is set to false for DP MST DSC case
- * and compressed_bpp is calculated same time once
- * vpci timeslots are allocated, because overall bpp
- * calculation procedure is bit different for MST case.
- */
- if (compute_pipe_bpp) {
- u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
- pipe_config->pipe_bpp);
-
- pipe_config->dsc.compressed_bpp = min_t(u16,
- dsc_max_compressed_bpp,
- output_bpp);
- }
pipe_config->dsc.slice_count = dsc_dp_slice_count;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 15/20] drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with DSC
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
Currently we check if the pipe_bpp selected is >= the
min DSC bpc/bpp requirement. We do not check if it is <= the max DSC
bpc/bpp requirement.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
v2: Fix the commit message.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f4870c9b0db6..67e8a9abe6ce 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1691,13 +1691,27 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
}
static
-bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits,
+ int pipe_bpp)
{
- return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
+ u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
+
+ dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
+ dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+
+ dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
+ dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
+
+ return pipe_bpp >= dsc_min_pipe_bpp &&
+ pipe_bpp <= dsc_max_pipe_bpp;
}
static
-int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int forced_bpp;
@@ -1707,7 +1721,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
forced_bpp = intel_dp->force_dsc_bpc * 3;
- if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
return forced_bpp;
}
@@ -1729,16 +1743,16 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
u16 output_bpp, dsc_max_compressed_bpp = 0;
int forced_bpp, pipe_bpp;
- forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
pipe_bpp = forced_bpp;
} else {
pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
drm_dbg_kms(&i915->drm,
- "Computed BPC less than min supported by source for DSC\n");
+ "Computed BPC is not in DSC BPC limits\n");
return -EINVAL;
}
}
@@ -1780,7 +1794,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int pipe_bpp, forced_bpp;
- forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
pipe_bpp = forced_bpp;
@@ -1788,9 +1802,9 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
/* For eDP use max bpp that can be supported with DSC. */
pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
drm_dbg_kms(&i915->drm,
- "Computed BPC less than min supported by source for DSC\n");
+ "Computed BPC is not in DSC BPC limits\n");
return -EINVAL;
}
}
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 15/20] drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with DSC
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Currently we check if the pipe_bpp selected is >= the
min DSC bpc/bpp requirement. We do not check if it is <= the max DSC
bpc/bpp requirement.
Add checks for max DSC BPC/BPP constraints while computing the
pipe_bpp when DSC is in use.
v2: Fix the commit message.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++--------
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f4870c9b0db6..67e8a9abe6ce 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1691,13 +1691,27 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
}
static
-bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp)
+bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits,
+ int pipe_bpp)
{
- return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
+ u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
+
+ dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
+ dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+
+ dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
+ dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
+
+ return pipe_bpp >= dsc_min_pipe_bpp &&
+ pipe_bpp <= dsc_max_pipe_bpp;
}
static
-int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
+ struct drm_connector_state *conn_state,
+ struct link_config_limits *limits)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int forced_bpp;
@@ -1707,7 +1721,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
forced_bpp = intel_dp->force_dsc_bpc * 3;
- if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
return forced_bpp;
}
@@ -1729,16 +1743,16 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
u16 output_bpp, dsc_max_compressed_bpp = 0;
int forced_bpp, pipe_bpp;
- forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
pipe_bpp = forced_bpp;
} else {
pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
drm_dbg_kms(&i915->drm,
- "Computed BPC less than min supported by source for DSC\n");
+ "Computed BPC is not in DSC BPC limits\n");
return -EINVAL;
}
}
@@ -1780,7 +1794,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int pipe_bpp, forced_bpp;
- forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
pipe_bpp = forced_bpp;
@@ -1788,9 +1802,9 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
/* For eDP use max bpp that can be supported with DSC. */
pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
conn_state->max_requested_bpc);
- if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
drm_dbg_kms(&i915->drm,
- "Computed BPC less than min supported by source for DSC\n");
+ "Computed BPC is not in DSC BPC limits\n");
return -EINVAL;
}
}
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 16/20] drm/i915/dp: Separate out function to get compressed bpp with joiner
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 54 ++++++++++++++-----------
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 67e8a9abe6ce..6901ab809587 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -740,6 +740,32 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
+static
+u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner)
+{
+ u32 max_bpp_small_joiner_ram;
+
+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
+ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
+
+ if (bigjoiner) {
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
+ /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
+ int ppc = 2;
+ u32 max_bpp_bigjoiner =
+ i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
+ intel_dp_mode_to_fec_clock(mode_clock);
+
+ max_bpp_small_joiner_ram *= 2;
+
+ return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
+ }
+
+ return max_bpp_small_joiner_ram;
+}
+
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
@@ -748,7 +774,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 pipe_bpp,
u32 timeslots)
{
- u32 bits_per_pixel, max_bpp_small_joiner_ram;
+ u32 bits_per_pixel, joiner_max_bpp;
/*
* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
@@ -788,29 +814,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
(link_clock * lane_count * 8),
intel_dp_mode_to_fec_clock(mode_clock));
- /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
- max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
- mode_hdisplay;
-
- if (bigjoiner)
- max_bpp_small_joiner_ram *= 2;
-
- /*
- * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
- * check, output bpp from small joiner RAM check)
- */
- bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
-
- if (bigjoiner) {
- int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
- /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
- int ppc = 2;
- u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
- intel_dp_mode_to_fec_clock(mode_clock);
-
- bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
- }
+ joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
+ mode_hdisplay, bigjoiner);
+ bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 16/20] drm/i915/dp: Separate out function to get compressed bpp with joiner
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Pull the code to get joiner constraints on maximum compressed bpp into
separate function.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 54 ++++++++++++++-----------
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 67e8a9abe6ce..6901ab809587 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -740,6 +740,32 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
+static
+u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner)
+{
+ u32 max_bpp_small_joiner_ram;
+
+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
+ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
+
+ if (bigjoiner) {
+ int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
+ /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
+ int ppc = 2;
+ u32 max_bpp_bigjoiner =
+ i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
+ intel_dp_mode_to_fec_clock(mode_clock);
+
+ max_bpp_small_joiner_ram *= 2;
+
+ return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
+ }
+
+ return max_bpp_small_joiner_ram;
+}
+
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
@@ -748,7 +774,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 pipe_bpp,
u32 timeslots)
{
- u32 bits_per_pixel, max_bpp_small_joiner_ram;
+ u32 bits_per_pixel, joiner_max_bpp;
/*
* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
@@ -788,29 +814,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
(link_clock * lane_count * 8),
intel_dp_mode_to_fec_clock(mode_clock));
- /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
- max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
- mode_hdisplay;
-
- if (bigjoiner)
- max_bpp_small_joiner_ram *= 2;
-
- /*
- * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
- * check, output bpp from small joiner RAM check)
- */
- bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
-
- if (bigjoiner) {
- int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
- /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
- int ppc = 2;
- u32 max_bpp_bigjoiner =
- i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
- intel_dp_mode_to_fec_clock(mode_clock);
-
- bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
- }
+ joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
+ mode_hdisplay, bigjoiner);
+ bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 17/20] drm/i915/dp: Get optimal link config to have best compressed bpp
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
-Fix the checks for limits->max/min_bpp while iterating over list of
valid DSC bpcs. (Stan)
v3:
-Refactor the code to have pipe bpp/compressed bpp computation and slice
count calculation separately for different cases.
v4:
-Separate the pipe_bpp calculation for eDP and DP.
v5:
-Get rid of magic numbers for max and min bpp,
and improve documentation. (Stan).
-Use functions for {src_sink}_{min_max}_compressed_bpp (Ville).
v6:
-Remove lines to set link config to max.
v7:
-Split the part to separate edp and dp functions for computing DSC BPP
into separate patch.
v8:
-Separate mechanism to get compressed bpp for ICL,TGL and XELPD+.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 294 +++++++++++++++++++++---
1 file changed, 261 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6901ab809587..196bda630944 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1689,6 +1689,231 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
}
+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+ u32 lane_count, u32 mode_clock,
+ enum intel_output_format output_format,
+ int timeslots)
+{
+ u32 available_bw, required_bw;
+
+ available_bw = (link_clock * lane_count * timeslots) / 8;
+ required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
+
+ return available_bw > required_bw;
+}
+
+static int dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ u16 compressed_bpp,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ int link_rate, lane_count;
+ int i;
+
+ for (i = 0; i < intel_dp->num_common_rates; i++) {
+ link_rate = intel_dp_common_rate(intel_dp, i);
+ if (link_rate < limits->min_rate || link_rate > limits->max_rate)
+ continue;
+
+ for (lane_count = limits->min_lane_count;
+ lane_count <= limits->max_lane_count;
+ lane_count <<= 1) {
+ if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count,
+ adjusted_mode->clock,
+ pipe_config->output_format,
+ timeslots))
+ continue;
+
+ pipe_config->lane_count = lane_count;
+ pipe_config->port_clock = link_rate;
+
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static
+u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
+{
+ u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd);
+
+ if (max_bppx16)
+ return max_bppx16;
+ /*
+ * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
+ * values as given in spec Table 2-157 DP v2.0
+ */
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return (3 * bpc) << 4;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return (3 * (bpc / 2)) << 4;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+{
+ /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return 8;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return 6;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
+{
+ return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp,
+ pipe_config, bpc) >> 4;
+}
+
+static int dsc_src_min_compressed_bpp(void)
+{
+ /* Min Compressed bpp supported by source is 8 */
+ return 8;
+}
+
+static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ /*
+ * Max Compressed bpp for Gen 13+ is 27bpp.
+ * For earlier platform is 23bpp. (Bspec:49259).
+ */
+ if (DISPLAY_VER(i915) <= 12)
+ return 23;
+ else
+ return 27;
+}
+
+/*
+ * From a list of valid compressed bpps try different compressed bpp and find a
+ * suitable link configuration that can support it.
+ */
+static int
+icl_dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int dsc_max_bpp,
+ int dsc_min_bpp,
+ int pipe_bpp,
+ int timeslots)
+{
+ int i, ret;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
+ if (valid_dsc_bpp[i] < dsc_min_bpp ||
+ valid_dsc_bpp[i] > dsc_max_bpp)
+ break;
+
+ ret = dsc_compute_link_config(intel_dp,
+ pipe_config,
+ limits,
+ valid_dsc_bpp[i],
+ timeslots);
+ if (ret == 0) {
+ pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+/*
+ * From XE_LPD onwards we supports compression bpps in steps of 1 up to
+ * uncompressed bpp-1. So we start from max compressed bpp and see if any
+ * link configuration is able to support that compressed bpp, if not we
+ * step down and check for lower compressed bpp.
+ */
+static int
+xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int dsc_max_bpp,
+ int dsc_min_bpp,
+ int pipe_bpp,
+ int timeslots)
+{
+ u16 compressed_bpp;
+ int ret;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ for (compressed_bpp = dsc_max_bpp;
+ compressed_bpp >= dsc_min_bpp;
+ compressed_bpp--) {
+ ret = dsc_compute_link_config(intel_dp,
+ pipe_config,
+ limits,
+ compressed_bpp,
+ timeslots);
+ if (ret == 0) {
+ pipe_config->dsc.compressed_bpp = compressed_bpp;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int pipe_bpp,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
+ int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+ int dsc_joiner_max_bpp;
+
+ dsc_src_min_bpp = dsc_src_min_compressed_bpp();
+ dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
+
+ dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
+ dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+
+ dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
+ adjusted_mode->hdisplay,
+ pipe_config->bigjoiner_pipes);
+ dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
+
+ if (DISPLAY_VER(i915) >= 13)
+ return xelpd_dsc_compute_link_config(intel_dp, pipe_config, limits,
+ dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
+ return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
+ dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
+}
+
static
u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
{
@@ -1744,52 +1969,55 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
struct link_config_limits *limits,
int timeslots)
{
- const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- u16 output_bpp, dsc_max_compressed_bpp = 0;
+ u8 max_req_bpc = conn_state->max_requested_bpc;
+ u8 dsc_max_bpc, dsc_max_bpp;
+ u8 dsc_min_bpc, dsc_min_bpp;
+ u8 dsc_bpc[3] = {0};
int forced_bpp, pipe_bpp;
+ int num_bpc, i, ret;
forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
- pipe_bpp = forced_bpp;
- } else {
- pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
-
- if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
- drm_dbg_kms(&i915->drm,
- "Computed BPC is not in DSC BPC limits\n");
- return -EINVAL;
+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, forced_bpp, timeslots);
+ if (ret == 0) {
+ pipe_config->pipe_bpp = forced_bpp;
+ return 0;
}
}
- /*
- * For now enable DSC for max link rate, max lane count.
- * Optimize this later for the minimum possible link rate/lane count
- * with DSC enabled for the requested mode.
- */
- pipe_config->port_clock = limits->max_rate;
- pipe_config->lane_count = limits->max_lane_count;
- dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_bpp,
- timeslots);
- if (!dsc_max_compressed_bpp) {
- drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
+
+ dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+ if (!dsc_max_bpc)
return -EINVAL;
- }
- output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
+ dsc_max_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
- pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp);
+ dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+ dsc_min_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
- pipe_config->pipe_bpp = pipe_bpp;
+ /*
+ * Get the maximum DSC bpc that will be supported by any valid
+ * link configuration and compressed bpp.
+ */
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, dsc_bpc);
+ for (i = 0; i < num_bpc; i++) {
+ pipe_bpp = dsc_bpc[i] * 3;
+ if (pipe_bpp < dsc_min_bpp)
+ break;
+ if (pipe_bpp > dsc_max_bpp)
+ continue;
+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, pipe_bpp, timeslots);
+ if (ret == 0) {
+ pipe_config->pipe_bpp = pipe_bpp;
+ return 0;
+ }
+ }
- return 0;
+ return -EINVAL;
}
static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 17/20] drm/i915/dp: Get optimal link config to have best compressed bpp
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Currently, we take the max lane, rate and pipe bpp, to get the maximum
compressed bpp possible. We then set the output bpp to this value.
This patch provides support to have max bpp, min rate and min lanes,
that can support the min compressed bpp.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
-Fix the checks for limits->max/min_bpp while iterating over list of
valid DSC bpcs. (Stan)
v3:
-Refactor the code to have pipe bpp/compressed bpp computation and slice
count calculation separately for different cases.
v4:
-Separate the pipe_bpp calculation for eDP and DP.
v5:
-Get rid of magic numbers for max and min bpp,
and improve documentation. (Stan).
-Use functions for {src_sink}_{min_max}_compressed_bpp (Ville).
v6:
-Remove lines to set link config to max.
v7:
-Split the part to separate edp and dp functions for computing DSC BPP
into separate patch.
v8:
-Separate mechanism to get compressed bpp for ICL,TGL and XELPD+.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 294 +++++++++++++++++++++---
1 file changed, 261 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6901ab809587..196bda630944 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1689,6 +1689,231 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
}
+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+ u32 lane_count, u32 mode_clock,
+ enum intel_output_format output_format,
+ int timeslots)
+{
+ u32 available_bw, required_bw;
+
+ available_bw = (link_clock * lane_count * timeslots) / 8;
+ required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
+
+ return available_bw > required_bw;
+}
+
+static int dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ u16 compressed_bpp,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ int link_rate, lane_count;
+ int i;
+
+ for (i = 0; i < intel_dp->num_common_rates; i++) {
+ link_rate = intel_dp_common_rate(intel_dp, i);
+ if (link_rate < limits->min_rate || link_rate > limits->max_rate)
+ continue;
+
+ for (lane_count = limits->min_lane_count;
+ lane_count <= limits->max_lane_count;
+ lane_count <<= 1) {
+ if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count,
+ adjusted_mode->clock,
+ pipe_config->output_format,
+ timeslots))
+ continue;
+
+ pipe_config->lane_count = lane_count;
+ pipe_config->port_clock = link_rate;
+
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static
+u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
+{
+ u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd);
+
+ if (max_bppx16)
+ return max_bppx16;
+ /*
+ * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
+ * values as given in spec Table 2-157 DP v2.0
+ */
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return (3 * bpc) << 4;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return (3 * (bpc / 2)) << 4;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+{
+ /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
+ switch (pipe_config->output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return 8;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ return 6;
+ default:
+ MISSING_CASE(pipe_config->output_format);
+ break;
+ }
+
+ return 0;
+}
+
+static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
+{
+ return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp,
+ pipe_config, bpc) >> 4;
+}
+
+static int dsc_src_min_compressed_bpp(void)
+{
+ /* Min Compressed bpp supported by source is 8 */
+ return 8;
+}
+
+static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ /*
+ * Max Compressed bpp for Gen 13+ is 27bpp.
+ * For earlier platform is 23bpp. (Bspec:49259).
+ */
+ if (DISPLAY_VER(i915) <= 12)
+ return 23;
+ else
+ return 27;
+}
+
+/*
+ * From a list of valid compressed bpps try different compressed bpp and find a
+ * suitable link configuration that can support it.
+ */
+static int
+icl_dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int dsc_max_bpp,
+ int dsc_min_bpp,
+ int pipe_bpp,
+ int timeslots)
+{
+ int i, ret;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
+ if (valid_dsc_bpp[i] < dsc_min_bpp ||
+ valid_dsc_bpp[i] > dsc_max_bpp)
+ break;
+
+ ret = dsc_compute_link_config(intel_dp,
+ pipe_config,
+ limits,
+ valid_dsc_bpp[i],
+ timeslots);
+ if (ret == 0) {
+ pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+/*
+ * From XE_LPD onwards we supports compression bpps in steps of 1 up to
+ * uncompressed bpp-1. So we start from max compressed bpp and see if any
+ * link configuration is able to support that compressed bpp, if not we
+ * step down and check for lower compressed bpp.
+ */
+static int
+xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int dsc_max_bpp,
+ int dsc_min_bpp,
+ int pipe_bpp,
+ int timeslots)
+{
+ u16 compressed_bpp;
+ int ret;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ for (compressed_bpp = dsc_max_bpp;
+ compressed_bpp >= dsc_min_bpp;
+ compressed_bpp--) {
+ ret = dsc_compute_link_config(intel_dp,
+ pipe_config,
+ limits,
+ compressed_bpp,
+ timeslots);
+ if (ret == 0) {
+ pipe_config->dsc.compressed_bpp = compressed_bpp;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct link_config_limits *limits,
+ int pipe_bpp,
+ int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
+ int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
+ int dsc_joiner_max_bpp;
+
+ dsc_src_min_bpp = dsc_src_min_compressed_bpp();
+ dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
+
+ dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
+ dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+
+ dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
+ adjusted_mode->hdisplay,
+ pipe_config->bigjoiner_pipes);
+ dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
+
+ if (DISPLAY_VER(i915) >= 13)
+ return xelpd_dsc_compute_link_config(intel_dp, pipe_config, limits,
+ dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
+ return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
+ dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
+}
+
static
u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
{
@@ -1744,52 +1969,55 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
struct link_config_limits *limits,
int timeslots)
{
- const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- u16 output_bpp, dsc_max_compressed_bpp = 0;
+ u8 max_req_bpc = conn_state->max_requested_bpc;
+ u8 dsc_max_bpc, dsc_max_bpp;
+ u8 dsc_min_bpc, dsc_min_bpp;
+ u8 dsc_bpc[3] = {0};
int forced_bpp, pipe_bpp;
+ int num_bpc, i, ret;
forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
if (forced_bpp) {
- pipe_bpp = forced_bpp;
- } else {
- pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc);
-
- if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
- drm_dbg_kms(&i915->drm,
- "Computed BPC is not in DSC BPC limits\n");
- return -EINVAL;
+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, forced_bpp, timeslots);
+ if (ret == 0) {
+ pipe_config->pipe_bpp = forced_bpp;
+ return 0;
}
}
- /*
- * For now enable DSC for max link rate, max lane count.
- * Optimize this later for the minimum possible link rate/lane count
- * with DSC enabled for the requested mode.
- */
- pipe_config->port_clock = limits->max_rate;
- pipe_config->lane_count = limits->max_lane_count;
- dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
- pipe_config->port_clock,
- pipe_config->lane_count,
- adjusted_mode->crtc_clock,
- adjusted_mode->crtc_hdisplay,
- pipe_config->bigjoiner_pipes,
- pipe_config->output_format,
- pipe_bpp,
- timeslots);
- if (!dsc_max_compressed_bpp) {
- drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
+
+ dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+ if (!dsc_max_bpc)
return -EINVAL;
- }
- output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
+ dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
+ dsc_max_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
- pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp);
+ dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
+ dsc_min_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
- pipe_config->pipe_bpp = pipe_bpp;
+ /*
+ * Get the maximum DSC bpc that will be supported by any valid
+ * link configuration and compressed bpp.
+ */
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, dsc_bpc);
+ for (i = 0; i < num_bpc; i++) {
+ pipe_bpp = dsc_bpc[i] * 3;
+ if (pipe_bpp < dsc_min_bpp)
+ break;
+ if (pipe_bpp > dsc_max_bpp)
+ continue;
+ ret = dsc_compute_compressed_bpp(intel_dp, pipe_config,
+ limits, pipe_bpp, timeslots);
+ if (ret == 0) {
+ pipe_config->pipe_bpp = pipe_bpp;
+ return 0;
+ }
+ }
- return 0;
+ return -EINVAL;
}
static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 18/20] drm/i915/dp: Check src/sink compressed bpp limit for edp
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
Use checks for src and sink limits before computing compressed bpp for
eDP.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 196bda630944..8c2e5393c6ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2027,6 +2027,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int pipe_bpp, forced_bpp;
+ int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
+ int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
@@ -2044,9 +2046,19 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
}
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
- pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
- pipe_bpp);
+
+ dsc_src_min_bpp = dsc_src_min_compressed_bpp();
+ dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
+
+ dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
+ dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);
pipe_config->pipe_bpp = pipe_bpp;
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 18/20] drm/i915/dp: Check src/sink compressed bpp limit for edp
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Use checks for src and sink limits before computing compressed bpp for
eDP.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 196bda630944..8c2e5393c6ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2027,6 +2027,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int pipe_bpp, forced_bpp;
+ int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
+ int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
@@ -2044,9 +2046,19 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
}
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
- pipe_config->dsc.compressed_bpp =
- min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
- pipe_bpp);
+
+ dsc_src_min_bpp = dsc_src_min_compressed_bpp();
+ dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
+
+ dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
+ dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+
+ /* Compressed BPP should be less than the Input DSC bpp */
+ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+
+ pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);
pipe_config->pipe_bpp = pipe_bpp;
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 19/20] drm/i915/dp: Check if force_dsc_output_format is possible
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
Currently for testing an output format with DSC, we just force the
output format, without checking if it can be supported.
This also creates an issue where there is a PCON which might need to
convert from forced output format to the format to sink format.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 30 +++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8c2e5393c6ec..9e904bb4ac5c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -935,16 +935,42 @@ dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
return false;
}
+static bool
+dfp_can_convert(struct intel_dp *intel_dp,
+ enum intel_output_format output_format,
+ enum intel_output_format sink_format)
+{
+ switch (output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ return dfp_can_convert_from_rgb(intel_dp, sink_format);
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
+ default:
+ MISSING_CASE(output_format);
+ return false;
+ }
+
+ return false;
+}
+
static enum intel_output_format
intel_dp_output_format(struct intel_connector *connector,
enum intel_output_format sink_format)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ enum intel_output_format force_dsc_output_format =
+ intel_dp->force_dsc_output_format;
enum intel_output_format output_format;
+ if (force_dsc_output_format) {
+ if (source_can_output(intel_dp, force_dsc_output_format) &&
+ (!drm_dp_is_branch(intel_dp->dpcd) ||
+ sink_format != force_dsc_output_format ||
+ dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
+ return force_dsc_output_format;
- if (intel_dp->force_dsc_output_format)
- return intel_dp->force_dsc_output_format;
+ drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
+ }
if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
dfp_can_convert_from_rgb(intel_dp, sink_format))
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 19/20] drm/i915/dp: Check if force_dsc_output_format is possible
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
Currently for testing an output format with DSC, we just force the
output format, without checking if it can be supported.
This also creates an issue where there is a PCON which might need to
convert from forced output format to the format to sink format.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 30 +++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8c2e5393c6ec..9e904bb4ac5c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -935,16 +935,42 @@ dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
return false;
}
+static bool
+dfp_can_convert(struct intel_dp *intel_dp,
+ enum intel_output_format output_format,
+ enum intel_output_format sink_format)
+{
+ switch (output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ return dfp_can_convert_from_rgb(intel_dp, sink_format);
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
+ default:
+ MISSING_CASE(output_format);
+ return false;
+ }
+
+ return false;
+}
+
static enum intel_output_format
intel_dp_output_format(struct intel_connector *connector,
enum intel_output_format sink_format)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ enum intel_output_format force_dsc_output_format =
+ intel_dp->force_dsc_output_format;
enum intel_output_format output_format;
+ if (force_dsc_output_format) {
+ if (source_can_output(intel_dp, force_dsc_output_format) &&
+ (!drm_dp_is_branch(intel_dp->dpcd) ||
+ sink_format != force_dsc_output_format ||
+ dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
+ return force_dsc_output_format;
- if (intel_dp->force_dsc_output_format)
- return intel_dp->force_dsc_output_format;
+ drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
+ }
if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
dfp_can_convert_from_rgb(intel_dp, sink_format))
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 20/20] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-10 13:03 ` Ankit Nautiyal
-1 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
register DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH.
This might also allow us to get rid of an ugly compressed bpp
recalculation, which we had to add to make some MST hubs usable.
v2: - Fix operator precedence
v3: - Added debug info about compressed bpps
v4: - Don't try to intersect Sink input bpp and compressed bpps.
v5: - Decrease step while looking for suitable compressed bpp to
accommodate.
v6: - Use helper for getting min and max compressed_bpp (Ankit)
v7: - Fix checkpatch warning (Ankit)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 +++++----
drivers/gpu/drm/i915/display/intel_dp.h | 4 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++------------
3 files changed, 36 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9e904bb4ac5c..bdaa2249409d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1789,7 +1789,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
return 0;
}
-static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
{
/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
switch (pipe_config->output_format) {
@@ -1806,9 +1806,9 @@ static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
return 0;
}
-static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config,
- int bpc)
+int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
{
return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp,
pipe_config, bpc) >> 4;
@@ -1921,11 +1921,13 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
int dsc_joiner_max_bpp;
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
- dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
- dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp,
+ pipe_config,
+ pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
@@ -2074,11 +2076,13 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
pipe_config->lane_count = limits->max_lane_count;
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
- dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
- dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp,
+ pipe_config,
+ pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
/* Compressed BPP should be less than the Input DSC bpp */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 788a577ebe16..f29e48028f39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -114,6 +114,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
+int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3eb085fbc7c8..06a456517383 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -101,6 +101,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->lane_count);
}
+ drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
+ min_bpp, max_bpp);
+
for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
@@ -194,8 +197,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
u8 dsc_bpc[3] = {0};
int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
u8 dsc_max_bpc;
- bool need_timeslot_recalc = false;
- u32 last_compressed_bpp;
+ int min_compressed_bpp, max_compressed_bpp;
/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
if (DISPLAY_VER(i915) >= 12)
@@ -231,34 +233,25 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
if (max_bpp > sink_max_bpp)
max_bpp = sink_max_bpp;
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
- min_bpp, limits,
- conn_state, 2 * 3, true);
-
- if (slots < 0)
- return slots;
-
- last_compressed_bpp = crtc_state->dsc.compressed_bpp;
+ max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp,
+ crtc_state,
+ max_bpp / 3);
+ min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
+ drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
+ min_compressed_bpp, max_compressed_bpp);
- crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
- last_compressed_bpp,
- crtc_state->pipe_bpp);
+ /* Align compressed bpps according to our own constraints */
+ max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,
+ crtc_state->pipe_bpp);
+ min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
+ crtc_state->pipe_bpp);
- if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
- need_timeslot_recalc = true;
+ slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,
+ min_compressed_bpp, limits,
+ conn_state, 1, true);
- /*
- * Apparently some MST hubs dislike if vcpi slots are not matching precisely
- * the actual compressed bpp we use.
- */
- if (need_timeslot_recalc) {
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
- crtc_state->dsc.compressed_bpp,
- crtc_state->dsc.compressed_bpp,
- limits, conn_state, 2 * 3, true);
- if (slots < 0)
- return slots;
- }
+ if (slots < 0)
+ return slots;
intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
crtc_state->lane_count,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PATCH 20/20] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
@ 2023-08-10 13:03 ` Ankit Nautiyal
0 siblings, 0 replies; 53+ messages in thread
From: Ankit Nautiyal @ 2023-08-10 13:03 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
register DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH.
This might also allow us to get rid of an ugly compressed bpp
recalculation, which we had to add to make some MST hubs usable.
v2: - Fix operator precedence
v3: - Added debug info about compressed bpps
v4: - Don't try to intersect Sink input bpp and compressed bpps.
v5: - Decrease step while looking for suitable compressed bpp to
accommodate.
v6: - Use helper for getting min and max compressed_bpp (Ankit)
v7: - Fix checkpatch warning (Ankit)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 +++++----
drivers/gpu/drm/i915/display/intel_dp.h | 4 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++------------
3 files changed, 36 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9e904bb4ac5c..bdaa2249409d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1789,7 +1789,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp,
return 0;
}
-static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
{
/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
switch (pipe_config->output_format) {
@@ -1806,9 +1806,9 @@ static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
return 0;
}
-static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
- struct intel_crtc_state *pipe_config,
- int bpc)
+int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc)
{
return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp,
pipe_config, bpc) >> 4;
@@ -1921,11 +1921,13 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
int dsc_joiner_max_bpp;
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
- dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
- dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp,
+ pipe_config,
+ pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
@@ -2074,11 +2076,13 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
pipe_config->lane_count = limits->max_lane_count;
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
- dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
+ dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
- dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
+ dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp,
+ pipe_config,
+ pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
/* Compressed BPP should be less than the Input DSC bpp */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 788a577ebe16..f29e48028f39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -114,6 +114,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
enum intel_output_format output_format,
u32 pipe_bpp,
u32 timeslots);
+int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
+int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int bpc);
u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
int mode_clock, int mode_hdisplay,
bool bigjoiner);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3eb085fbc7c8..06a456517383 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -101,6 +101,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->lane_count);
}
+ drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
+ min_bpp, max_bpp);
+
for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
@@ -194,8 +197,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
u8 dsc_bpc[3] = {0};
int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
u8 dsc_max_bpc;
- bool need_timeslot_recalc = false;
- u32 last_compressed_bpp;
+ int min_compressed_bpp, max_compressed_bpp;
/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
if (DISPLAY_VER(i915) >= 12)
@@ -231,34 +233,25 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
if (max_bpp > sink_max_bpp)
max_bpp = sink_max_bpp;
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
- min_bpp, limits,
- conn_state, 2 * 3, true);
-
- if (slots < 0)
- return slots;
-
- last_compressed_bpp = crtc_state->dsc.compressed_bpp;
+ max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp,
+ crtc_state,
+ max_bpp / 3);
+ min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
+ drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
+ min_compressed_bpp, max_compressed_bpp);
- crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
- last_compressed_bpp,
- crtc_state->pipe_bpp);
+ /* Align compressed bpps according to our own constraints */
+ max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,
+ crtc_state->pipe_bpp);
+ min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
+ crtc_state->pipe_bpp);
- if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
- need_timeslot_recalc = true;
+ slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,
+ min_compressed_bpp, limits,
+ conn_state, 1, true);
- /*
- * Apparently some MST hubs dislike if vcpi slots are not matching precisely
- * the actual compressed bpp we use.
- */
- if (need_timeslot_recalc) {
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
- crtc_state->dsc.compressed_bpp,
- crtc_state->dsc.compressed_bpp,
- limits, conn_state, 2 * 3, true);
- if (slots < 0)
- return slots;
- }
+ if (slots < 0)
+ return slots;
intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
crtc_state->lane_count,
--
2.40.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DSC misc fixes (rev7)
2023-08-10 13:02 ` Ankit Nautiyal
` (20 preceding siblings ...)
(?)
@ 2023-08-10 18:43 ` Patchwork
-1 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2023-08-10 18:43 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
== Series Details ==
Series: DSC misc fixes (rev7)
URL : https://patchwork.freedesktop.org/series/117662/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
^ permalink raw reply [flat|nested] 53+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for DSC misc fixes (rev7)
2023-08-10 13:02 ` Ankit Nautiyal
` (21 preceding siblings ...)
(?)
@ 2023-08-10 18:43 ` Patchwork
-1 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2023-08-10 18:43 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
== Series Details ==
Series: DSC misc fixes (rev7)
URL : https://patchwork.freedesktop.org/series/117662/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
^ permalink raw reply [flat|nested] 53+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for DSC misc fixes (rev7)
2023-08-10 13:02 ` Ankit Nautiyal
` (22 preceding siblings ...)
(?)
@ 2023-08-10 18:56 ` Patchwork
-1 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2023-08-10 18:56 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8898 bytes --]
== Series Details ==
Series: DSC misc fixes (rev7)
URL : https://patchwork.freedesktop.org/series/117662/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13500 -> Patchwork_117662v7
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/index.html
Participating hosts (42 -> 41)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_117662v7 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-adlp-11: NOTRUN -> [SKIP][1] ([i915#7456])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-adlp-11/igt@debugfs_test@basic-hwmon.html
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-2: NOTRUN -> [ABORT][2] ([i915#6687] / [i915#7978] / [i915#8668])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-rpls-2/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_tiled_pread_basic:
- bat-adlp-11: NOTRUN -> [SKIP][3] ([i915#3282])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-adlp-11/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-guc: [PASS][4] -> [FAIL][5] ([i915#7940])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/fi-skl-guc/igt@i915_pm_rpm@module-reload.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/fi-skl-guc/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][6] ([i915#6367])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@kms_busy@basic@flip:
- bat-adlp-11: NOTRUN -> [ABORT][7] ([i915#4423])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-adlp-11/igt@kms_busy@basic@flip.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#7828])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-dg2-11/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][9] -> [ABORT][10] ([i915#8442] / [i915#8668])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-bsw-nick: NOTRUN -> [SKIP][11] ([fdo#109271]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/fi-bsw-nick/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@i915_module_load@load:
- bat-adlp-11: [ABORT][12] ([i915#4423]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/bat-adlp-11/igt@i915_module_load@load.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-adlp-11/igt@i915_module_load@load.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-tgl-1115g4: [FAIL][14] ([i915#7940]) -> [PASS][15] +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/fi-tgl-1115g4/igt@i915_pm_rpm@basic-pci-d3-state.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/fi-tgl-1115g4/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- fi-cfl-8109u: [FAIL][16] ([i915#7940]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/fi-cfl-8109u/igt@i915_pm_rpm@basic-rte.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/fi-cfl-8109u/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [ABORT][18] ([i915#7911] / [i915#7913]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_lrc:
- bat-dg2-11: [INCOMPLETE][20] ([i915#7609] / [i915#7913]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@migrate:
- bat-atsm-1: [DMESG-FAIL][22] ([i915#7699] / [i915#7913]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/bat-atsm-1/igt@i915_selftest@live@migrate.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-atsm-1/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [ABORT][24] ([i915#4983] / [i915#7913]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/bat-rpls-2/igt@i915_selftest@live@requests.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-rpls-2/igt@i915_selftest@live@requests.html
- bat-mtlp-6: [DMESG-FAIL][26] ([i915#8497]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/bat-mtlp-6/igt@i915_selftest@live@requests.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/bat-mtlp-6/igt@i915_selftest@live@requests.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
Build changes
-------------
* Linux: CI_DRM_13500 -> Patchwork_117662v7
CI-20190529: 20190529
CI_DRM_13500: 4be6c76008410cf6ada52b25cb4bc4280bc3a3ee @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7426: 67e7470eb79ca386087775d0b1b51c164abbf9c8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117662v7: 4be6c76008410cf6ada52b25cb4bc4280bc3a3ee @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
8985a84b00b6 drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
0bf4fcea4d27 drm/i915/dp: Check if force_dsc_output_format is possible
67c415d8d862 drm/i915/dp: Check src/sink compressed bpp limit for edp
443e975e998e drm/i915/dp: Get optimal link config to have best compressed bpp
008e3cad7cfd drm/i915/dp: Separate out function to get compressed bpp with joiner
c143bb27f8cc drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with DSC
a6053e4e1ca1 drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
5a2c08d792a1 drm/i915/dp: Rename helper to get DSC max pipe_bpp
74a84235d8fa drm/i915/dp: Avoid left shift of DSC output bpp by 4
90d626e8b8d0 drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
b5de45a01e30 drm/i915/dp: Add functions to get min/max src input bpc with DSC
e0c3cd912b7e drm/i915/dp: Avoid forcing DSC BPC for MST case
c839624d0cd9 drm/display/dp: Fix the DP DSC Receiver cap size
20f20c34fe63 drm/i915/dp: Remove extra logs for printing DSC info
7fdf3bb931c6 drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
88a80b198226 drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp
4776350a4c89 drm/i915/dp: Use consistent name for link bpp and compressed bpp
068092f382ed drm/i915/dp_mst: Use output_format to get the final link bpp
82285c064d7d drm/i915/dp: Move compressed bpp check with 420 format inside the helper
249212705d7c drm/i915/dp: Consider output_format while computing dsc bpp
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/index.html
[-- Attachment #2: Type: text/html, Size: 10491 bytes --]
^ permalink raw reply [flat|nested] 53+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for DSC misc fixes (rev7)
2023-08-10 13:02 ` Ankit Nautiyal
` (23 preceding siblings ...)
(?)
@ 2023-08-11 15:36 ` Patchwork
-1 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2023-08-11 15:36 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 63935 bytes --]
== Series Details ==
Series: DSC misc fixes (rev7)
URL : https://patchwork.freedesktop.org/series/117662/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13500_full -> Patchwork_117662v7_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_117662v7_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_117662v7_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_117662v7_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_schedule@preempt-engines@ccs0:
- shard-mtlp: [PASS][1] -> [FAIL][2] +7 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-6/igt@gem_exec_schedule@preempt-engines@ccs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-4/igt@gem_exec_schedule@preempt-engines@ccs0.html
* igt@gem_exec_schedule@preempt-engines@rcs0:
- shard-mtlp: [PASS][3] -> [DMESG-FAIL][4] +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-6/igt@gem_exec_schedule@preempt-engines@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-4/igt@gem_exec_schedule@preempt-engines@rcs0.html
* igt@kms_atomic_transition@plane-all-transition-fencing@pipe-a-hdmi-a-2:
- shard-rkl: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-rkl-4/igt@kms_atomic_transition@plane-all-transition-fencing@pipe-a-hdmi-a-2.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-2/igt@kms_atomic_transition@plane-all-transition-fencing@pipe-a-hdmi-a-2.html
New tests
---------
New tests have been introduced between CI_DRM_13500_full and Patchwork_117662v7_full:
### New IGT tests (6) ###
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-a-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-d-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-dp-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-dp-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-d-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_117662v7_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-dg2: NOTRUN -> [SKIP][7] ([i915#8411])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@drm_fdinfo@most-busy-idle-check-all@vecs1:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#8414]) +21 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@drm_fdinfo@most-busy-idle-check-all@vecs1.html
* igt@drm_mm@drm_mm_test:
- shard-tglu: NOTRUN -> [SKIP][9] ([i915#8661])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@drm_mm@drm_mm_test.html
* igt@feature_discovery@chamelium:
- shard-dg2: NOTRUN -> [SKIP][10] ([i915#4854])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@feature_discovery@chamelium.html
* igt@feature_discovery@display-4x:
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#1839])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@feature_discovery@display-4x.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-tglu: NOTRUN -> [SKIP][12] ([i915#5325])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ctx_persistence@engines-cleanup:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-snb7/igt@gem_ctx_persistence@engines-cleanup.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#8555]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_persistence@smoketest:
- shard-rkl: [PASS][15] -> [FAIL][16] ([i915#5099])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-rkl-2/igt@gem_ctx_persistence@smoketest.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-2/igt@gem_ctx_persistence@smoketest.html
* igt@gem_eio@banned:
- shard-mtlp: [PASS][17] -> [FAIL][18] ([i915#8798])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-8/igt@gem_eio@banned.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-8/igt@gem_eio@banned.html
* igt@gem_eio@hibernate:
- shard-dg2: NOTRUN -> [ABORT][19] ([i915#7975] / [i915#8213])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-2/igt@gem_eio@hibernate.html
* igt@gem_eio@kms:
- shard-dg2: NOTRUN -> [FAIL][20] ([i915#5784])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@gem_eio@kms.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][21] ([i915#8898])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-snb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@bonded-true-hang:
- shard-dg2: NOTRUN -> [SKIP][22] ([i915#4812])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@gem_exec_balancer@bonded-true-hang.html
* igt@gem_exec_capture@pi@ccs0:
- shard-mtlp: [PASS][23] -> [FAIL][24] ([i915#7765])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-3/igt@gem_exec_capture@pi@ccs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@gem_exec_capture@pi@ccs0.html
* igt@gem_exec_capture@pi@vcs1:
- shard-mtlp: [PASS][25] -> [FAIL][26] ([i915#4475] / [i915#7765])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-3/igt@gem_exec_capture@pi@vcs1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@gem_exec_capture@pi@vcs1.html
* igt@gem_exec_endless@dispatch@vcs1:
- shard-tglu: [PASS][27] -> [TIMEOUT][28] ([i915#3778])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-tglu-4/igt@gem_exec_endless@dispatch@vcs1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-8/igt@gem_exec_endless@dispatch@vcs1.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][29] -> [FAIL][30] ([i915#2846])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-glk4/igt@gem_exec_fair@basic-deadline.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-glk8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-rkl: [PASS][31] -> [FAIL][32] ([i915#2842])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-rkl-2/igt@gem_exec_fair@basic-none-share@rcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-1/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: NOTRUN -> [FAIL][33] ([i915#2842])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-dg2: NOTRUN -> [SKIP][34] ([i915#3539] / [i915#4852]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@gem_exec_flush@basic-uc-pro-default.html
* igt@gem_exec_gttfill@multigpu-basic:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#7697])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@gem_exec_gttfill@multigpu-basic.html
* igt@gem_exec_params@secure-non-master:
- shard-dg2: NOTRUN -> [SKIP][36] ([fdo#112283])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@gem_exec_params@secure-non-master.html
* igt@gem_exec_schedule@preempt-queue-chain:
- shard-dg2: NOTRUN -> [SKIP][37] ([i915#4537] / [i915#4812])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@gem_exec_schedule@preempt-queue-chain.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg2: [PASS][38] -> [ABORT][39] ([i915#7975] / [i915#8213])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg2-11/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-1/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@gem_exec_whisper@basic-fds-priority-all:
- shard-tglu: [PASS][40] -> [INCOMPLETE][41] ([i915#6755] / [i915#7392])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-tglu-5/igt@gem_exec_whisper@basic-fds-priority-all.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-3/igt@gem_exec_whisper@basic-fds-priority-all.html
* igt@gem_fence_thrash@bo-write-verify-x:
- shard-dg2: NOTRUN -> [SKIP][42] ([i915#4860])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@gem_fence_thrash@bo-write-verify-x.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][43] ([i915#4860])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-tglu: NOTRUN -> [SKIP][44] ([i915#4613])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: NOTRUN -> [DMESG-WARN][45] ([i915#4936] / [i915#5493])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html
- shard-dg1: [PASS][46] -> [TIMEOUT][47] ([i915#5493])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg1-19/igt@gem_lmem_swapping@smem-oom@lmem0.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#4077]) +9 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_wc@close:
- shard-dg2: NOTRUN -> [SKIP][49] ([i915#4083]) +7 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@gem_mmap_wc@close.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#4270]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@gem_pxp@reject-modify-context-protection-off-3.html
* igt@gem_readwrite@beyond-eob:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#3282]) +8 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@gem_readwrite@beyond-eob.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][52] ([i915#8428])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-ccs.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#4079]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-tglu: NOTRUN -> [SKIP][54] ([fdo#109312])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_spin_batch@user-each:
- shard-mtlp: [PASS][55] -> [DMESG-FAIL][56] ([i915#8962])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-7/igt@gem_spin_batch@user-each.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-4/igt@gem_spin_batch@user-each.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#3297])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@relocations:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#3281]) +9 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@gem_userptr_blits@relocations.html
* igt@gem_workarounds@suspend-resume-context:
- shard-dg2: [PASS][59] -> [FAIL][60] ([fdo#103375])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg2-10/igt@gem_workarounds@suspend-resume-context.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-11/igt@gem_workarounds@suspend-resume-context.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-snb: NOTRUN -> [SKIP][61] ([fdo#109271]) +194 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-snb7/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@bb-oversize:
- shard-tglu: NOTRUN -> [SKIP][62] ([i915#2527] / [i915#2856])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@gen9_exec_parse@bb-oversize.html
* igt@gen9_exec_parse@shadow-peek:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#2856]) +4 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@gen9_exec_parse@shadow-peek.html
* igt@gen9_exec_parse@unaligned-access:
- shard-mtlp: NOTRUN -> [SKIP][64] ([i915#2856])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [PASS][65] -> [ABORT][66] ([i915#8489] / [i915#8668])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-5/igt@i915_module_load@reload-with-fault-injection.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-2/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_backlight@fade-with-suspend:
- shard-dg2: NOTRUN -> [SKIP][67] ([i915#5354] / [i915#7561]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-2/igt@i915_pm_backlight@fade-with-suspend.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-tglu: NOTRUN -> [SKIP][68] ([i915#8399])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#1937])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-11/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rc6_residency@rc6-idle@bcs0:
- shard-dg1: [PASS][70] -> [FAIL][71] ([i915#3591])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-dg2: [PASS][72] -> [SKIP][73] ([i915#1397])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg2-12/igt@i915_pm_rpm@dpms-lpsp.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-11/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [PASS][74] -> [SKIP][75] ([i915#1397])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-rkl-2/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#1397])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-lmem0:
- shard-dg1: [PASS][77] -> [FAIL][78] ([i915#7940]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg1-14/igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-lmem0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-16/igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-lmem0.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-dg1: [PASS][79] -> [SKIP][80] ([i915#1397]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg1-17/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
- shard-tglu: NOTRUN -> [SKIP][81] ([fdo#111644] / [i915#1397])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-dg2: NOTRUN -> [SKIP][82] ([fdo#109506])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_pm_sseu@full-enable:
- shard-dg2: NOTRUN -> [SKIP][83] ([i915#4387])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@hwconfig_table:
- shard-tglu: NOTRUN -> [SKIP][84] ([i915#6245])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@i915_query@hwconfig_table.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#4212])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-rc_ccs-cc:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#8502] / [i915#8709]) +11 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-rc_ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs:
- shard-dg1: NOTRUN -> [SKIP][87] ([i915#8502]) +7 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-17/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][88] ([i915#8247]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-2/igt@kms_async_flips@crc@pipe-a-hdmi-a-2.html
* igt@kms_async_flips@crc@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [FAIL][89] ([i915#8247]) +3 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-6/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-snb: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#1769])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-snb4/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-tglu: NOTRUN -> [SKIP][91] ([fdo#111615] / [i915#5286]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][92] ([fdo#111614]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][93] ([i915#5190]) +12 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#4538] / [i915#5190]) +3 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-mtlp: NOTRUN -> [SKIP][95] ([fdo#111615])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][96] ([fdo#111615]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_ccs:
- shard-mtlp: NOTRUN -> [SKIP][97] ([i915#6095]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#3689] / [i915#5354]) +25 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#3689] / [i915#3886] / [i915#5354]) +10 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_dg2_rc_ccs_cc:
- shard-tglu: NOTRUN -> [SKIP][100] ([i915#3689] / [i915#5354] / [i915#6095]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:
- shard-tglu: NOTRUN -> [SKIP][101] ([i915#5354] / [i915#6095]) +3 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-pixel-format-yf_tiled_ccs:
- shard-tglu: NOTRUN -> [SKIP][102] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_ccs@pipe-c-bad-pixel-format-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_mtl_rc_ccs:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#5354]) +46 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_mtl_rc_ccs.html
* igt@kms_cdclk@plane-scaling@pipe-a-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#4087]) +3 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-2/igt@kms_cdclk@plane-scaling@pipe-a-hdmi-a-2.html
* igt@kms_chamelium_color@ctm-negative:
- shard-tglu: NOTRUN -> [SKIP][105] ([fdo#111827])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_color@ctm-red-to-blue:
- shard-dg2: NOTRUN -> [SKIP][106] ([fdo#111827]) +2 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_chamelium_color@ctm-red-to-blue.html
* igt@kms_chamelium_edid@dp-edid-change-during-suspend:
- shard-mtlp: NOTRUN -> [SKIP][107] ([i915#7828]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#7828]) +6 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@dp-hpd-storm-disable:
- shard-tglu: NOTRUN -> [SKIP][109] ([i915#7828]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html
* igt@kms_content_protection@atomic-dpms@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [TIMEOUT][110] ([i915#8628])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_content_protection@atomic-dpms@pipe-a-dp-2.html
* igt@kms_content_protection@content_type_change:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#7118]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_content_protection@content_type_change.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#3299])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@srm@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [TIMEOUT][113] ([i915#7173])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_content_protection@srm@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-tglu: NOTRUN -> [SKIP][114] ([i915#3359])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#3359]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-dg2: NOTRUN -> [SKIP][116] ([i915#3555]) +3 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_cursor_crc@cursor-random-max-size.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-tglu: NOTRUN -> [SKIP][117] ([fdo#109274])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-dg2: NOTRUN -> [SKIP][118] ([fdo#109274] / [fdo#111767] / [i915#5354])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-dg2: NOTRUN -> [SKIP][119] ([fdo#109274] / [i915#5354]) +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2: NOTRUN -> [SKIP][120] ([i915#4103] / [i915#4213])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dsc@dsc-with-formats:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#3555] / [i915#3840])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_dsc@dsc-with-formats.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-dg2: NOTRUN -> [SKIP][122] ([fdo#109274] / [fdo#111767])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][123] ([i915#8381])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-dg2: NOTRUN -> [SKIP][124] ([fdo#109274]) +7 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-tglu: NOTRUN -> [SKIP][125] ([fdo#109274] / [i915#3637]) +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-vga1:
- shard-snb: NOTRUN -> [DMESG-WARN][126] ([i915#8841]) +3 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-snb7/igt@kms_flip@flip-vs-suspend-interruptible@a-vga1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][127] ([i915#2587] / [i915#2672])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#2672]) +3 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][129] ([i915#2672] / [i915#3555])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-dg2: NOTRUN -> [SKIP][130] ([fdo#109285])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [FAIL][131] ([i915#6880]) +1 similar issue
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#8708]) +10 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][133] ([i915#5460])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-pwrite:
- shard-tglu: NOTRUN -> [SKIP][134] ([fdo#109280]) +4 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][135] ([i915#8708])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- shard-dg2: NOTRUN -> [SKIP][136] ([i915#3458]) +16 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_getfb@getfb-reject-ccs:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#6118])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_getfb@getfb-reject-ccs.html
* igt@kms_hdr@bpc-switch:
- shard-rkl: NOTRUN -> [SKIP][138] ([i915#3555] / [i915#8228]) +2 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-1/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#3555] / [i915#8228])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-6/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-dg2: NOTRUN -> [SKIP][140] ([fdo#109289]) +5 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1:
- shard-apl: [PASS][141] -> [ABORT][142] ([i915#180])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-apl4/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-1:
- shard-apl: [PASS][143] -> [DMESG-WARN][144] ([i915#180]) +1 similar issue
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-apl4/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-1.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-1.html
* igt@kms_plane@pixel-format-source-clamping@pipe-b-planes:
- shard-mtlp: [PASS][145] -> [FAIL][146] ([i915#1623]) +1 similar issue
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-6/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-4/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
* igt@kms_plane_lowres@tiling-y:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#8821])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_plane_lowres@tiling-y.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][148] ([i915#5176]) +7 similar issues
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][149] ([i915#5176]) +1 similar issue
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-4/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-d-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][150] ([i915#5176]) +23 similar issues
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-19/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-d-hdmi-a-1.html
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][151] ([i915#5176]) +3 similar issues
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][152] ([i915#5235]) +7 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-19/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#5235]) +23 similar issues
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][154] ([i915#5235]) +1 similar issue
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][155] ([i915#658]) +4 similar issues
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_basic:
- shard-tglu: NOTRUN -> [SKIP][156] ([fdo#110189]) +6 similar issues
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_psr@psr2_basic.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#1072]) +3 similar issues
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg2: NOTRUN -> [SKIP][158] ([i915#5461] / [i915#658])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_selftest@drm_damage:
- shard-mtlp: NOTRUN -> [SKIP][159] ([i915#8661])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@kms_selftest@drm_damage.html
* igt@kms_selftest@drm_plane:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#8661])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@kms_selftest@drm_plane.html
* igt@kms_writeback@writeback-fb-id:
- shard-dg2: NOTRUN -> [SKIP][161] ([i915#2437])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-tglu: NOTRUN -> [SKIP][162] ([i915#2437])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [PASS][163] -> [FAIL][164] ([i915#4349]) +3 similar issues
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-1/igt@perf_pmu@busy-double-start@vecs1.html
* igt@perf_pmu@cpu-hotplug:
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#8850])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@frequency@gt0:
- shard-dg2: NOTRUN -> [FAIL][166] ([i915#6806])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@perf_pmu@frequency@gt0.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#8516])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@fence-read-hang:
- shard-tglu: NOTRUN -> [SKIP][168] ([fdo#109295])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@prime_vgem@fence-read-hang.html
* igt@syncobj_timeline@single-wait-all-for-submit-available-signaled:
- shard-mtlp: [PASS][169] -> [DMESG-WARN][170] ([i915#2017])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-3/igt@syncobj_timeline@single-wait-all-for-submit-available-signaled.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@syncobj_timeline@single-wait-all-for-submit-available-signaled.html
* igt@v3d/v3d_submit_cl@simple-flush-cache:
- shard-dg2: NOTRUN -> [SKIP][171] ([i915#2575]) +12 similar issues
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@v3d/v3d_submit_cl@simple-flush-cache.html
* igt@v3d/v3d_submit_cl@single-out-sync:
- shard-tglu: NOTRUN -> [SKIP][172] ([fdo#109315] / [i915#2575]) +1 similar issue
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@v3d/v3d_submit_cl@single-out-sync.html
* igt@vc4/vc4_perfmon@get-values-invalid-pointer:
- shard-tglu: NOTRUN -> [SKIP][173] ([i915#2575])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@vc4/vc4_perfmon@get-values-invalid-pointer.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained:
- shard-dg2: NOTRUN -> [SKIP][174] ([i915#7711]) +5 similar issues
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-10/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#7711])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice.html
#### Possible fixes ####
* igt@gem_create@create-clear@smem0:
- shard-tglu: [INCOMPLETE][176] -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-tglu-6/igt@gem_create@create-clear@smem0.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-6/igt@gem_create@create-clear@smem0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [FAIL][178] ([i915#6268]) -> [PASS][179]
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-tglu-4/igt@gem_ctx_exec@basic-nohangcheck.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-8/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_freq@sysfs@gt0:
- shard-dg2: [FAIL][180] ([i915#6786]) -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg2-12/igt@gem_ctx_freq@sysfs@gt0.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-11/igt@gem_ctx_freq@sysfs@gt0.html
* igt@gem_eio@hibernate:
- shard-tglu: [ABORT][182] ([i915#7975] / [i915#8213] / [i915#8398]) -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-tglu-10/igt@gem_eio@hibernate.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-4/igt@gem_eio@hibernate.html
* igt@gem_exec_capture@pi@vcs0:
- shard-mtlp: [FAIL][184] ([i915#4475]) -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-3/igt@gem_exec_capture@pi@vcs0.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][186] ([i915#2842]) -> [PASS][187]
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: [FAIL][188] ([i915#2842]) -> [PASS][189]
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-rkl-2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-glk: [FAIL][190] ([i915#2842]) -> [PASS][191]
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-glk9/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-wb:
- shard-mtlp: [DMESG-FAIL][192] -> [PASS][193]
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-4/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-1/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
* igt@gem_spin_batch@spin-each:
- shard-apl: [FAIL][194] -> [PASS][195]
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-apl2/igt@gem_spin_batch@spin-each.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-apl7/igt@gem_spin_batch@spin-each.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-dg1: [FAIL][196] ([i915#3591]) -> [PASS][197]
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- shard-dg1: [FAIL][198] ([i915#7691]) -> [PASS][199]
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg1-13/igt@i915_pm_rpm@basic-pci-d3-state.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-19/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-rkl: [SKIP][200] ([i915#1397]) -> [PASS][201]
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-rkl-1/igt@i915_pm_rpm@dpms-lpsp.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-7/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-dg1: [SKIP][202] ([i915#1397]) -> [PASS][203] +2 similar issues
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg1-19/igt@i915_pm_rpm@dpms-non-lpsp.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-18/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0:
- shard-tglu: [FAIL][204] ([i915#7940]) -> [PASS][205] +2 similar issues
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-tglu-8/igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-tglu-7/igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: [SKIP][206] ([i915#1397]) -> [PASS][207] +1 similar issue
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-6/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@sysfs-read:
- shard-dg1: [FAIL][208] ([i915#7940]) -> [PASS][209] +1 similar issue
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg1-16/igt@i915_pm_rpm@sysfs-read.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-15/igt@i915_pm_rpm@sysfs-read.html
* igt@i915_selftest@live@requests:
- shard-mtlp: [DMESG-FAIL][210] ([i915#8497]) -> [PASS][211]
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-5/igt@i915_selftest@live@requests.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-6/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [FAIL][212] ([fdo#103375]) -> [PASS][213]
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-2/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-mtlp: [FAIL][214] ([i915#3743]) -> [PASS][215]
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-mtlp: [DMESG-WARN][216] ([i915#1982]) -> [PASS][217] +1 similar issue
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp1:
- shard-apl: [FAIL][218] ([i915#79]) -> [PASS][219]
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-apl2/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-apl6/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render:
- shard-dg2: [FAIL][220] ([i915#6880]) -> [PASS][221]
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-mtlp: [FAIL][222] ([fdo#103375]) -> [PASS][223]
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-suspend.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][224] ([i915#7484]) -> [PASS][225]
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-12/igt@perf@non-zero-reason@0-rcs0.html
#### Warnings ####
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-dg1: [FAIL][226] ([i915#7940]) -> [SKIP][227] ([i915#1397])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg1-18/igt@i915_pm_rpm@modeset-lpsp-stress.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-16/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][228] ([i915#3955]) -> [SKIP][229] ([fdo#110189] / [i915#3955])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-rkl-4/igt@kms_fbcon_fbt@psr-suspend.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_psr@sprite_plane_onoff:
- shard-dg1: [SKIP][230] ([i915#1072]) -> [SKIP][231] ([i915#1072] / [i915#4078]) +1 similar issue
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg1-15/igt@kms_psr@sprite_plane_onoff.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg1-13/igt@kms_psr@sprite_plane_onoff.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [CRASH][232] ([i915#7331]) -> [INCOMPLETE][233] ([i915#5493])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13500/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/shard-dg2-11/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1623]: https://gitlab.freedesktop.org/drm/intel/issues/1623
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6118]: https://gitlab.freedesktop.org/drm/intel/issues/6118
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755
[i915#6786]: https://gitlab.freedesktop.org/drm/intel/issues/6786
[i915#6806]: https://gitlab.freedesktop.org/drm/intel/issues/6806
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7691]: https://gitlab.freedesktop.org/drm/intel/issues/7691
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7765]: https://gitlab.freedesktop.org/drm/intel/issues/7765
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
[i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8489]: https://gitlab.freedesktop.org/drm/intel/issues/8489
[i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8628]: https://gitlab.freedesktop.org/drm/intel/issues/8628
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8798]: https://gitlab.freedesktop.org/drm/intel/issues/8798
[i915#8821]: https://gitlab.freedesktop.org/drm/intel/issues/8821
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
[i915#8898]: https://gitlab.freedesktop.org/drm/intel/issues/8898
[i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
[i915#9053]: https://gitlab.freedesktop.org/drm/intel/issues/9053
Build changes
-------------
* Linux: CI_DRM_13500 -> Patchwork_117662v7
CI-20190529: 20190529
CI_DRM_13500: 4be6c76008410cf6ada52b25cb4bc4280bc3a3ee @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7426: 67e7470eb79ca386087775d0b1b51c164abbf9c8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_117662v7: 4be6c76008410cf6ada52b25cb4bc4280bc3a3ee @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117662v7/index.html
[-- Attachment #2: Type: text/html, Size: 74799 bytes --]
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [Intel-gfx] [PATCH 00/20] DSC misc fixes
2023-08-10 13:02 ` Ankit Nautiyal
@ 2023-08-17 9:49 ` Jani Nikula
-1 siblings, 0 replies; 53+ messages in thread
From: Jani Nikula @ 2023-08-17 9:49 UTC (permalink / raw)
To: Ankit Nautiyal, intel-gfx, dri-devel
On Thu, 10 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> This series is an attempt to address multiple issues with DSC,
> scattered in separate existing series.
I think it's a good idea to have one person manage the series, and
combine it all together, because it touches the same areas.
However, once you have smaller batches of patches that are all reviewed,
send them out as smaller series, and get them merged. Re-sending and
rebasing ready patches as part of a 19-patch series where some patches
aren't ready has become counter-productive.
Getting patches upstream is like working on a machine that has a certain
peak throughput. Send patches one by one, and it's inefficient. Send too
many at once, and it bogs down. Personally, I think 5-10 non-trivial
patches at a time is about right, get them reviewed and merged, rebase
the rest locally, and again send the next 5-10.
Or you can initially send a longer series, but once the first 5-10 have
been reviewed, send them separately.
BR,
Jani.
>
> Patches 1-4 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
> https://patchwork.freedesktop.org/series/107550/
>
> Patches 5-6 are from series DSC fixes for Bigjoiner:
> https://patchwork.freedesktop.org/series/115773/
>
> Patches 7-17 are based on series to add DSC fractional BPP support:
> https://patchwork.freedesktop.org/series/111391/
>
> Patch 20 is to fix compressed bpc for MST DSC, from Stan's series :
> https://patchwork.freedesktop.org/series/116179/
>
> Rev2: Addressed review comments from Stan, Ville.
>
> Rev3: Split larger patches. Separate out common helpers.
>
> Rev4: Rebased, fixed checkpatch warnings.
>
> Rev5: Addressed review comments from Stan.
> Added a patch to check if forced dsc format can be used before forcing.
>
> Rev6: Addressed review comments from Stan.
>
> Rev7: Reordered and rebased.
>
> Ankit Nautiyal (19):
> drm/i915/dp: Consider output_format while computing dsc bpp
> drm/i915/dp: Move compressed bpp check with 420 format inside the
> helper
> drm/i915/dp_mst: Use output_format to get the final link bpp
> drm/i915/dp: Use consistent name for link bpp and compressed bpp
> drm/i915/dp: Update Bigjoiner interface bits for computing compressed
> bpp
> drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
> drm/i915/dp: Remove extra logs for printing DSC info
> drm/display/dp: Fix the DP DSC Receiver cap size
> drm/i915/dp: Avoid forcing DSC BPC for MST case
> drm/i915/dp: Add functions to get min/max src input bpc with DSC
> drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
> drm/i915/dp: Avoid left shift of DSC output bpp by 4
> drm/i915/dp: Rename helper to get DSC max pipe_bpp
> drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
> drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with
> DSC
> drm/i915/dp: Separate out function to get compressed bpp with joiner
> drm/i915/dp: Get optimal link config to have best compressed bpp
> drm/i915/dp: Check src/sink compressed bpp limit for edp
> drm/i915/dp: Check if force_dsc_output_format is possible
>
> Stanislav Lisovskiy (1):
> drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
> info
>
> drivers/gpu/drm/i915/display/intel_cdclk.c | 59 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 655 ++++++++++++++++----
> drivers/gpu/drm/i915/display/intel_dp.h | 20 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 80 +--
> include/drm/display/drm_dp.h | 2 +-
> 5 files changed, 625 insertions(+), 191 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 00/20] DSC misc fixes
@ 2023-08-17 9:49 ` Jani Nikula
0 siblings, 0 replies; 53+ messages in thread
From: Jani Nikula @ 2023-08-17 9:49 UTC (permalink / raw)
To: Ankit Nautiyal, intel-gfx, dri-devel
Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
On Thu, 10 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> This series is an attempt to address multiple issues with DSC,
> scattered in separate existing series.
I think it's a good idea to have one person manage the series, and
combine it all together, because it touches the same areas.
However, once you have smaller batches of patches that are all reviewed,
send them out as smaller series, and get them merged. Re-sending and
rebasing ready patches as part of a 19-patch series where some patches
aren't ready has become counter-productive.
Getting patches upstream is like working on a machine that has a certain
peak throughput. Send patches one by one, and it's inefficient. Send too
many at once, and it bogs down. Personally, I think 5-10 non-trivial
patches at a time is about right, get them reviewed and merged, rebase
the rest locally, and again send the next 5-10.
Or you can initially send a longer series, but once the first 5-10 have
been reviewed, send them separately.
BR,
Jani.
>
> Patches 1-4 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
> https://patchwork.freedesktop.org/series/107550/
>
> Patches 5-6 are from series DSC fixes for Bigjoiner:
> https://patchwork.freedesktop.org/series/115773/
>
> Patches 7-17 are based on series to add DSC fractional BPP support:
> https://patchwork.freedesktop.org/series/111391/
>
> Patch 20 is to fix compressed bpc for MST DSC, from Stan's series :
> https://patchwork.freedesktop.org/series/116179/
>
> Rev2: Addressed review comments from Stan, Ville.
>
> Rev3: Split larger patches. Separate out common helpers.
>
> Rev4: Rebased, fixed checkpatch warnings.
>
> Rev5: Addressed review comments from Stan.
> Added a patch to check if forced dsc format can be used before forcing.
>
> Rev6: Addressed review comments from Stan.
>
> Rev7: Reordered and rebased.
>
> Ankit Nautiyal (19):
> drm/i915/dp: Consider output_format while computing dsc bpp
> drm/i915/dp: Move compressed bpp check with 420 format inside the
> helper
> drm/i915/dp_mst: Use output_format to get the final link bpp
> drm/i915/dp: Use consistent name for link bpp and compressed bpp
> drm/i915/dp: Update Bigjoiner interface bits for computing compressed
> bpp
> drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
> drm/i915/dp: Remove extra logs for printing DSC info
> drm/display/dp: Fix the DP DSC Receiver cap size
> drm/i915/dp: Avoid forcing DSC BPC for MST case
> drm/i915/dp: Add functions to get min/max src input bpc with DSC
> drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
> drm/i915/dp: Avoid left shift of DSC output bpp by 4
> drm/i915/dp: Rename helper to get DSC max pipe_bpp
> drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
> drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with
> DSC
> drm/i915/dp: Separate out function to get compressed bpp with joiner
> drm/i915/dp: Get optimal link config to have best compressed bpp
> drm/i915/dp: Check src/sink compressed bpp limit for edp
> drm/i915/dp: Check if force_dsc_output_format is possible
>
> Stanislav Lisovskiy (1):
> drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
> info
>
> drivers/gpu/drm/i915/display/intel_cdclk.c | 59 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 655 ++++++++++++++++----
> drivers/gpu/drm/i915/display/intel_dp.h | 20 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 80 +--
> include/drm/display/drm_dp.h | 2 +-
> 5 files changed, 625 insertions(+), 191 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 00/20] DSC misc fixes
2023-08-17 9:49 ` Jani Nikula
@ 2023-08-17 13:52 ` Nautiyal, Ankit K
-1 siblings, 0 replies; 53+ messages in thread
From: Nautiyal, Ankit K @ 2023-08-17 13:52 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, dri-devel
On 8/17/2023 3:19 PM, Jani Nikula wrote:
> On Thu, 10 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> This series is an attempt to address multiple issues with DSC,
>> scattered in separate existing series.
> I think it's a good idea to have one person manage the series, and
> combine it all together, because it touches the same areas.
>
> However, once you have smaller batches of patches that are all reviewed,
> send them out as smaller series, and get them merged. Re-sending and
> rebasing ready patches as part of a 19-patch series where some patches
> aren't ready has become counter-productive.
>
> Getting patches upstream is like working on a machine that has a certain
> peak throughput. Send patches one by one, and it's inefficient. Send too
> many at once, and it bogs down. Personally, I think 5-10 non-trivial
> patches at a time is about right, get them reviewed and merged, rebase
> the rest locally, and again send the next 5-10.
>
> Or you can initially send a longer series, but once the first 5-10 have
> been reviewed, send them separately.
Yeah this indeed become bloated with assortment of fixes. Should have
separated series as they got reviewed. Will take care going forward.
For this series, I will merge the reviewed i915 patches and send a
separate series for the drm patch#8 (drm/display/dp: Fix the DP DSC
Receiver cap size).
Regards,
Ankit
>
>
> BR,
> Jani.
>
>
>> Patches 1-4 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
>> https://patchwork.freedesktop.org/series/107550/
>>
>> Patches 5-6 are from series DSC fixes for Bigjoiner:
>> https://patchwork.freedesktop.org/series/115773/
>>
>> Patches 7-17 are based on series to add DSC fractional BPP support:
>> https://patchwork.freedesktop.org/series/111391/
>>
>> Patch 20 is to fix compressed bpc for MST DSC, from Stan's series :
>> https://patchwork.freedesktop.org/series/116179/
>>
>> Rev2: Addressed review comments from Stan, Ville.
>>
>> Rev3: Split larger patches. Separate out common helpers.
>>
>> Rev4: Rebased, fixed checkpatch warnings.
>>
>> Rev5: Addressed review comments from Stan.
>> Added a patch to check if forced dsc format can be used before forcing.
>>
>> Rev6: Addressed review comments from Stan.
>>
>> Rev7: Reordered and rebased.
>>
>> Ankit Nautiyal (19):
>> drm/i915/dp: Consider output_format while computing dsc bpp
>> drm/i915/dp: Move compressed bpp check with 420 format inside the
>> helper
>> drm/i915/dp_mst: Use output_format to get the final link bpp
>> drm/i915/dp: Use consistent name for link bpp and compressed bpp
>> drm/i915/dp: Update Bigjoiner interface bits for computing compressed
>> bpp
>> drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
>> drm/i915/dp: Remove extra logs for printing DSC info
>> drm/display/dp: Fix the DP DSC Receiver cap size
>> drm/i915/dp: Avoid forcing DSC BPC for MST case
>> drm/i915/dp: Add functions to get min/max src input bpc with DSC
>> drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
>> drm/i915/dp: Avoid left shift of DSC output bpp by 4
>> drm/i915/dp: Rename helper to get DSC max pipe_bpp
>> drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
>> drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with
>> DSC
>> drm/i915/dp: Separate out function to get compressed bpp with joiner
>> drm/i915/dp: Get optimal link config to have best compressed bpp
>> drm/i915/dp: Check src/sink compressed bpp limit for edp
>> drm/i915/dp: Check if force_dsc_output_format is possible
>>
>> Stanislav Lisovskiy (1):
>> drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
>> info
>>
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 59 +-
>> drivers/gpu/drm/i915/display/intel_dp.c | 655 ++++++++++++++++----
>> drivers/gpu/drm/i915/display/intel_dp.h | 20 +-
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 80 +--
>> include/drm/display/drm_dp.h | 2 +-
>> 5 files changed, 625 insertions(+), 191 deletions(-)
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH 00/20] DSC misc fixes
@ 2023-08-17 13:52 ` Nautiyal, Ankit K
0 siblings, 0 replies; 53+ messages in thread
From: Nautiyal, Ankit K @ 2023-08-17 13:52 UTC (permalink / raw)
To: Jani Nikula, intel-gfx, dri-devel
Cc: stanislav.lisovskiy, anusha.srivatsa, navaremanasi
On 8/17/2023 3:19 PM, Jani Nikula wrote:
> On Thu, 10 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> This series is an attempt to address multiple issues with DSC,
>> scattered in separate existing series.
> I think it's a good idea to have one person manage the series, and
> combine it all together, because it touches the same areas.
>
> However, once you have smaller batches of patches that are all reviewed,
> send them out as smaller series, and get them merged. Re-sending and
> rebasing ready patches as part of a 19-patch series where some patches
> aren't ready has become counter-productive.
>
> Getting patches upstream is like working on a machine that has a certain
> peak throughput. Send patches one by one, and it's inefficient. Send too
> many at once, and it bogs down. Personally, I think 5-10 non-trivial
> patches at a time is about right, get them reviewed and merged, rebase
> the rest locally, and again send the next 5-10.
>
> Or you can initially send a longer series, but once the first 5-10 have
> been reviewed, send them separately.
Yeah this indeed become bloated with assortment of fixes. Should have
separated series as they got reviewed. Will take care going forward.
For this series, I will merge the reviewed i915 patches and send a
separate series for the drm patch#8 (drm/display/dp: Fix the DP DSC
Receiver cap size).
Regards,
Ankit
>
>
> BR,
> Jani.
>
>
>> Patches 1-4 are DSC fixes from series to Handle BPC for HDMI2.1 PCON
>> https://patchwork.freedesktop.org/series/107550/
>>
>> Patches 5-6 are from series DSC fixes for Bigjoiner:
>> https://patchwork.freedesktop.org/series/115773/
>>
>> Patches 7-17 are based on series to add DSC fractional BPP support:
>> https://patchwork.freedesktop.org/series/111391/
>>
>> Patch 20 is to fix compressed bpc for MST DSC, from Stan's series :
>> https://patchwork.freedesktop.org/series/116179/
>>
>> Rev2: Addressed review comments from Stan, Ville.
>>
>> Rev3: Split larger patches. Separate out common helpers.
>>
>> Rev4: Rebased, fixed checkpatch warnings.
>>
>> Rev5: Addressed review comments from Stan.
>> Added a patch to check if forced dsc format can be used before forcing.
>>
>> Rev6: Addressed review comments from Stan.
>>
>> Rev7: Reordered and rebased.
>>
>> Ankit Nautiyal (19):
>> drm/i915/dp: Consider output_format while computing dsc bpp
>> drm/i915/dp: Move compressed bpp check with 420 format inside the
>> helper
>> drm/i915/dp_mst: Use output_format to get the final link bpp
>> drm/i915/dp: Use consistent name for link bpp and compressed bpp
>> drm/i915/dp: Update Bigjoiner interface bits for computing compressed
>> bpp
>> drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck
>> drm/i915/dp: Remove extra logs for printing DSC info
>> drm/display/dp: Fix the DP DSC Receiver cap size
>> drm/i915/dp: Avoid forcing DSC BPC for MST case
>> drm/i915/dp: Add functions to get min/max src input bpc with DSC
>> drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also
>> drm/i915/dp: Avoid left shift of DSC output bpp by 4
>> drm/i915/dp: Rename helper to get DSC max pipe_bpp
>> drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
>> drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with
>> DSC
>> drm/i915/dp: Separate out function to get compressed bpp with joiner
>> drm/i915/dp: Get optimal link config to have best compressed bpp
>> drm/i915/dp: Check src/sink compressed bpp limit for edp
>> drm/i915/dp: Check if force_dsc_output_format is possible
>>
>> Stanislav Lisovskiy (1):
>> drm/i915: Query compressed bpp properly using correct DPCD and DP Spec
>> info
>>
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 59 +-
>> drivers/gpu/drm/i915/display/intel_dp.c | 655 ++++++++++++++++----
>> drivers/gpu/drm/i915/display/intel_dp.h | 20 +-
>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 80 +--
>> include/drm/display/drm_dp.h | 2 +-
>> 5 files changed, 625 insertions(+), 191 deletions(-)
^ permalink raw reply [flat|nested] 53+ messages in thread