* [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access
@ 2020-01-23 13:59 Jani Nikula
2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 2/6] drm/i915/display: use intel de " Jani Nikula
` (8 more replies)
0 siblings, 9 replies; 16+ messages in thread
From: Jani Nikula @ 2020-01-23 13:59 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using
intel_uncore_read_fw() and intel_uncore_write_fw(), respectively.
No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_csr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index ae25960f74e0..6a408e11a3de 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -315,7 +315,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
preempt_disable();
for (i = 0; i < fw_size; i++)
- I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+ intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i),
+ payload[i]);
preempt_enable();
--
2.20.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [Intel-gfx] [PATCH RESEND 2/6] drm/i915/display: use intel de functions for forcewake register access 2020-01-23 13:59 [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access Jani Nikula @ 2020-01-23 14:00 ` Jani Nikula 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 3/6] drm/i915/irq: " Jani Nikula ` (7 subsequent siblings) 8 siblings, 0 replies; 16+ messages in thread From: Jani Nikula @ 2020-01-23 14:00 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 79 +++++++++++--------- 1 file changed, 42 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 878d331b9e8c..0fb0773c70b6 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4331,7 +4331,8 @@ static void i9xx_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), + plane_state->color_plane[0].stride); if (INTEL_GEN(dev_priv) < 4) { /* @@ -4339,21 +4340,26 @@ static void i9xx_update_plane(struct intel_plane *plane, * generator but let's assume we still need to * program whatever is there. */ - I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(DSPSIZE(i9xx_plane), - ((crtc_h - 1) << 16) | (crtc_w - 1)); + intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), + ((crtc_h - 1) << 16) | (crtc_w - 1)); } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { - I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(PRIMSIZE(i9xx_plane), - ((crtc_h - 1) << 16) | (crtc_w - 1)); - I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0); + intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), + ((crtc_h - 1) << 16) | (crtc_w - 1)); + intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); } if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x); + intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), + (y << 16) | x); } else if (INTEL_GEN(dev_priv) >= 4) { - I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset); - I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x); + intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), + linear_offset); + intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), + (y << 16) | x); } /* @@ -4361,15 +4367,13 @@ static void i9xx_update_plane(struct intel_plane *plane, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); if (INTEL_GEN(dev_priv) >= 4) - I915_WRITE_FW(DSPSURF(i9xx_plane), - intel_plane_ggtt_offset(plane_state) + - dspaddr_offset); + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); else - I915_WRITE_FW(DSPADDR(i9xx_plane), - intel_plane_ggtt_offset(plane_state) + - dspaddr_offset); + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -4396,11 +4400,11 @@ static void i9xx_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); if (INTEL_GEN(dev_priv) >= 4) - I915_WRITE_FW(DSPSURF(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); else - I915_WRITE_FW(DSPADDR(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -6175,10 +6179,10 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) id = scaler_state->scaler_id; I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); - I915_WRITE_FW(SKL_PS_VPHASE(pipe, id), - PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); - I915_WRITE_FW(SKL_PS_HPHASE(pipe, id), - PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); + intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); + intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos); I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size); } @@ -11315,17 +11319,17 @@ static void i845_update_cursor(struct intel_plane *plane, if (plane->cursor.base != base || plane->cursor.size != size || plane->cursor.cntl != cntl) { - I915_WRITE_FW(CURCNTR(PIPE_A), 0); - I915_WRITE_FW(CURBASE(PIPE_A), base); - I915_WRITE_FW(CURSIZE, size); - I915_WRITE_FW(CURPOS(PIPE_A), pos); - I915_WRITE_FW(CURCNTR(PIPE_A), cntl); + intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); + intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); + intel_de_write_fw(dev_priv, CURSIZE, size); + intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); + intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); plane->cursor.base = base; plane->cursor.size = size; plane->cursor.cntl = cntl; } else { - I915_WRITE_FW(CURPOS(PIPE_A), pos); + intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); @@ -11566,17 +11570,18 @@ static void i9xx_update_cursor(struct intel_plane *plane, plane->cursor.size != fbc_ctl || plane->cursor.cntl != cntl) { if (HAS_CUR_FBC(dev_priv)) - I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); - I915_WRITE_FW(CURCNTR(pipe), cntl); - I915_WRITE_FW(CURPOS(pipe), pos); - I915_WRITE_FW(CURBASE(pipe), base); + intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), + fbc_ctl); + intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); + intel_de_write_fw(dev_priv, CURPOS(pipe), pos); + intel_de_write_fw(dev_priv, CURBASE(pipe), base); plane->cursor.base = base; plane->cursor.size = fbc_ctl; plane->cursor.cntl = cntl; } else { - I915_WRITE_FW(CURPOS(pipe), pos); - I915_WRITE_FW(CURBASE(pipe), base); + intel_de_write_fw(dev_priv, CURPOS(pipe), pos); + intel_de_write_fw(dev_priv, CURBASE(pipe), base); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH RESEND 3/6] drm/i915/irq: use intel de functions for forcewake register access 2020-01-23 13:59 [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access Jani Nikula 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 2/6] drm/i915/display: use intel de " Jani Nikula @ 2020-01-23 14:00 ` Jani Nikula 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 4/6] drm/i915/gmbus: " Jani Nikula ` (6 subsequent siblings) 8 siblings, 0 replies; 16+ messages in thread From: Jani Nikula @ 2020-01-23 14:00 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 94cb25ac504d..87a6662abc1b 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -629,9 +629,9 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc) * register. */ do { - high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; - low = I915_READ_FW(low_frame); - high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK; + high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; + low = intel_de_read_fw(dev_priv, low_frame); + high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; } while (high1 != high2); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); @@ -688,15 +688,17 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) * pipe frame time stamp. The time stamp value * is sampled at every start of vertical blank. */ - scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); + scan_prev_time = intel_de_read_fw(dev_priv, + PIPE_FRMTMSTMP(crtc->pipe)); /* * The TIMESTAMP_CTR register has the current * time stamp value. */ - scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR); + scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); - scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe)); + scan_post_time = intel_de_read_fw(dev_priv, + PIPE_FRMTMSTMP(crtc->pipe)); } while (scan_post_time != scan_prev_time); scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, @@ -707,7 +709,10 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) return scanline; } -/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */ +/* + * intel_de_read_fw(), only for fast reads of display block, no need for + * forcewake etc. + */ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; @@ -731,9 +736,9 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) vtotal /= 2; if (IS_GEN(dev_priv, 2)) - position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; + position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; else - position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; + position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; /* * On HSW, the DSL reg (0x70000) appears to return 0 if we @@ -752,7 +757,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) for (i = 0; i < 100; i++) { udelay(1); - temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; + temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; if (temp != position) { position = temp; break; @@ -823,7 +828,7 @@ bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int index, * We can split this into vertical and horizontal * scanout position. */ - position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; + position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; /* convert to pixel counts */ vbl_start *= htotal; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH RESEND 4/6] drm/i915/gmbus: use intel de functions for forcewake register access 2020-01-23 13:59 [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access Jani Nikula 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 2/6] drm/i915/display: use intel de " Jani Nikula 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 3/6] drm/i915/irq: " Jani Nikula @ 2020-01-23 14:00 ` Jani Nikula 2020-01-23 14:13 ` Ville Syrjälä 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 5/6] drm/i915/sprite: " Jani Nikula ` (5 subsequent siblings) 8 siblings, 1 reply; 16+ messages in thread From: Jani Nikula @ 2020-01-23 14:00 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. Also switch I915_READ() and I915_WRITE() over in this file while at it. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_gmbus.c | 74 ++++++++++------------ 1 file changed, 35 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index 3d4d19ac1d14..508308555dc6 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -143,8 +143,8 @@ to_intel_gmbus(struct i2c_adapter *i2c) void intel_gmbus_reset(struct drm_i915_private *dev_priv) { - I915_WRITE(GMBUS0, 0); - I915_WRITE(GMBUS4, 0); + intel_de_write(dev_priv, GMBUS0, 0); + intel_de_write(dev_priv, GMBUS4, 0); } static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -153,12 +153,12 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, u32 val; /* When using bit bashing for I2C, this bit needs to be set to 1 */ - val = I915_READ(DSPCLK_GATE_D); + val = intel_de_read(dev_priv, DSPCLK_GATE_D); if (!enable) val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; else val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(DSPCLK_GATE_D, val); + intel_de_write(dev_priv, DSPCLK_GATE_D, val); } static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -166,12 +166,12 @@ static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(SOUTH_DSPCLK_GATE_D); + val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); if (!enable) val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; else val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(SOUTH_DSPCLK_GATE_D, val); + intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); } static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -179,12 +179,12 @@ static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(GEN9_CLKGATE_DIS_4); + val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4); if (!enable) val |= BXT_GMBUS_GATING_DIS; else val &= ~BXT_GMBUS_GATING_DIS; - I915_WRITE(GEN9_CLKGATE_DIS_4, val); + intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val); } static u32 get_reserved(struct intel_gmbus *bus) @@ -337,14 +337,16 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) irq_en = 0; add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); - I915_WRITE_FW(GMBUS4, irq_en); + intel_de_write_fw(dev_priv, GMBUS4, irq_en); status |= GMBUS_SATOER; - ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); + ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, + 2); if (ret) - ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); + ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, + 50); - I915_WRITE_FW(GMBUS4, 0); + intel_de_write_fw(dev_priv, GMBUS4, 0); remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); if (gmbus2 & GMBUS_SATOER) @@ -366,13 +368,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) irq_enable = GMBUS_IDLE_EN; add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); - I915_WRITE_FW(GMBUS4, irq_enable); + intel_de_write_fw(dev_priv, GMBUS4, irq_enable); ret = intel_wait_for_register_fw(&dev_priv->uncore, GMBUS2, GMBUS_ACTIVE, 0, 10); - I915_WRITE_FW(GMBUS4, 0); + intel_de_write_fw(dev_priv, GMBUS4, 0); remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); return ret; @@ -404,15 +406,12 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, len++; } size = len % 256 + 256; - I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); + intel_de_write_fw(dev_priv, GMBUS0, + gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); } - I915_WRITE_FW(GMBUS1, - gmbus1_index | - GMBUS_CYCLE_WAIT | - (size << GMBUS_BYTE_COUNT_SHIFT) | - (addr << GMBUS_SLAVE_ADDR_SHIFT) | - GMBUS_SLAVE_READ | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS1, + gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); while (len) { int ret; u32 val, loop = 0; @@ -421,7 +420,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, if (ret) return ret; - val = I915_READ_FW(GMBUS3); + val = intel_de_read_fw(dev_priv, GMBUS3); do { if (extra_byte_added && len == 1) break; @@ -432,7 +431,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, if (burst_read && len == size - 4) /* Reset the override bit */ - I915_WRITE_FW(GMBUS0, gmbus0_reg); + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg); } return 0; @@ -489,12 +488,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, len -= 1; } - I915_WRITE_FW(GMBUS3, val); - I915_WRITE_FW(GMBUS1, - gmbus1_index | GMBUS_CYCLE_WAIT | - (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | - (addr << GMBUS_SLAVE_ADDR_SHIFT) | - GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS3, val); + intel_de_write_fw(dev_priv, GMBUS1, + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); while (len) { int ret; @@ -503,7 +499,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, val |= *buf++ << (8 * loop); } while (--len && ++loop < 4); - I915_WRITE_FW(GMBUS3, val); + intel_de_write_fw(dev_priv, GMBUS3, val); ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); if (ret) @@ -568,7 +564,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, /* GMBUS5 holds 16-bit index */ if (gmbus5) - I915_WRITE_FW(GMBUS5, gmbus5); + intel_de_write_fw(dev_priv, GMBUS5, gmbus5); if (msgs[1].flags & I2C_M_RD) ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, @@ -578,7 +574,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, /* Clear GMBUS5 after each index transfer */ if (gmbus5) - I915_WRITE_FW(GMBUS5, 0); + intel_de_write_fw(dev_priv, GMBUS5, 0); return ret; } @@ -601,7 +597,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, pch_gmbus_clock_gating(dev_priv, false); retry: - I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0); + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0); for (; i < num; i += inc) { inc = 1; @@ -629,7 +625,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, * a STOP on the very first cycle. To simplify the code we * unconditionally generate the STOP condition with an additional gmbus * cycle. */ - I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); /* Mark the GMBUS interface as disabled after waiting for idle. * We will re-enable it at the start of the next xfer, @@ -640,7 +636,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, adapter->name); ret = -ETIMEDOUT; } - I915_WRITE_FW(GMBUS0, 0); + intel_de_write_fw(dev_priv, GMBUS0, 0); ret = ret ?: i; goto out; @@ -669,9 +665,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, * of resetting the GMBUS controller and so clearing the * BUS_ERROR raised by the slave's NAK. */ - I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); - I915_WRITE_FW(GMBUS1, 0); - I915_WRITE_FW(GMBUS0, 0); + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT); + intel_de_write_fw(dev_priv, GMBUS1, 0); + intel_de_write_fw(dev_priv, GMBUS0, 0); DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", adapter->name, msgs[i].addr, @@ -694,7 +690,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, timeout: DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", bus->adapter.name, bus->reg0 & 0xff); - I915_WRITE_FW(GMBUS0, 0); + intel_de_write_fw(dev_priv, GMBUS0, 0); /* * Hardware may not support GMBUS over these pins? Try GPIO bitbanging -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH RESEND 4/6] drm/i915/gmbus: use intel de functions for forcewake register access 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 4/6] drm/i915/gmbus: " Jani Nikula @ 2020-01-23 14:13 ` Ville Syrjälä 0 siblings, 0 replies; 16+ messages in thread From: Ville Syrjälä @ 2020-01-23 14:13 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Thu, Jan 23, 2020 at 04:00:02PM +0200, Jani Nikula wrote: > Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and > switch to using intel_de_read_fw() and intel_de_write_fw(), > respectively. Also switch I915_READ() and I915_WRITE() over in this file > while at it. > > No functional changes. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_gmbus.c | 74 ++++++++++------------ > 1 file changed, 35 insertions(+), 39 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c > index 3d4d19ac1d14..508308555dc6 100644 > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c <snip> > @@ -404,15 +406,12 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, > len++; > } > size = len % 256 + 256; > - I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); > + intel_de_write_fw(dev_priv, GMBUS0, > + gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); > } > > - I915_WRITE_FW(GMBUS1, > - gmbus1_index | > - GMBUS_CYCLE_WAIT | > - (size << GMBUS_BYTE_COUNT_SHIFT) | > - (addr << GMBUS_SLAVE_ADDR_SHIFT) | > - GMBUS_SLAVE_READ | GMBUS_SW_RDY); > + intel_de_write_fw(dev_priv, GMBUS1, > + gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); This one turned a bit ugly. > while (len) { > int ret; > u32 val, loop = 0; > @@ -421,7 +420,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, > if (ret) > return ret; > > - val = I915_READ_FW(GMBUS3); > + val = intel_de_read_fw(dev_priv, GMBUS3); > do { > if (extra_byte_added && len == 1) > break; > @@ -432,7 +431,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, > > if (burst_read && len == size - 4) > /* Reset the override bit */ > - I915_WRITE_FW(GMBUS0, gmbus0_reg); > + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg); > } > > return 0; > @@ -489,12 +488,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, > len -= 1; > } > > - I915_WRITE_FW(GMBUS3, val); > - I915_WRITE_FW(GMBUS1, > - gmbus1_index | GMBUS_CYCLE_WAIT | > - (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | > - (addr << GMBUS_SLAVE_ADDR_SHIFT) | > - GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); > + intel_de_write_fw(dev_priv, GMBUS3, val); > + intel_de_write_fw(dev_priv, GMBUS1, > + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); ditto > while (len) { > int ret; > > @@ -503,7 +499,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, > val |= *buf++ << (8 * loop); > } while (--len && ++loop < 4); > > - I915_WRITE_FW(GMBUS3, val); > + intel_de_write_fw(dev_priv, GMBUS3, val); > > ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); > if (ret) > @@ -568,7 +564,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, > > /* GMBUS5 holds 16-bit index */ > if (gmbus5) > - I915_WRITE_FW(GMBUS5, gmbus5); > + intel_de_write_fw(dev_priv, GMBUS5, gmbus5); > > if (msgs[1].flags & I2C_M_RD) > ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, > @@ -578,7 +574,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, > > /* Clear GMBUS5 after each index transfer */ > if (gmbus5) > - I915_WRITE_FW(GMBUS5, 0); > + intel_de_write_fw(dev_priv, GMBUS5, 0); > > return ret; > } > @@ -601,7 +597,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, > pch_gmbus_clock_gating(dev_priv, false); > > retry: > - I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0); > + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0); > > for (; i < num; i += inc) { > inc = 1; > @@ -629,7 +625,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, > * a STOP on the very first cycle. To simplify the code we > * unconditionally generate the STOP condition with an additional gmbus > * cycle. */ > - I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); > + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); > > /* Mark the GMBUS interface as disabled after waiting for idle. > * We will re-enable it at the start of the next xfer, > @@ -640,7 +636,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, > adapter->name); > ret = -ETIMEDOUT; > } > - I915_WRITE_FW(GMBUS0, 0); > + intel_de_write_fw(dev_priv, GMBUS0, 0); > ret = ret ?: i; > goto out; > > @@ -669,9 +665,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, > * of resetting the GMBUS controller and so clearing the > * BUS_ERROR raised by the slave's NAK. > */ > - I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); > - I915_WRITE_FW(GMBUS1, 0); > - I915_WRITE_FW(GMBUS0, 0); > + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT); > + intel_de_write_fw(dev_priv, GMBUS1, 0); > + intel_de_write_fw(dev_priv, GMBUS0, 0); > > DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", > adapter->name, msgs[i].addr, > @@ -694,7 +690,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, > timeout: > DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", > bus->adapter.name, bus->reg0 & 0xff); > - I915_WRITE_FW(GMBUS0, 0); > + intel_de_write_fw(dev_priv, GMBUS0, 0); > > /* > * Hardware may not support GMBUS over these pins? Try GPIO bitbanging > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH RESEND 5/6] drm/i915/sprite: use intel de functions for forcewake register access 2020-01-23 13:59 [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access Jani Nikula ` (2 preceding siblings ...) 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 4/6] drm/i915/gmbus: " Jani Nikula @ 2020-01-23 14:00 ` Jani Nikula 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 6/6] drm/i915/pm: " Jani Nikula ` (4 subsequent siblings) 8 siblings, 0 replies; 16+ messages in thread From: Jani Nikula @ 2020-01-23 14:00 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. Also switch I915_READ() and I915_WRITE() over in this file while at it. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_sprite.c | 318 +++++++++++--------- 1 file changed, 173 insertions(+), 145 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index fca77ec1e0dd..3e597ebe4f67 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -434,14 +434,16 @@ skl_program_scaler(struct intel_plane *plane, uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); } - I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), - PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode); - I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id), - PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); - I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id), - PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); - I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); - I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h); + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), + PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode); + intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id), + PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); + intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id), + PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id), + (crtc_x << 16) | crtc_y); + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id), + (crtc_w << 16) | crtc_h); } /* Preoffset values for YUV to RGB Conversion */ @@ -547,28 +549,37 @@ icl_program_input_csc(struct intel_plane *plane, else csc = input_csc_matrix_lr[plane_state->hw.color_encoding]; - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) | - GOFF(csc[1])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) | - GOFF(csc[4])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) | - GOFF(csc[7])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8])); - - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), - PREOFF_YUV_TO_RGB_HI); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), + ROFF(csc[0]) | GOFF(csc[1])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), + BOFF(csc[2])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), + ROFF(csc[3]) | GOFF(csc[4])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), + BOFF(csc[5])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), + ROFF(csc[6]) | GOFF(csc[7])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), + BOFF(csc[8])); + + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), + PREOFF_YUV_TO_RGB_HI); if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), + 0); else - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), - PREOFF_YUV_TO_RGB_ME); - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), - PREOFF_YUV_TO_RGB_LO); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), + PREOFF_YUV_TO_RGB_ME); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), + PREOFF_YUV_TO_RGB_LO); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } static void @@ -623,44 +634,47 @@ skl_program_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); - I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); + intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride); + intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); if (INTEL_GEN(dev_priv) < 12) aux_dist |= aux_stride; - I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist); + intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist); if (icl_is_hdr_plane(dev_priv, plane_id)) - I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl); + intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), + plane_state->cus_ctl); if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) - I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), + plane_color_ctl); if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) icl_program_input_csc(plane, crtc_state, plane_state); skl_write_plane_wm(plane, crtc_state); - I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); - I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk); - I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax); + intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), + key->min_value); + intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk); + intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax); - I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); + intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), + (y << 16) | x); if (INTEL_GEN(dev_priv) < 11) - I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), - (plane_state->color_plane[1].y << 16) | - plane_state->color_plane[1].x); + intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), + (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); - I915_WRITE_FW(PLANE_SURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + surf_addr); + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + surf_addr); if (plane_state->scaler_id >= 0) skl_program_scaler(plane, crtc_state, plane_state); @@ -693,12 +707,12 @@ skl_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); if (icl_is_hdr_plane(dev_priv, plane_id)) - I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); skl_write_plane_wm(plane, crtc_state); - I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); - I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -718,7 +732,7 @@ skl_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; + ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; *pipe = plane->pipe; @@ -774,23 +788,36 @@ chv_update_csc(const struct intel_plane_state *plane_state) if (!fb->format->is_yuv) return; - I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - - I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); - I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); - I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); - I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); - I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8])); - - I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0)); - I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); - I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); - - I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); - I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); - I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + + intel_de_write_fw(dev_priv, SPCSCC01(plane_id), + SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); + intel_de_write_fw(dev_priv, SPCSCC23(plane_id), + SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); + intel_de_write_fw(dev_priv, SPCSCC45(plane_id), + SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); + intel_de_write_fw(dev_priv, SPCSCC67(plane_id), + SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); + intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8])); + + intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id), + SPCSC_IMAX(1023) | SPCSC_IMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id), + SPCSC_IMAX(512) | SPCSC_IMIN(-512)); + intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id), + SPCSC_IMAX(512) | SPCSC_IMIN(-512)); + + intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); } #define SIN_0 0 @@ -829,10 +856,10 @@ vlv_update_clrc(const struct intel_plane_state *plane_state) } /* FIXME these register are single buffered :( */ - I915_WRITE_FW(SPCLRC0(pipe, plane_id), - SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); - I915_WRITE_FW(SPCLRC1(pipe, plane_id), - SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); + intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id), + SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); + intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id), + SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); } static void @@ -1019,10 +1046,8 @@ static void vlv_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ /* The two end points are implicit (0.0 and 1.0) */ for (i = 1; i < 8 - 1; i++) - I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1), - gamma[i] << 16 | - gamma[i] << 8 | - gamma[i]); + intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1), + gamma[i] << 16 | gamma[i] << 8 | gamma[i]); } static void @@ -1055,32 +1080,37 @@ vlv_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPSTRIDE(pipe, plane_id), - plane_state->color_plane[0].stride); - I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w); - I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id), + (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0); if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) chv_update_csc(plane_state); if (key->flags) { - I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value); - I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask); - I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value); + intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id), + key->min_value); + intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id), + key->channel_mask); + intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id), + key->max_value); } - I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset); - I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x); + intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset); + intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl); - I915_WRITE_FW(SPSURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + sprsurf_offset); + intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl); + intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + sprsurf_offset); vlv_update_clrc(plane_state); vlv_update_gamma(plane_state); @@ -1099,8 +1129,8 @@ vlv_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPCNTR(pipe, plane_id), 0); - I915_WRITE_FW(SPSURF(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1120,7 +1150,7 @@ vlv_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; + ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; *pipe = plane->pipe; @@ -1424,19 +1454,17 @@ static void ivb_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ for (i = 0; i < 16; i++) - I915_WRITE_FW(SPRGAMC(pipe, i), - gamma[i] << 20 | - gamma[i] << 10 | - gamma[i]); - - I915_WRITE_FW(SPRGAMC16(pipe, 0), gamma[i]); - I915_WRITE_FW(SPRGAMC16(pipe, 1), gamma[i]); - I915_WRITE_FW(SPRGAMC16(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC(pipe, i), + gamma[i] << 20 | gamma[i] << 10 | gamma[i]); + + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]); i++; - I915_WRITE_FW(SPRGAMC17(pipe, 0), gamma[i]); - I915_WRITE_FW(SPRGAMC17(pipe, 1), gamma[i]); - I915_WRITE_FW(SPRGAMC17(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]); i++; } @@ -1476,25 +1504,27 @@ ivb_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride); - I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, SPRSTRIDE(pipe), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w); if (IS_IVYBRIDGE(dev_priv)) - I915_WRITE_FW(SPRSCALE(pipe), sprscale); + intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale); if (key->flags) { - I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value); - I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask); - I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value); + intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value); + intel_de_write_fw(dev_priv, SPRKEYMSK(pipe), + key->channel_mask); + intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value); } /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET * register */ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x); } else { - I915_WRITE_FW(SPRLINOFF(pipe), linear_offset); - I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset); + intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x); } /* @@ -1502,9 +1532,9 @@ ivb_update_plane(struct intel_plane *plane, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(SPRCTL(pipe), sprctl); - I915_WRITE_FW(SPRSURF(pipe), - intel_plane_ggtt_offset(plane_state) + sprsurf_offset); + intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl); + intel_de_write_fw(dev_priv, SPRSURF(pipe), + intel_plane_ggtt_offset(plane_state) + sprsurf_offset); ivb_update_gamma(plane_state); @@ -1521,11 +1551,11 @@ ivb_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPRCTL(pipe), 0); + intel_de_write_fw(dev_priv, SPRCTL(pipe), 0); /* Disable the scaler */ if (IS_IVYBRIDGE(dev_priv)) - I915_WRITE_FW(SPRSCALE(pipe), 0); - I915_WRITE_FW(SPRSURF(pipe), 0); + intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0); + intel_de_write_fw(dev_priv, SPRSURF(pipe), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1544,7 +1574,7 @@ ivb_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE; + ret = intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE; *pipe = plane->pipe; @@ -1710,10 +1740,8 @@ static void g4x_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ /* The two end points are implicit (0.0 and 1.0) */ for (i = 1; i < 8 - 1; i++) - I915_WRITE_FW(DVSGAMC_G4X(pipe, i - 1), - gamma[i] << 16 | - gamma[i] << 8 | - gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1), + gamma[i] << 16 | gamma[i] << 8 | gamma[i]); } static void ilk_sprite_linear_gamma(u16 gamma[17]) @@ -1741,14 +1769,12 @@ static void ilk_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ for (i = 0; i < 16; i++) - I915_WRITE_FW(DVSGAMC_ILK(pipe, i), - gamma[i] << 20 | - gamma[i] << 10 | - gamma[i]); - - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 0), gamma[i]); - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 1), gamma[i]); - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i), + gamma[i] << 20 | gamma[i] << 10 | gamma[i]); + + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]); i++; } @@ -1788,28 +1814,30 @@ g4x_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride); - I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); - I915_WRITE_FW(DVSSCALE(pipe), dvsscale); + intel_de_write_fw(dev_priv, DVSSTRIDE(pipe), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale); if (key->flags) { - I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value); - I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask); - I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value); + intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value); + intel_de_write_fw(dev_priv, DVSKEYMSK(pipe), + key->channel_mask); + intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value); } - I915_WRITE_FW(DVSLINOFF(pipe), linear_offset); - I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset); + intel_de_write_fw(dev_priv, DVSTILEOFF(pipe), (y << 16) | x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(DVSCNTR(pipe), dvscntr); - I915_WRITE_FW(DVSSURF(pipe), - intel_plane_ggtt_offset(plane_state) + dvssurf_offset); + intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr); + intel_de_write_fw(dev_priv, DVSSURF(pipe), + intel_plane_ggtt_offset(plane_state) + dvssurf_offset); if (IS_G4X(dev_priv)) g4x_update_gamma(plane_state); @@ -1829,10 +1857,10 @@ g4x_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DVSCNTR(pipe), 0); + intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0); /* Disable the scaler */ - I915_WRITE_FW(DVSSCALE(pipe), 0); - I915_WRITE_FW(DVSSURF(pipe), 0); + intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0); + intel_de_write_fw(dev_priv, DVSSURF(pipe), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1851,7 +1879,7 @@ g4x_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE; + ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE; *pipe = plane->pipe; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH RESEND 6/6] drm/i915/pm: use intel de functions for forcewake register access 2020-01-23 13:59 [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access Jani Nikula ` (3 preceding siblings ...) 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 5/6] drm/i915/sprite: " Jani Nikula @ 2020-01-23 14:00 ` Jani Nikula 2020-01-23 14:16 ` Ville Syrjälä 2020-01-23 14:10 ` [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore " Ville Syrjälä ` (3 subsequent siblings) 8 siblings, 1 reply; 16+ messages in thread From: Jani Nikula @ 2020-01-23 14:00 UTC (permalink / raw) To: intel-gfx; +Cc: Jani Nikula Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and switch to using intel_de_read_fw() and intel_de_write_fw(), respectively. No functional changes. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 36d158d6c5b2..1cf909d8347b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5061,9 +5061,10 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, const struct skl_ddb_entry *entry) { if (entry->end) - I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start); + intel_de_write_fw(dev_priv, reg, + (entry->end - 1) << 16 | entry->start); else - I915_WRITE_FW(reg, 0); + intel_de_write_fw(dev_priv, reg, 0); } static void skl_write_wm_level(struct drm_i915_private *dev_priv, @@ -5079,7 +5080,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv, val |= level->plane_res_b; val |= level->plane_res_l << PLANE_WM_LINES_SHIFT; - I915_WRITE_FW(reg, val); + intel_de_write_fw(dev_priv, reg, val); } void skl_write_plane_wm(struct intel_plane *plane, -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH RESEND 6/6] drm/i915/pm: use intel de functions for forcewake register access 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 6/6] drm/i915/pm: " Jani Nikula @ 2020-01-23 14:16 ` Ville Syrjälä 2020-01-23 14:34 ` Chris Wilson 0 siblings, 1 reply; 16+ messages in thread From: Ville Syrjälä @ 2020-01-23 14:16 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Thu, Jan 23, 2020 at 04:00:04PM +0200, Jani Nikula wrote: > Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and > switch to using intel_de_read_fw() and intel_de_write_fw(), > respectively. > > No functional changes. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Only a few oddities spotted. Overall series lgtm For all Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 36d158d6c5b2..1cf909d8347b 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5061,9 +5061,10 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, > const struct skl_ddb_entry *entry) > { > if (entry->end) > - I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start); > + intel_de_write_fw(dev_priv, reg, > + (entry->end - 1) << 16 | entry->start); > else > - I915_WRITE_FW(reg, 0); > + intel_de_write_fw(dev_priv, reg, 0); > } > > static void skl_write_wm_level(struct drm_i915_private *dev_priv, > @@ -5079,7 +5080,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv, > val |= level->plane_res_b; > val |= level->plane_res_l << PLANE_WM_LINES_SHIFT; > > - I915_WRITE_FW(reg, val); > + intel_de_write_fw(dev_priv, reg, val); > } > > void skl_write_plane_wm(struct intel_plane *plane, > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH RESEND 6/6] drm/i915/pm: use intel de functions for forcewake register access 2020-01-23 14:16 ` Ville Syrjälä @ 2020-01-23 14:34 ` Chris Wilson 2020-01-27 9:18 ` Jani Nikula 0 siblings, 1 reply; 16+ messages in thread From: Chris Wilson @ 2020-01-23 14:34 UTC (permalink / raw) To: Jani Nikula, Ville Syrjälä; +Cc: intel-gfx Quoting Ville Syrjälä (2020-01-23 14:16:46) > On Thu, Jan 23, 2020 at 04:00:04PM +0200, Jani Nikula wrote: > > Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and > > switch to using intel_de_read_fw() and intel_de_write_fw(), > > respectively. > > > > No functional changes. > > > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Only a few oddities spotted. Overall series lgtm Concurred, checkpatch is going to have some very stern words regarding some of those lines! > For all > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> +1 Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH RESEND 6/6] drm/i915/pm: use intel de functions for forcewake register access 2020-01-23 14:34 ` Chris Wilson @ 2020-01-27 9:18 ` Jani Nikula 0 siblings, 0 replies; 16+ messages in thread From: Jani Nikula @ 2020-01-27 9:18 UTC (permalink / raw) To: Chris Wilson, Ville Syrjälä; +Cc: intel-gfx On Thu, 23 Jan 2020, Chris Wilson <chris@chris-wilson.co.uk> wrote: > Quoting Ville Syrjälä (2020-01-23 14:16:46) >> On Thu, Jan 23, 2020 at 04:00:04PM +0200, Jani Nikula wrote: >> > Move away from I915_READ_FW() and I915_WRITE_FW() in display code, and >> > switch to using intel_de_read_fw() and intel_de_write_fw(), >> > respectively. >> > >> > No functional changes. >> > >> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> >> Only a few oddities spotted. Overall series lgtm > > Concurred, checkpatch is going to have some very stern words regarding > some of those lines! > >> For all >> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > +1 > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Thanks for the reviews, I pushed the ones *not* in display/ with hopes we'll do the mass conversion there (the other series). BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access 2020-01-23 13:59 [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access Jani Nikula ` (4 preceding siblings ...) 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 6/6] drm/i915/pm: " Jani Nikula @ 2020-01-23 14:10 ` Ville Syrjälä 2020-01-23 14:18 ` Jani Nikula 2020-01-23 14:33 ` Chris Wilson 2020-01-23 23:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [RESEND,1/6] " Patchwork ` (2 subsequent siblings) 8 siblings, 2 replies; 16+ messages in thread From: Ville Syrjälä @ 2020-01-23 14:10 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Thu, Jan 23, 2020 at 03:59:59PM +0200, Jani Nikula wrote: > Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using > intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. > > No functional changes. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_csr.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c > index ae25960f74e0..6a408e11a3de 100644 > --- a/drivers/gpu/drm/i915/intel_csr.c > +++ b/drivers/gpu/drm/i915/intel_csr.c > @@ -315,7 +315,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv) > preempt_disable(); > > for (i = 0; i < fw_size; i++) > - I915_WRITE_FW(CSR_PROGRAM(i), payload[i]); > + intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i), > + payload[i]); Why uncore instead of de? > > preempt_enable(); > > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access 2020-01-23 14:10 ` [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore " Ville Syrjälä @ 2020-01-23 14:18 ` Jani Nikula 2020-01-23 14:33 ` Chris Wilson 1 sibling, 0 replies; 16+ messages in thread From: Jani Nikula @ 2020-01-23 14:18 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx On Thu, 23 Jan 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Thu, Jan 23, 2020 at 03:59:59PM +0200, Jani Nikula wrote: >> Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using >> intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. >> >> No functional changes. >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/intel_csr.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c >> index ae25960f74e0..6a408e11a3de 100644 >> --- a/drivers/gpu/drm/i915/intel_csr.c >> +++ b/drivers/gpu/drm/i915/intel_csr.c >> @@ -315,7 +315,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv) >> preempt_disable(); >> >> for (i = 0; i < fw_size; i++) >> - I915_WRITE_FW(CSR_PROGRAM(i), payload[i]); >> + intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i), >> + payload[i]); > > Why uncore instead of de? Good question! :) BR, Jani. > >> >> preempt_enable(); >> >> -- >> 2.20.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access 2020-01-23 14:10 ` [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore " Ville Syrjälä 2020-01-23 14:18 ` Jani Nikula @ 2020-01-23 14:33 ` Chris Wilson 1 sibling, 0 replies; 16+ messages in thread From: Chris Wilson @ 2020-01-23 14:33 UTC (permalink / raw) To: Jani Nikula, Ville Syrjälä; +Cc: intel-gfx Quoting Ville Syrjälä (2020-01-23 14:10:34) > On Thu, Jan 23, 2020 at 03:59:59PM +0200, Jani Nikula wrote: > > Move away from I915_READ_FW() and I915_WRITE_FW() and switch to using > > intel_uncore_read_fw() and intel_uncore_write_fw(), respectively. > > > > No functional changes. > > > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > --- > > drivers/gpu/drm/i915/intel_csr.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c > > index ae25960f74e0..6a408e11a3de 100644 > > --- a/drivers/gpu/drm/i915/intel_csr.c > > +++ b/drivers/gpu/drm/i915/intel_csr.c > > @@ -315,7 +315,8 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv) > > preempt_disable(); > > > > for (i = 0; i < fw_size; i++) > > - I915_WRITE_FW(CSR_PROGRAM(i), payload[i]); > > + intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i), > > + payload[i]); > > Why uncore instead of de? Outside of display/ It might be very well worth moving intel_csr.c under the auspices of display powermanagement. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [RESEND,1/6] drm/i915/dmc: use intel uncore functions for forcewake register access 2020-01-23 13:59 [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access Jani Nikula ` (5 preceding siblings ...) 2020-01-23 14:10 ` [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore " Ville Syrjälä @ 2020-01-23 23:01 ` Patchwork 2020-01-23 23:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-01-25 15:30 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 8 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2020-01-23 23:01 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: series starting with [RESEND,1/6] drm/i915/dmc: use intel uncore functions for forcewake register access URL : https://patchwork.freedesktop.org/series/72476/ State : warning == Summary == $ dim checkpatch origin/drm-tip 68bf5a21a662 drm/i915/dmc: use intel uncore functions for forcewake register access 668006a8978f drm/i915/display: use intel de functions for forcewake register access d9cd42314a64 drm/i915/irq: use intel de functions for forcewake register access -:91: WARNING:LONG_LINE: line over 100 characters #91: FILE: drivers/gpu/drm/i915/i915_irq.c:831: + position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; total: 0 errors, 1 warnings, 0 checks, 70 lines checked 686aa5c7b1c6 drm/i915/gmbus: use intel de functions for forcewake register access -:129: WARNING:LONG_LINE: line over 100 characters #129: FILE: drivers/gpu/drm/i915/display/intel_gmbus.c:414: + gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); -:163: WARNING:LONG_LINE: line over 100 characters #163: FILE: drivers/gpu/drm/i915/display/intel_gmbus.c:493: + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); total: 0 errors, 2 warnings, 0 checks, 205 lines checked 9705f531210a drm/i915/sprite: use intel de functions for forcewake register access -:151: WARNING:LONG_LINE: line over 100 characters #151: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:668: + (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); total: 0 errors, 1 warnings, 0 checks, 508 lines checked c730e340b56a drm/i915/pm: use intel de functions for forcewake register access _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RESEND,1/6] drm/i915/dmc: use intel uncore functions for forcewake register access 2020-01-23 13:59 [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access Jani Nikula ` (6 preceding siblings ...) 2020-01-23 23:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [RESEND,1/6] " Patchwork @ 2020-01-23 23:30 ` Patchwork 2020-01-25 15:30 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 8 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2020-01-23 23:30 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: series starting with [RESEND,1/6] drm/i915/dmc: use intel uncore functions for forcewake register access URL : https://patchwork.freedesktop.org/series/72476/ State : success == Summary == CI Bug Log - changes from CI_DRM_7804 -> Patchwork_16238 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/index.html Known issues ------------ Here are the changes found in Patchwork_16238 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_param@basic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([CI#94] / [i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-tgl-y/igt@gem_ctx_param@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-tgl-y/igt@gem_ctx_param@basic.html * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6700k2: [PASS][3] -> [DMESG-WARN][4] ([i915#889]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_pm_rpm@module-reload: - fi-skl-6600u: [PASS][5] -> [DMESG-WARN][6] ([i915#889]) +23 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html - fi-skl-6700k2: [PASS][7] -> [INCOMPLETE][8] ([i915#151]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live_gem_contexts: - fi-byt-j1900: [PASS][9] -> [DMESG-FAIL][10] ([i915#722]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_gt_lrc: - fi-skl-6600u: [PASS][11] -> [DMESG-FAIL][12] ([i915#889]) +7 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-skl-6600u/igt@i915_selftest@live_gt_lrc.html #### Possible fixes #### * igt@gem_close_race@basic-threads: - fi-byt-j1900: [TIMEOUT][13] ([fdo#112271] / [i915#816]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-byt-j1900/igt@gem_close_race@basic-threads.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-byt-j1900/igt@gem_close_race@basic-threads.html * igt@gem_exec_parallel@fds: - fi-byt-j1900: [TIMEOUT][15] ([fdo#112271]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-byt-j1900/igt@gem_exec_parallel@fds.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-byt-j1900/igt@gem_exec_parallel@fds.html * igt@gem_exec_suspend@basic-s3: - fi-cml-s: [INCOMPLETE][17] ([i915#283]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-cml-s/igt@gem_exec_suspend@basic-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-cml-s/igt@gem_exec_suspend@basic-s3.html * igt@gem_exec_suspend@basic-s4-devices: - fi-tgl-y: [FAIL][19] ([CI#94]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-tgl-y/igt@gem_exec_suspend@basic-s4-devices.html * igt@i915_selftest@live_blt: - fi-hsw-4770: [DMESG-FAIL][21] ([i915#725]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-hsw-4770/igt@i915_selftest@live_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@kms_addfb_basic@bad-pitch-0: - fi-tgl-y: [DMESG-WARN][23] ([CI#94] / [i915#402]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-tgl-y/igt@kms_addfb_basic@bad-pitch-0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-tgl-y/igt@kms_addfb_basic@bad-pitch-0.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][25] ([fdo#111096] / [i915#323]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html #### Warnings #### * igt@i915_selftest@live_blt: - fi-hsw-4770r: [DMESG-FAIL][27] ([i915#725]) -> [DMESG-FAIL][28] ([i915#553] / [i915#725]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/fi-hsw-4770r/igt@i915_selftest@live_blt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/fi-hsw-4770r/igt@i915_selftest@live_blt.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816 [i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889 Participating hosts (49 -> 43) ------------------------------ Additional (2): fi-hsw-peppy fi-snb-2600 Missing (8): fi-cml-u2 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-n2820 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7804 -> Patchwork_16238 CI-20190529: 20190529 CI_DRM_7804: 74ed9d57007ab848a57ec6d785de4187b70acd9b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5382: 8dbe5ce61baa2d563d4dd7c56a018bb1e1077467 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16238: c730e340b56aec0284f86d7db38be3a482d764f2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c730e340b56a drm/i915/pm: use intel de functions for forcewake register access 9705f531210a drm/i915/sprite: use intel de functions for forcewake register access 686aa5c7b1c6 drm/i915/gmbus: use intel de functions for forcewake register access d9cd42314a64 drm/i915/irq: use intel de functions for forcewake register access 668006a8978f drm/i915/display: use intel de functions for forcewake register access 68bf5a21a662 drm/i915/dmc: use intel uncore functions for forcewake register access == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [RESEND,1/6] drm/i915/dmc: use intel uncore functions for forcewake register access 2020-01-23 13:59 [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access Jani Nikula ` (7 preceding siblings ...) 2020-01-23 23:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2020-01-25 15:30 ` Patchwork 8 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2020-01-25 15:30 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: series starting with [RESEND,1/6] drm/i915/dmc: use intel uncore functions for forcewake register access URL : https://patchwork.freedesktop.org/series/72476/ State : success == Summary == CI Bug Log - changes from CI_DRM_7804_full -> Patchwork_16238_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_16238_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +9 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb4/igt@gem_busy@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb8/igt@gem_busy@busy-vcs1.html * igt@gem_ctx_persistence@bcs0-mixed-process: - shard-iclb: [PASS][3] -> [FAIL][4] ([i915#679]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb2/igt@gem_ctx_persistence@bcs0-mixed-process.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb2/igt@gem_ctx_persistence@bcs0-mixed-process.html - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#679]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-tglb5/igt@gem_ctx_persistence@bcs0-mixed-process.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-tglb7/igt@gem_ctx_persistence@bcs0-mixed-process.html * igt@gem_ctx_persistence@vcs1-mixed: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb4/igt@gem_ctx_persistence@vcs1-mixed.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb7/igt@gem_ctx_persistence@vcs1-mixed.html * igt@gem_exec_schedule@in-order-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb5/igt@gem_exec_schedule@in-order-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb1/igt@gem_exec_schedule@in-order-bsd.html * igt@gem_exec_schedule@pi-userfault-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([i915#677]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb8/igt@gem_exec_schedule@pi-userfault-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb4/igt@gem_exec_schedule@pi-userfault-bsd.html * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing: - shard-kbl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103665]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-kbl1/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-kbl6/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive: - shard-kbl: [PASS][15] -> [INCOMPLETE][16] ([fdo#103665] / [i915#640]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html * igt@gem_persistent_relocs@forked-thrash-inactive: - shard-apl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103927]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-apl7/igt@gem_persistent_relocs@forked-thrash-inactive.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-apl6/igt@gem_persistent_relocs@forked-thrash-inactive.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#69]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-skl2/igt@gem_softpin@noreloc-s3.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-skl4/igt@gem_softpin@noreloc-s3.html * igt@gem_tiled_blits@normal: - shard-hsw: [PASS][21] -> [FAIL][22] ([i915#818]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-hsw1/igt@gem_tiled_blits@normal.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-hsw7/igt@gem_tiled_blits@normal.html * igt@i915_pm_rps@waitboost: - shard-iclb: [PASS][23] -> [FAIL][24] ([i915#413]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb4/igt@i915_pm_rps@waitboost.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb7/igt@i915_pm_rps@waitboost.html * igt@i915_selftest@mock_requests: - shard-snb: [PASS][25] -> [INCOMPLETE][26] ([i915#82]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-snb6/igt@i915_selftest@mock_requests.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-snb4/igt@i915_selftest@mock_requests.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-iclb: [PASS][27] -> [INCOMPLETE][28] ([i915#140]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb2/igt@kms_fbcon_fbt@fbc-suspend.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb8/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][29] -> [DMESG-WARN][30] ([i915#109]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-skl7/igt@kms_fbcon_fbt@psr-suspend.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-skl9/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#180]) +5 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-tglb: [PASS][33] -> [FAIL][34] ([i915#49]) +4 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][37] -> [FAIL][38] ([fdo#108145]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109642] / [fdo#111068]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb2/igt@kms_psr2_su@frontbuffer.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb5/igt@kms_psr2_su@frontbuffer.html * igt@kms_setmode@basic: - shard-apl: [PASS][41] -> [FAIL][42] ([i915#31]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-apl4/igt@kms_setmode@basic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-apl1/igt@kms_setmode@basic.html * igt@prime_busy@hang-bsd2: - shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109276]) +16 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb1/igt@prime_busy@hang-bsd2.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb7/igt@prime_busy@hang-bsd2.html * igt@prime_mmap_coherency@ioctl-errors: - shard-hsw: [PASS][45] -> [INCOMPLETE][46] ([i915#61]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-hsw5/igt@prime_mmap_coherency@ioctl-errors.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-hsw8/igt@prime_mmap_coherency@ioctl-errors.html #### Possible fixes #### * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [SKIP][47] ([fdo#109276] / [fdo#112080]) -> [PASS][48] +3 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb5/igt@gem_ctx_isolation@vcs1-dirty-create.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html * igt@gem_ctx_persistence@rcs0-mixed-process: - shard-glk: [FAIL][49] ([i915#679]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-glk3/igt@gem_ctx_persistence@rcs0-mixed-process.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-glk6/igt@gem_ctx_persistence@rcs0-mixed-process.html * igt@gem_ctx_persistence@vecs0-mixed-process: - shard-tglb: [FAIL][51] ([i915#679]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-tglb5/igt@gem_ctx_persistence@vecs0-mixed-process.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-tglb7/igt@gem_ctx_persistence@vecs0-mixed-process.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [SKIP][53] ([fdo#112146]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb7/igt@gem_exec_async@concurrent-writes-bsd.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [SKIP][55] ([i915#677]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb4/igt@gem_exec_schedule@pi-distinct-iova-bsd.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb7/igt@gem_exec_schedule@pi-distinct-iova-bsd.html * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing: - shard-hsw: [INCOMPLETE][57] ([i915#61]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-hsw1/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-hsw2/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html - shard-iclb: [INCOMPLETE][59] ([i915#140]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb4/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb4/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-glk: [INCOMPLETE][61] ([i915#58] / [k.org#198133]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-glk7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-glk8/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_persistent_relocs@forked-thrashing: - shard-kbl: [INCOMPLETE][63] ([fdo#103665]) -> [PASS][64] +2 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-kbl6/igt@gem_persistent_relocs@forked-thrashing.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-kbl3/igt@gem_persistent_relocs@forked-thrashing.html * igt@i915_selftest@mock_requests: - shard-apl: [INCOMPLETE][65] ([fdo#103927]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-apl7/igt@i915_selftest@mock_requests.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-apl4/igt@i915_selftest@mock_requests.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +5 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@kms_color@pipe-b-ctm-0-75: - shard-skl: [DMESG-WARN][69] ([i915#109]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-skl2/igt@kms_color@pipe-b-ctm-0-75.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-skl3/igt@kms_color@pipe-b-ctm-0-75.html * igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent: - shard-skl: [FAIL][71] ([i915#54]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html * igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled: - shard-skl: [FAIL][73] ([i915#52] / [i915#54]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-skl3/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [FAIL][75] ([i915#79]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [INCOMPLETE][77] ([i915#221]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-skl1/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-tglb: [FAIL][79] ([i915#49]) -> [PASS][80] +2 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [DMESG-WARN][81] ([i915#180]) -> [PASS][82] +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][83] ([fdo#108145]) -> [PASS][84] [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt@kms_psr@psr2_sprite_plane_onoff: - shard-iclb: [SKIP][85] ([fdo#109441]) -> [PASS][86] [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb1/igt@kms_psr@psr2_sprite_plane_onoff.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html * igt@perf_pmu@busy-check-all-vcs1: - shard-iclb: [SKIP][87] ([fdo#112080]) -> [PASS][88] +2 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb7/igt@perf_pmu@busy-check-all-vcs1.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb1/igt@perf_pmu@busy-check-all-vcs1.html * igt@prime_vgem@wait-bsd2: - shard-iclb: [SKIP][89] ([fdo#109276]) -> [PASS][90] +9 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb6/igt@prime_vgem@wait-bsd2.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb2/igt@prime_vgem@wait-bsd2.html #### Warnings #### * igt@gem_ctx_isolation@vcs1-nonpriv-switch: - shard-iclb: [SKIP][91] ([fdo#109276] / [fdo#112080]) -> [FAIL][92] ([IGT#28]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb7/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html * igt@i915_selftest@live_blt: - shard-hsw: [DMESG-FAIL][93] ([i915#770]) -> [DMESG-FAIL][94] ([i915#725]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-hsw8/igt@i915_selftest@live_blt.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-hsw2/igt@i915_selftest@live_blt.html * igt@kms_atomic_transition@3x-modeset-transitions: - shard-hsw: [SKIP][95] ([fdo#109271] / [i915#439]) -> [SKIP][96] ([fdo#109271]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-hsw2/igt@kms_atomic_transition@3x-modeset-transitions.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-hsw5/igt@kms_atomic_transition@3x-modeset-transitions.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][97] ([fdo#109349]) -> [DMESG-WARN][98] ([fdo#107724]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7804/shard-iclb1/igt@kms_dp_dsc@basic-dsc-enable-edp.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413 [i915#439]: https://gitlab.freedesktop.org/drm/intel/issues/439 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#640]: https://gitlab.freedesktop.org/drm/intel/issues/640 [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677 [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#818]: https://gitlab.freedesktop.org/drm/intel/issues/818 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7804 -> Patchwork_16238 CI-20190529: 20190529 CI_DRM_7804: 74ed9d57007ab848a57ec6d785de4187b70acd9b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5382: 8dbe5ce61baa2d563d4dd7c56a018bb1e1077467 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16238: c730e340b56aec0284f86d7db38be3a482d764f2 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16238/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-01-27 9:27 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-01-23 13:59 [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore functions for forcewake register access Jani Nikula 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 2/6] drm/i915/display: use intel de " Jani Nikula 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 3/6] drm/i915/irq: " Jani Nikula 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 4/6] drm/i915/gmbus: " Jani Nikula 2020-01-23 14:13 ` Ville Syrjälä 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 5/6] drm/i915/sprite: " Jani Nikula 2020-01-23 14:00 ` [Intel-gfx] [PATCH RESEND 6/6] drm/i915/pm: " Jani Nikula 2020-01-23 14:16 ` Ville Syrjälä 2020-01-23 14:34 ` Chris Wilson 2020-01-27 9:18 ` Jani Nikula 2020-01-23 14:10 ` [Intel-gfx] [PATCH RESEND 1/6] drm/i915/dmc: use intel uncore " Ville Syrjälä 2020-01-23 14:18 ` Jani Nikula 2020-01-23 14:33 ` Chris Wilson 2020-01-23 23:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [RESEND,1/6] " Patchwork 2020-01-23 23:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-01-25 15:30 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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